JPH0582609B2 - - Google Patents

Info

Publication number
JPH0582609B2
JPH0582609B2 JP61216592A JP21659286A JPH0582609B2 JP H0582609 B2 JPH0582609 B2 JP H0582609B2 JP 61216592 A JP61216592 A JP 61216592A JP 21659286 A JP21659286 A JP 21659286A JP H0582609 B2 JPH0582609 B2 JP H0582609B2
Authority
JP
Japan
Prior art keywords
partial product
group
digit
intermediate partial
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61216592A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6371729A (ja
Inventor
Tamotsu Nishama
Shigero Kuninobu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61216592A priority Critical patent/JPS6371729A/ja
Priority to US07/074,971 priority patent/US4864528A/en
Priority to US07/086,967 priority patent/US4866657A/en
Publication of JPS6371729A publication Critical patent/JPS6371729A/ja
Priority to US03/239,243 priority patent/US5031136A/en
Priority to US07/599,275 priority patent/US5153847A/en
Publication of JPH0582609B2 publication Critical patent/JPH0582609B2/ja
Granted legal-status Critical Current

Links

JP61216592A 1986-06-27 1986-09-12 演算処理装置 Granted JPS6371729A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP61216592A JPS6371729A (ja) 1986-09-12 1986-09-12 演算処理装置
US07/074,971 US4864528A (en) 1986-07-18 1987-07-17 Arithmetic processor and multiplier using redundant signed digit arithmetic
US07/086,967 US4866657A (en) 1986-07-18 1987-08-18 Adder circuitry utilizing redundant signed digit operands
US03/239,243 US5031136A (en) 1986-06-27 1990-05-07 Signed-digit arithmetic processing units with binary operands
US07/599,275 US5153847A (en) 1986-06-27 1990-10-16 Arithmetic processor using signed digit representation of internal operands

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61216592A JPS6371729A (ja) 1986-09-12 1986-09-12 演算処理装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP5112842A Division JPH07122847B2 (ja) 1993-05-14 1993-05-14 演算処理装置

Publications (2)

Publication Number Publication Date
JPS6371729A JPS6371729A (ja) 1988-04-01
JPH0582609B2 true JPH0582609B2 (OSRAM) 1993-11-19

Family

ID=16690832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61216592A Granted JPS6371729A (ja) 1986-06-27 1986-09-12 演算処理装置

Country Status (1)

Country Link
JP (1) JPS6371729A (OSRAM)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6410325A (en) * 1987-07-03 1989-01-13 Matsushita Graphic Communic Binary multiplication device
JP2606326B2 (ja) * 1988-10-25 1997-04-30 日本電気株式会社 乗算器

Also Published As

Publication number Publication date
JPS6371729A (ja) 1988-04-01

Similar Documents

Publication Publication Date Title
US4864528A (en) Arithmetic processor and multiplier using redundant signed digit arithmetic
US4594678A (en) Digital parallel computing circuit for computing p=xy+z in a shortened time
JPH0555894B2 (OSRAM)
US4868777A (en) High speed multiplier utilizing signed-digit and carry-save operands
US4878192A (en) Arithmetic processor and divider using redundant signed digit arithmetic
Kalaiyarasi et al. Design of an efficient high speed radix-4 booth multiplier for both signed and unsigned numbers
Asadi et al. Towards designing quantum reversible ternary multipliers
US4866655A (en) Arithmetic processor and divider using redundant signed digit
JPH0619685A (ja) 並列乗算回路
US4873660A (en) Arithmetic processor using redundant signed digit arithmetic
US5115408A (en) High speed multiplier
US4935892A (en) Divider and arithmetic processing units using signed digit operands
JPH0582609B2 (OSRAM)
US3462589A (en) Parallel digital arithmetic unit utilizing a signed-digit format
EP0326414B1 (en) High speed multiplier
US5031136A (en) Signed-digit arithmetic processing units with binary operands
JPH06230933A (ja) 演算処理装置
JP2682142B2 (ja) 乗算装置
Sahu et al. Improved redundant binary adder realization in FPGA
Reddy et al. A high speed, high Radix 32-bit Redundant parallel multiplier
Castellanos et al. Decimal partial product generation architectures
JPH0652500B2 (ja) 演算処理装置
JPH0610787B2 (ja) 乗算処理装置
JP2563473B2 (ja) ２進演算器
JPH0528407B2 (OSRAM)

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term