JPH0581186A - Serial data transfer control circuit - Google Patents

Abstract

PURPOSE:To provide a transfer control circuit for highway data which eliminates 5 bit delay by reading the data out of serial data so as to process it in parallel with detecting of head coincidence. CONSTITUTION:A detection reading control part 3 which detects coincidence for each bit between a highway data header frame and the header frame externally set in advance is provided. When all the bits coincide with each other, it outputs a coincidence detection signal, and when inconsistency is found, it outputs an inconsistency detection signal. A memory part 4 which outputs a stored data if the coincidence detection signal is given by the detection reading control part 3, a selection part 5 which selects and outputs either the highway data or the data in the memory part 4 based upon the control signal from the detection reading control part 3 and the second delay part which receives the data out of the selection part 5 and delay it by a specified bits are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transfer control circuit for replacing data information stored in a memory with header information with data information of input serial data and outputting the same.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a conventional serial data transfer control circuit. Reference numerals 1 and 9 are 2-bit flip-flops for delaying input data by 1 bit. Reference numeral 2 is a 5-bit delay circuit which incorporates a 5-bit shift register 2a and a 5-bit shift register 2b. Data is delayed by 5 bits,
Reference numeral 3 is a header detection unit for detecting a match between a highway data header and a header input from the outside, and 4 is a read control unit for a match pulse (D2 in FIG. 8).
1)) to control the reading of the data stored in the ROM 5, and 5 is a ROM that receives the control signal for reading and reads and outputs the stored data. , 7 are P / S converters, and 8
A bit flip-flop 7a and an 8-bit shift register 7b are built in to convert parallel data into serial data. Reference numeral 8 denotes a selector which receives a control signal from the read control unit 4 (see D35 in FIG. 8). Either the output data of the 5-bit delay circuit 10 or the output data of the P / S converter 7 is selected.

FIG. 8 is a time chart of a conventional highway data transfer control circuit. FIG. 9 is a circuit diagram of a header detection unit of a conventional highway data transfer control circuit. 3a and 3c are 4-bit shift register circuits, 3b is a comparator, and 3d is an AND circuit.

FIG. 10 is a circuit diagram of a read control section of a conventional highway data transfer circuit.
-K flip-flop circuit, 4b is a 4-bit counter circuit, 4c is a decoder circuit, 4d is a 5-bit shift register circuit, 4e, 4f are T flip-flop circuits, 4g is an 8-bit counter. Circuit.

Next, the operation of the conventional highway data transfer control circuit will be described. The 2-bit flip-flop 1 in FIG. 7 delays each of the input frame data (FRMPI) and highway data (HWDTI) by one bit based on the cycle of the clock pulse (CLK) (D1, FIG. 8). (See D2), and outputs to the 5-bit delay circuit 2 and the header detection unit 3.

The header detector 3 compares the header input from the outside with the header of the highway data (HWDTI) from the 2-bit flip-flop 1 on a bit-by-bit basis based on the frame data from the 2-bit flip-flop 1. Then, if they match, a matching pulse (D21 in FIG. 8) is output to the read control unit 4. The read control unit 4 receives the coincidence pulse (D21 in FIG. 8) from the header detection unit 3, and based on the cycle of the clock pulse (CLK), a frame pulse (D25 in FIG. 8) and a read control signal (see FIG. 8). 8 D29) to the ROM 5, and frame pulses (D25 and D27 in FIG. 8) to the 8-bit flip-flop 7a and 8-bit shift register 7b, respectively.
The selection control signal (D35 in FIG. 8) is output to the selector 8.

The ROM 5 receives the control signal and outputs the stored data to the 8-bit flip-flop 7a of the P / S converter 7. 8-bit flip-flop 7
The data a received from the ROM 5 is used as a clock based on the frame pulse (D25 in FIG. 8) from the read control unit 4 to input 1 of the input 8-bit parallel data.
When each bit is delayed by 8 bits, 16 bits of parallel data having an 8-bit interval are obtained and output to the 8-bit shift register 7b.

The 8-bit shift register 7b successively reads out eight parallel data having 8-bit intervals and successively outputs 8-bit data based on the input of the frame pulse (D27 in FIG. 8) and the clock pulse (CLK) from the control unit. 16 bits of the serial data are output to the selector 8. The 5-bit delay circuit 2 receives the frame pulse (D1 in FIG. 8) and the highway data (HWDTI) (D2 in FIG. 8) from the 2-bit flip-flop 1, and
Highway data (HWDTI) (D2 in FIG. 8) in the 5-bit shift register 2a and frame pulse (D2 in FIG. 8) in the 5-bit shift register 2b of the 5-bit delay circuit 2.
And a clock pulse (CLK) is input to each 5-bit shift register. The 5-bit shift register 2a delays the highway data (HWDTLI) by 5 bits based on the input of the clock pulse (CLK) (see D34 in FIG. 8) and outputs it to the 0 terminal of the selector 8. The 5-bit shift register 2b delays the frame pulse (D2 in FIG. 8) by 5 bits based on the input of the clock pulse (CLK) (see D33 in FIG. 8) and outputs it to the 2-bit flip-flop circuit 9. Selector 8
Is a selection control signal (D3 in FIG. 8) from the read control unit 4.
5)), the data input to terminal 1 or terminal 0
The selected data is output to the 2-bit flip-flop circuit 9. The 2-bit flip-flop circuit 9 respectively receives the frame pulse (see D33 in FIG. 8) from the 5-bit delay circuit 2 and the highway data selected by the selector 8 as a clock pulse (CLK).
Based on the above, it is delayed by one bit and output.

Next, as shown in the circuit diagram of the header detecting section of serial FIG. 9, a header which is parallel data from the outside is input to the comparator 3b, and the 4-bit shift register 3 is supplied.
At a, highway data (HWDT) D2 is converted from serial data to parallel data based on the clock pulse, and is output to the comparator 3b. The comparator 3b compares the header from the outside with the header which is parallel data from the 4-bit shift register 3a bit by bit, and outputs a pulse to one terminal of the AND circuit 3d if all bits match. ..

The 4-bit shift register 3c delays the frame pulse (FRMP) by 4 bits based on the clock pulse and outputs it to the other terminal of the AND circuit 3d. When the output pulse of the comparator 3b and the output pulse of the 4-bit shift register 3c are input, the AND circuit 3d outputs a coincidence pulse (see D21 in FIG. 8) to the read control unit 4.

In the read control unit 4 in FIG. 10, the coincidence pulse (see D21 in FIG. 8), the clock pulse, and the decoder 4 are used.
The output pulse from the F terminal of c is input to the JK flip-flop circuit 4a and the EN of the 4-bit counter circuit 4b is input.
The output pulse of the JK flip-flop circuit 4a (see D22 in FIG. 8) is output to the terminal. A match pulse (see D21 in FIG. 8) is output to the LD terminal of the 4-bit counter circuit 4b, and a clock pulse is output to the CK terminal.

The 4-bit counter circuit 4b receives the pulse of D22 and the clock pulse (CLK), and encodes a 4-bit coded pulse (D23 of FIG. 8) indicating the count.
Reference) to the decoder 4c. Further, in the 4-bit pulse counter circuit 4b, when the pulse of D21 is input to the LD terminal, a 4-bit initialization pulse (for example, "0000") is output to the decoder 4c from the grounded D terminal.

The 5-bit shift register circuit 4d has a D2
The second pulse is delayed by 5 bits based on the clock pulse (see D35 in FIG. 8), and the control signal of the selector 8 is output.

The decoder circuit 4c receives the data of the 4-bit counter circuit 4b (see D23 of FIG. 8), and inputs it to the OR circuit 4k which receives the bit pulses of the hexadecimal count numbers 1 and 9 of the data. If either one of the pulses is input, it is output to the T flip-flop circuit 4e (see D24 in FIG. 8).

Further, the decoder circuit 4c receives the data of the 4-bit counter circuit 4b (see D23 of FIG. 8), and receives the hexadecimal count number 3 and the bit pulse of B of the data from the OR circuit. If either pulse is input to 4k, the T flip-flop circuit 4f
To the OR circuit 4m which receives the bit pulse of the count number 7 and F as an input (see D26 of FIG. 8), and inputs either pulse, the 8-bit counter circuit 4g
(See D28 in FIG. 8).

The T flip-flop circuit 4e inverts the input pulse D24 at the trailing edge of the pulse (see FIG. 8).
D25) of the P / S converter 7 and the CK terminal of the 8-bit flip-flop 7a of the P / S converter 7 and the XOER terminal of the ROM 5. The T flip-flop circuit 4f inverts the input pulse D26 at the trailing edge of the pulse (D2 in FIG. 8).
7), the 8-bit shift register 7 of the P / S converter 7
output to b. The 8-bit counter circuit 4g receives the pulse from the decoder circuit 4c via the OR circuit 4m and outputs it to the ADDR terminal of the ROM 5 (see D29 in FIG. 8) based on the clock pulse.

The ROM 5 receives the inputted D25 pulse and D29 pulse and stores the stored data (FIG. 8).
Output D30) to the P / S conversion unit 7. The 8-bit shift register circuit 7a of the P / S conversion unit 7 receives the pulse of D30 and the pulse of D25 and delays the pulse of D30 for each pulse of each bit based on the clock pulse of the pulse of D25. A pulse having a pulse width of 8 bits (D31 in FIG. 8) is transferred to the 8-bit shift register circuit 7
Output to b.

The 8-bit shift register circuit 7b has a D3
Based on the clock pulse, the parallel data of 1 and the pulse of D27 are converted into parallel data of D31 (see D32 of FIG. 8) and output to the selector 8. The selector 8 controls the read control unit 4 by the control signal D3.
Upon receiving 5, the terminal is switched from 0 input data to 1 input data, and the pulse of D32 is output to the 2-bit flip-flop 9. Normally, the selector 8 outputs 0 input data (D34 pulse) to the 2-bit flip-flop 9. The 2-bit flip-flop 9 superimposes the data of the output of the 5-bit delay circuit 2 on the output data of the selector 8 based on the clock pulse, and outputs it.

[0019]

In the conventional highway data transfer control circuit, the header of the input serial data is read out and compared with the header from the outside.
If they match, the data stored in the ROM is read. Therefore, in order to transfer only the stored data and the input serial data, it is necessary to match the phases. Therefore, a delay of 7 bits occurs from the input to the output of the serial data until the transfer with the data in the memory is completed.

Therefore, according to the present invention, the data stored in the memory is sequentially read out before the matching detection between the header of the input highway data and the external header is detected. Rather than reading out the data frame sequentially, the data stored in the memory is sequentially read out to detect the header match in parallel. If they do not match, the data read from the memory is read. Discard.

Therefore, in order to transfer the data from the input to the output of the serial data, in order to match the phase of the header from the outside, a 5-bit delay is read out from the header first, and the match is detected. Instead, it is an object of the present invention to provide a highway data transfer control circuit capable of eliminating a 5-bit delay by reading serial data and performing processing in parallel with header matching detection.

[0022]

FIG. 1 shows an explanatory diagram of the principle of the present invention. The pulse data (PDATA) including the frame pulse, the header and the data is input, and when the desired header is detected, the data preset in the memory unit 4 and the data of the pulse data are selected by the selection unit 5. In the serial data transfer control circuit which transfers and outputs the data, the frame pulse is detected, and the data of the pulse data and the data set in the memory unit 4 are input to the selection unit 5 at the same timing. After the frame pulse is detected, the pre-reading unit 2 outputs a control pulse delayed by a predetermined bit, and the memory unit 4 outputs a read pulse for reading the data set in the memory unit 4 when the control pulse is input. The output of the pulse data is detected by detecting whether or not the header of the input pulse data is the desired header. Results The selected data read from the memory unit 4, if desired header, said desired the selection unit 5 a control signal for instructing to select the data of the pulse data without header
And a detection / readout control unit 3 for outputting to.

[0023]

In the present invention, the data is stored in the memory by reading the data from the memory after detecting whether the header is the desired one. At the same time, the detection of whether the header is the desired header is performed.

Before the detection of the desired header is completed, the read control unit sequentially reads the data stored in the memory by the frame pulse of the pre-reading unit. It can be processed in parallel with detection. Furthermore, when the data frame of the highway data is transferred to the data frame stored in the memory, it is possible to transfer the data without delaying the data necessary for matching the phases.

[0025]

2 is a block diagram of a serial data transfer control circuit according to an embodiment of the present invention.

The same objects as those in the configuration diagram of the conventional serial data transfer control circuit of FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted. Reference numeral 10 is a look-ahead pulse generator.

The correspondence between the pre-reading unit 2 of FIG. 1 and the pre-reading pulse generator 1 of FIG. 2 is shown.
1 corresponds to the header detection unit 3 and the read control unit 4 of FIG. 2, and the memory unit 4 of FIG. 1 corresponds to the ROM 5 of FIG. Selector 5
Corresponds to the P / S converter 7 and the selector 8 in FIG.

FIG. 3 shows a time chart of the serial data transfer control circuit of the present invention. FIG. 4 is a circuit diagram of the prefetch pulse generation unit 10 of the serial data transfer control circuit of the present invention. 10a is a 5-bit counter circuit, 10b is a decoder circuit, and 10c is
It is a T flip-flop circuit.

FIG. 5 is a circuit diagram of the header detecting section of the serial data transfer control circuit of the present invention. The same objects as those in the conventional header detecting section are designated by the same reference numerals.
The description is omitted. 3e is an AND circuit.

FIG. 6 is a circuit diagram of the read control unit 4 of the serial data transfer control circuit of the present invention, and FIG.
The same number is given to the same object as the circuit diagram of the read control unit 4 of the conventional serial data transfer control circuit of
The description is omitted. 4h is a JK flip-flop circuit.

The operation of the serial data transfer control circuit according to the embodiment of FIG. 2 will be described below with reference to FIGS. 3, 4, 5 and 6. The 2-bit flip-flop 1 of FIG. 2 is based on the cycle of the clock pulse (CLK).
The input frame data (FRMPI) and highway data (HWDTI) are each delayed by 1 bit (see D1 and D2 in FIG. 3), and the data D1 which is the frame data delayed by 1 bit is flip-flop 9 , High-way data (HWD) output to the prefetch pulse generation unit 10 and the header detection unit 3 and delayed by 1 bit.
The data D2 which is TI) is output to the selector 8 and the header detection unit 3.

The pre-read pulse generator 10 counts the frame pulse (see D1 in FIG. 3) from the 2-bit flip-flop 1 based on the clock pulse, and the ROM 5
18 after considering the processing time for reading the data from and converting the parallel data to serial data.
A bit-delayed pulse (D5 in FIG. 3) is created and output to the read control unit 4. The pulse of D5 in FIG. 3 is
Seen in units of continuous cycles, it comes two bits before the pulse D1 in FIG. The read control unit 4 receives the pulse (see D5 in FIG. 3) from the prefetch pulse generation unit 10 and receives R
ROM to read the data stored in OM5
Data is input to the ADDR terminal of No. 5 and the stored data is sequentially read when the pulse (see D9 in FIG. 3) to the XOER terminal changes from the H level to the L level, and the read data ( (See D14 in FIG. 3) P / S
The data is output to the 8-bit flip-flop 7a of the conversion unit 7.
Further, the read control unit 4 uses the 8-bit shift register 7
The pulse (D11 in FIG. 3) is output to b. The P / S conversion unit 7 reads the data read from the ROM 5 (D1 in FIG. 3).
4) is latched by the 8-bit flip-flop 7a based on the clock pulse (see D9 in FIG. 3), delayed by the 8-bit shift register 7b, and then the selector 8
Is output to the terminal 1. The header detection unit 3 uses the frame pulse of the 2-bit flip-flop 1 (see D1 in FIG. 3).
And the highway data header from the highway data (see D2 in FIG. 3) is extracted and compared with the header input from the outside on a bit-by-bit basis,
If they match, a matching pulse is output to the read control unit 4,
If they do not match, a mismatch pulse is output. When the read control unit 4 receives the coincidence pulse (see D3 in FIG. 3) from the header detection unit 3, the read control unit 4 outputs an H level pulse as a selection control signal for the selector 8 so that the terminal 1 of the selector 1 is selected. The data input to the terminal is output to the 2-bit flip-flop 9. Further, the header detection unit 3 is
The mismatch pulse (see D4 in FIG. 3) is output to the read control unit 4. When the read control unit 4 receives the mismatch pulse (see D4 in FIG. 3) from the header detection unit 3 and the H level pulse is input to the LD terminal of the 8-bit shift register 7b, the read data is converted from parallel data to serial data. To stop. The read control unit 4 receives the mismatch pulse (see D4 in FIG. 3) and sends the L level pulse as the selection control signal of the selector 8 to select the data input to the 0 terminal of the selector to select the 2-bit Output to the flip-flop 9. The 2-bit flop-flop 9 delays the frame pulse (see D1 in FIG. 3) and the data output from the selector 8 by 1 bit based on the clock pulse and outputs the delayed signal.

Next, as shown in the circuit diagram of the prefetch pulse generator of FIG. 4, the 5-bit counter circuit 10a receives the frame data (FRMPI) at the LD terminal and receives 5 bits based on the input of the clock pulse. Each of them is counted and output to the decoder circuit 10b. Decoder circuit 1
0b receives a count of 5 bits each, outputs a pulse to the T flip-flop circuit 10c at the time of counting the 17th bit, and delays by 1 bit in the T flip-flop circuit 10c (see D5 in FIG. 3). ), And output to the read control unit 4.

As shown in the circuit diagram of the header detector of FIG. 5, an external header is input to the comparator 3b, and the 4-bit shift register 3a converts the data D2 from serial data to parallel data based on clock pulses. do it,
Only the header of the data D2 is output to the comparator 3b.
The comparator 3b compares the header from the outside with the parallel header from the 4-bit shift register 3a bit by bit, and if all the bits match, the pulse is ANDed by the AND circuit 3
Output to one terminal of d and 3e.

The 4-bit shift register 3c delays the frame pulse D1 by 4 bits based on the clock pulse and outputs the delayed signal to the other terminals of the AND circuits 3d and 3e. When the output pulse of the comparator 3b and the output pulse of the 4-bit shift register 3c are input, the AND circuit 3d outputs a coincidence pulse to the read control unit 4 (see D3 in FIG. 3).
When the output pulse of the comparator 3b and the pulse obtained by inverting the output pulse of the 4-bit shift register 3c are input, the AND circuit 3e outputs a mismatch pulse to the read control unit 4 (see D4 in FIG. 3). Is output.

In the read control section of FIG. 6, the OR circuit 4i
Receives the non-matching pulse D4 of the header detection unit 3 and the output of the terminal F of the decoder circuit 4c, and if there is an output in either one, it is input to the JK flip-flop circuit 4a.
The NOR circuit 4j receives the output pulse (see D5 of FIG. 3) of the prefetch pulse generator 10 and the mismatch pulse D4 of the header detector 3 and outputs a pulse to the 4-bit counter circuit 4b when both pulses are not output. ..

The JK flip-flop circuit 4a outputs the output pulse D5 of the prefetch pulse generator 10 and the output pulse of the OR circuit 4i based on the clock pulse, and outputs the output pulse of the JK flip-flop circuit 4a (D6 of FIG. 3). Reference) to the 4-bit counter circuit 4b.

The 4-bit counter circuit 4b receives the output pulse D6 and the clock pulse (CLK), and outputs a 4-bit coded pulse (D7 in FIG. 3) indicating the count to the decoder 4c in parallel. The 4-bit counter circuit 4b outputs the output pulse of the NOR circuit 4j to the LD
When input to the terminal, a 4-bit initialization pulse (for example, "0000") is input from the grounded D terminal to the decoder 4c.
Is output to.

The 5-bit shift register circuit 4d receives the output pulse from the terminal F of the decoder circuit 4c, delays it by 5 bits based on the clock pulse, and outputs it to the JK flip-flop circuit 4h. The JK flip-flop circuit 4h outputs a pulse (see D17 in FIG. 3) as a control signal to the selector 8 based on the coincidence pulse D3 of the header detection unit 3 based on the clock pulse.

The decoder circuit 4c receives the frame pulse of the 4-bit counter circuit 4b (see D7 in FIG. 3),
The first and ninth pulses corresponding to the hexadecimal number of the frame are output to the OR circuit 4k, the third and B (10 in decimal number) pulses are output to the OR circuit 4l, and the seventh and F (10 The 16th pulse in the base number is output to the OR circuit 4m.

The OR circuit 4k receives the T flip-flop 4k when a pulse is input to one of the two inputs.
A pulse (see D8 in FIG. 3) is output to e. OR circuit 4
If a pulse is input to either one of the two inputs, l will be pulsed to the T flip-flop 4f (D1 in FIG. 3).
0 (see 0) is output. The OR circuit 4m outputs a pulse (see D12 in FIG. 3) to the 8-bit counter circuit 4g when a pulse is input to either one of both inputs.

The T flip-flop 4e is an OR circuit 4k.
Based on the clock pulse, the output pulse D8 of FIG. 3 is inverted at the trailing edge of the pulse (see D9 in FIG. 3)
Output to OM5. The T flip-flop circuit 4f outputs a pulse (see D11 in FIG. 3) obtained by inverting the input pulse D10 at the trailing edge of the pulse to the LD terminal of the 8-bit shift register 7b of the P / S conversion unit 7.

The 8-bit counter circuit 4g receives the pulse (D in FIG. 3) from the OR circuit 4m based on the clock pulse.
(See 12), 8 bits are counted, and the ADD of the ROM 5 is
A pulse (see D13 in FIG. 5) is output to the R terminal.

The ROM 5 shown in FIG. 2 has an input pulse D9.
And the stored data (D1 in FIG. 3).
4) is output to the P / S conversion unit 7. P / S converter 7
The 8-bit shift register circuit 7a of
4 and D9, the pulse of D14 is delayed for each bit based on the clock of the pulse of D9, and a pulse having a pulse width of 8 bits (see D15 in FIG. 3) is supplied to the 8-bit shift register circuit 7b. Output to.

The 8-bit shift register circuit 7b has a D1
Based on the clock pulse, the serial data of 5 and the pulse of D11 are converted from the parallel data of D15 into serial data (see D16 of FIG. 3) and output to the selector 8. The selector 8 receives the control signal of the read control unit 4 (see D17 in FIG. 3), selects the data of the 1 input terminal, and the data pulse D16 input to the 1 input terminal of the 2-bit flip-flop 9. Is output.

Normally, if the detection results of the header detection unit 3 do not match, an H level pulse is input from the read control unit 4 to the LD terminal of the 8-bit shift register 7b to convert parallel data to serial data. When stopped, the selector 8 outputs the data pulse D2 of the input terminal of 0, that is, the highway data D2 itself to the 2-bit flip-flop 9.

If the detection results of the header detection unit 3 match, an L level pulse is input to the LD terminal of the 8-bit shift register 7b to continue conversion from parallel data to serial data and 2 bits. The flip-flop 9 selects the highway data pulse D2 from the 2-bit flip-flop circuit 1 based on the clock pulse by the control signal pulse D17 of the read control unit 4 to select the selector 8
The input data D16 of the 1 input terminal is replaced and output.

[0048]

As described above, according to the present invention, when data is transposed, the data is delayed by 5 bits in order to adjust the timing of the data. , By reading the data in consideration of the reading time of the data from the memory and the time to convert the read data from parallel to serial, of the time used from the input to the output of the data The time required for data transfer can be considerably reduced, which contributes to speeding up of data processing.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a configuration of a serial data transfer control circuit showing an embodiment of the present invention.

FIG. 3 is a diagram showing a time chart of the serial data transfer control circuit of the present invention.

FIG. 4 is a circuit diagram showing a prefetch pulse generator of the serial data transfer control circuit of the present invention.

FIG. 5 is a circuit diagram showing a header detection unit of the serial data transfer control circuit of the present invention.

FIG. 6 is a circuit diagram showing a read control unit of the serial data transfer control circuit of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional serial data transfer control circuit.

FIG. 8 is a diagram showing a time chart of a conventional serial data transfer control circuit.

FIG. 9 is a circuit diagram showing a header detection unit of a conventional serial data transfer control circuit.

FIG. 10 is a circuit diagram showing a read control unit of a conventional serial data transfer control circuit.

[Explanation of symbols]

 1, 9, 2-bit flip-flop circuit 2, 5-bit delay circuit 3, header detection unit 4, read control unit 5, ROM 7, P / S conversion unit 8, selector

Claims (1)

[Claims] 1. When pulse data (PDATA) including a frame pulse, a header and data is input and a desired header is detected, the data previously set in the memory unit (4) and the pulse data In a serial data transfer control circuit for transferring and outputting the data in a selection unit (5), the frame pulse is detected, and the data of the pulse data and the data set in the memory unit (4) are described above. A pre-reading unit (2) that outputs a control pulse delayed by a predetermined bit after the frame pulse is detected so that the selection unit (5) inputs the same timing, and the memory unit (4) when the control pulse is input. A read pulse for reading the data set to is output to the memory unit (4), and the header of the input pulse data is forwarded. If it is the desired header as a result of the detection, the data read from the memory unit (4) is selected, and if it is not the desired header, the pulse data of the pulse data is detected. A serial data transfer control circuit, comprising: a detection / readout control section (3) for outputting a control signal for instructing to select data to the selection section (5).