JPH0581170A - Dma transfer device - Google Patents

Abstract

PURPOSE:To make it possible to make the loss of transfer time and the handling time of software development minimum by performing a DMA transfer providing an address counter every dimension of memory space. CONSTITUTION:When the number of picture elements in the horizontal direction memory space is 2N and the number of picture elements in the vertical direction is 2M (M=N+A), an address is shown by a N+M bit. When a horizontal direction address counter of N bit (H counter) 4 is counted to a termination address set by a DMA transfer termination detection circuit 9, a vertical direction address counter (V counter) of N+A bit 5 is counted by a H direction DMA transfer termination detection circuit 8. Thus, the DMA transfer is proceeded and the DMA transfer termination detection circuit 9 detects the DMA transfer termination by the count value of a V counter 5 and the output of a H direction DMA transfer termination detection circuit 8. Thus, only by setting of a transfer start address of the left up of picture data and a transfer termination address of the right down of picture data, the DMA transfer can be performed for the picture data within a window shown by the diagonal at one time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transfer between an input device and a memory, and more particularly to a central processing unit (hereinafter referred to as C
The present invention relates to a direct memory access (hereinafter abbreviated as DMA) transfer that directly transfers data without intervention of PU.

[0002]

2. Description of the Related Art Generally, in an image processing device or the like, the amount of image data to be processed is so large that data is directly transferred between an input / output device and a main memory without CPU intervention. DMA transfer is used.

In this DMA transfer, a DMA transfer device is used, and during the data transfer, this DMA transfer device manages the bus and controls the transfer. The CPU sends a control signal to the DMA transfer device as needed for the DMA transfer, and the DMA transfer device receives the control signal, activates the input device and occupies the memory, starts the data transfer, and ends the transfer. Then, the monopolization of the memory is released. That is, since the data is transferred after the memory access from the CPU is prohibited, a large amount of data as described above can be processed at high speed. The DMA transfer performed by the conventional DMA transfer device will be described below with reference to FIG.

As shown in FIG. 1, a conventional DMA transfer device includes a microcomputer 40 including a CPU (hereinafter abbreviated as a microcomputer), a memory 41, and a timing control circuit 4.
2, address counter 43, bus controller 44, D
It is composed of an MA transfer end detection circuit 45. The microcomputer 40 includes a CPU and controls the entire operation. The memory 41 stores data to be transferred to and from the external bus 47. The timing control circuit 42 is
The timing of data exchange between the memory 41 and the external bus 47 is controlled.

The address counter 43 increments or decrements the address of the data to be transferred on the memory 41 set by the microcomputer 40 in response to the signal from the timing control circuit 42.

The bus controller 44 switches the memory data bus to the microcomputer 40 side or the external bus side and the memory address bus to the microcomputer side or the address counter 43 side according to the signal from the timing control circuit 42. The DMA transfer end detection circuit 4
5 detects that data has been transferred up to the value set by the microcomputer 40.

With the DMA transfer device having such a configuration,
When performing the DMA transfer, first, the microcomputer 40 executes the DMA
The address to start the transfer is set to D in the address counter 43.
An address for ending the MA transfer is set in the DMA transfer end detection circuit 45, respectively. Then, after setting the transmission or reception mode in the timing control circuit 42, the DMA
Start the transfer.

When the transmission / reception mode is set, the timing control circuit 42 starts exchanging data with the external bus. Then, the address counter 43 updates the address each time data is transmitted / received and indicates the address of the next data.

Then, the DMA transfer end detection circuit 45 refers to the value of the address counter 43, compares whether or not the data has been transferred up to the count value set by the microcomputer 40, and when the data is transferred up to the set value, The timing control circuit 42 is stopped and the microcomputer 40 is notified of the end of the DMA transfer. Conventionally, DMA transfer has been realized by the above method. Next, FIG. 5 shows the conventional DMA described above.
3 shows a memory space in which image data is stored when performing DMA transfer by the transfer device.

As shown in the figure, in the present embodiment, the memory space in which the image data is placed has horizontal A pixels and vertical N pixels, and is a continuous memory space from the upper left pixel to the lower right pixel. Is becoming When transferring image data to an external device or memory, in order to transfer the entire screen, the data is all continuous, so the upper left pixel data address is used as the transfer start address and the end address is used as the end address. Just set the address of the lower right pixel,
Data can be transferred.

[0011]

However, only a small part of the image is required as normal data, and when a part of the image is transferred as a window 500 as shown in FIG. Each of them is located in a discontinuous memory space, and the above method cannot transfer data at one time. Therefore, DMA transfer must be performed for each line. That is, the window 500
The address of the image data at the left end and the address at the right end of the line are set, and then the left end and the right address of the next line are set. In this way, the image data in the window is set and transferred line by line. Therefore, in this way, DMA is performed line by line.
If the transfer is set, there is a drawback that the transfer time is delayed. Furthermore, it becomes annoying when developing software.

The present invention has been made in view of such a problem, and an object thereof is to provide a DMA transfer device for minimizing the loss of DMA transfer time and the effort of software development. To do.

[0013]

To achieve the above object, in the DMA transfer apparatus of the present invention, at least (M-1) of a plurality (M) -dimensional memory space in which image data is placed.
In an image processing apparatus in which the size of each dimension is represented by the number of pixels of a power of 2, DMA transfer is performed by providing a counter for each dimension as a DMA address counter.

[0014]

That is, the operation of the present invention is such that the number of pixels in the horizontal direction of the two-dimensional memory space in which image data is placed is 2 ^{N, for example.} And the number of pixels in the vertical direction is 2 ^M By setting (M = N + A), the address is indicated by N + M bits, the lower N bits of the address are the portion indicating the horizontal position, and the other upper lower M bits are indicating the vertical position.

Therefore, even for image data in a window placed in a discontinuous memory space, a counter provided for each dimension simply sets a start address and an end address of DMA transfer, and the diagonally crosses the address. The image data in the window shown can be DMA-transferred at one time.

[0016]

1 is a diagram showing the configuration of an embodiment of a DMA transfer apparatus of the present invention.

The DMA transfer device of this embodiment is a microcomputer 1 including a CPU (hereinafter abbreviated as a microcomputer).
And a memory 2, a timing control circuit 3, an N-bit lateral address counter 4 (hereinafter, H counter), and N + A
Bit vertical address counter 5 (hereinafter, V counter), N bit latch 6, bus controller 7, H direction DMA transfer end detection circuit 8, DMA transfer end detection circuit 9
It is composed by. The microcomputer 1 includes a CPU and is responsible for overall control. The memory 2 stores data to be transferred to and from the external bus, and has an address space as shown in FIG.

That is, in this embodiment, image data is stored
The number of horizontal pixels in the two-dimensional memory space^N And vertical
Number of pixels in the direction is 2^M (M = N + A) and enter the address
The lower N bits are indicated by N + M bits of the sum of
The other upper M bits are set vertically to indicate the horizontal position.
It indicates the position of the direction.

For example, the address at position 21 in the figure is "2 ^{N + A-2} " indicating the vertical position. ", And" 2 "indicating the horizontal position
^N The sum of "-1" and "2 ^{N + A-1"} -1 ". The timing control circuit 3 controls the timing of data exchange between the memory 2 and the external bus 10.

The N-bit H counter 4 increments or decrements the address of the transfer data on the memory 2 set by the microcomputer 1 in response to a signal from the timing control circuit 3.

The bus controller 7 switches the memory data bus to the microcomputer 1 side or the external bus side and the memory address bus to the microcomputer side or the address counter side in response to the signal from the timing control circuit 3.

The H-direction DMA transfer end detection circuit 8 is
When the H counter 4 counts up to the address set by the microcomputer 1, the count start data is loaded again and the V counter is incremented or decremented. The DMA transfer end detection circuit 9 detects the end of the DMA transfer from the count value of the V counter 5 and the output of the H direction transfer end detection circuit 8.

With the DMA transfer device having such a configuration, D
When performing the MA transfer, the microcomputer 1 first sets the start address for starting the DMA transfer to each address counter by D
The end address for ending the MA transfer is set in the DMA transfer end detection circuit 9, respectively. After the above setting, the transmission / reception mode is set in the timing control circuit 3, and the DM
A Transfer is started.

When the DMA transfer is started, the timing control circuit 3 controls the timing of data exchange between the memory 2 and the external bus 10. Under the control of the timing control circuit 3, the bus controller 7 switches the memory data bus to the microcomputer side or the external bus side,
Alternatively, switch the memory address bus to the microcomputer side or address counter side.

When the image data to be DMA-transferred is two-dimensional, the address counters are N-bit H counter 4 and N-bit.
Two + A bit V counters 5 are provided,
The H counter 4 increments or decrements the address of the transfer data on the memory 2 previously set by the microcomputer 1 in response to the signal from the timing control circuit 3.

When the H counter 4 counts up to the end address previously set in the DMA transfer end detection circuit 9 by the microcomputer 1, the H direction DMA transfer end detection circuit 8 again outputs the data of the count start address. It is loaded, and the V counter 5 is incremented or decremented.

Thus, the DMA transfer is advanced, and when the DMA transfer end detection circuit 9 detects the end of the DMA transfer from the count value of the V counter 5 and the output of the H direction transfer end detection circuit 8, the timing control circuit 3 is stopped and the DMA transfer is completed. Notify the microcomputer 1 of the end of the DMA transfer by the end detection signal,
The DMA transfer ends.

Therefore, according to this embodiment, for example, a part of the image data is displayed as a window 20 as shown in FIG.
Even in the case of MA transfer, it is only necessary to specify the upper left transfer start address and the lower right transfer end address of the image data shown in the window 20 without transferring the image data line by line as in the conventional case. , The data in the window indicated by the diagonal can be transferred at one time. The detailed configuration of the DMA transfer device according to the embodiment of the present invention will be described below with reference to FIG.

In this embodiment, 2 ¹¹ = 2048 (11 bits) pixels in the horizontal direction (hereinafter, H direction) and the vertical direction (hereinafter, V
The direction is 2 ¹⁰ = 1024 (10 bits) pixels, and the data of one pixel is B / W data of 8 bits.

The DMA transfer apparatus according to this embodiment includes an 11-bit latch 31, an 11-bit counter 32, an 11-bit latch 33, an 11-bit comparator 34, a 10-bit counter 35, a 10-bit latch 36, a 10-bit comparator 37, a load pulse. Generation circuit 38, negative O
It is composed of an R circuit 39.

With the DMA transfer device having such a configuration, D
When performing the MA transfer, the microcomputer 1 first outputs the DMA start address via the data bus, and then outputs the start address set signal (hereinafter, S signal). This signal is
It can be easily created by ANDing the output of the address decoder and the read signal of the microcomputer 1. The S signal causes the DMA start address in the H direction to be latched in the 11-bit latch 31, and
The start address in the V direction is loaded into the 10-bit counter 35.

Next, the microcomputer 1 outputs the DMA end address to the data bus and outputs an end address set signal (hereinafter referred to as E signal).
The MA end address is latched by the 11-bit latch 33, and the end address in the V direction is the 10-bit latch 3.
Latched to 6.

When the timing control circuit 3 is enabled, the timing control circuit 3 receives DM from the external bus.
ACK signal (active lo
w) is output, and the output of data from the memory 2 is started.
Then, after outputting the data, the ACK signal is raised to wait for the next DMA request signal. At this time, the 11-bit counter 3 is caused by the rise of the ACK signal during the DMA transfer.
2 counts. Then, the 11-bit latch 3
1 loads the start address into the 11-bit counter 32 by the pulse of the load pulse generating circuit 38 described later.

By repeating this, the 11-bit comparator 34 compares the output of the 11-bit counter 32 with the output of the 11-bit latch 33, and when they are equal, outputs the = H signal (active low) to the load pulse generating circuit 38, At the next rise of the ACK signal, the 10-bit counter 35 performs a counting operation, the load pulse generation circuit 38 outputs a load pulse to the 11-bit counter 32 via the negative OR circuit 39, and the H-direction start address is loaded again. Let

By repeating the above operation, the value of the 10-bit counter 35 and the value of the 10-bit latch 36 become equal.
Thereafter, when the value of the 11-bit counter 32 becomes equal to the value of the 11-bit latch 33, the ACK signal rises, that is, when the final data to be DMA-transferred is transferred, the 10-bit counter 35 is counted. The count value is different from the value of the 10-bit latch 36. At this time, a DMA end signal (= V signal) rises from the 10-bit comparator 37 and interrupts the microcomputer 1 to end the DMA transfer. In the above description, the case of transmitting data has been described, but the case of receiving data can be performed by the same process.

As described above, according to this embodiment,
With a DMA transfer device with a very simple circuit configuration, even if part of image data is not transferred line by line as in the conventional case,
The data can be transferred at an extremely high speed because the DMA transfer can be performed depending on the degree setting. Furthermore, since the setting of DMA transfer can be easily done, the software can be developed very easily. Although one embodiment of the present invention has been described above, the present invention is not limited to this, and it goes without saying that other changes and modifications can be made.

For example, not only two-dimensional image data, but also for transfer of three-dimensional or more data including, for example, the Z axis, the time axis, etc. in addition to the X and Y axes, an address counter in that direction is added. By doing so, it is possible to easily deal with this, and the effect of increasing the transfer speed and the ease of setting is further enhanced.

[0038]

As described above in detail, according to the present invention, even if a part of the image data is not transferred line by line.
Since the DMA transfer can be performed by setting the degree, it is possible to provide a DMA transfer device that can minimize the loss of the DMA transfer time and the labor of software development.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a DMA transfer device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a memory space of a DMA transfer device according to an embodiment.

FIG. 3 is a diagram showing a detailed circuit configuration of a DMA transfer device of the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional DMA transfer device.

FIG. 5 is a diagram showing a memory space in which image data is stored in a conventional DMA transfer device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Microcomputer, 2 ... Memory, 3 ... Timing control circuit, 4 ... H counter, 5 ... V counter, 6 ... Latch, 7 ... Bus controller, 8 ... H direction DMA transfer completion detection circuit, 9 ... DMA detection completion circuit 10 ... External bus, 11 ... Microcomputer address data bus, 12 ... DMA
Address bus, 13 ... DMA address bus, 14 ... Memory address data bus.

Claims (1)

[Claims] 1. A DMA address in an image processing device, wherein the size of at least (M-1) dimensions of a plurality of (M) -dimensional memory spaces in which image data is placed is represented by a power of 2 pixels. A DMA provided by providing a counter for each of the above dimensions as a counter to perform DMA transfer
Transfer device.