JPH0580830B2 - - Google Patents
Info
- Publication number
- JPH0580830B2 JPH0580830B2 JP59035908A JP3590884A JPH0580830B2 JP H0580830 B2 JPH0580830 B2 JP H0580830B2 JP 59035908 A JP59035908 A JP 59035908A JP 3590884 A JP3590884 A JP 3590884A JP H0580830 B2 JPH0580830 B2 JP H0580830B2
- Authority
- JP
- Japan
- Prior art keywords
- cell
- layer
- bit line
- semiconductor memory
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 7
- 238000006073 displacement reaction Methods 0.000 claims 1
- 238000000926 separation method Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 4
- 238000001514 detection method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/10—SRAM devices comprising bipolar components
Description
【発明の詳細な説明】 発明の技術分野 本発明は半導体記憶装置に関する。[Detailed description of the invention] Technical field of invention The present invention relates to a semiconductor memory device.
従来技術と問題点
一般に、半導体記憶装置は、第１図に示すよう
に左側の第１セル１と右側の第２セル２との２つ
のセルから成り、それぞれがビツト線bl，brまた
は共通にワード線ｗ、ホールド線ｈに接続されて
いる。この場合、第２図から明らかなように２つ
のセルはフリツプフロツプ回路を構成し、検出及
び保持用のトランジスタQ1，Q3と同様のトラン
ジスタQ2，Q4のベースＢとコレクタＣが交叉し
て接続せざるを得ないため、実際には第３図のよ
うに第１セル１と第２セル２を変位させている。
これにより、ベース端子Ｂとコレクタ端子Ｃが対
向するので（第３図）、配線がし易くなつている。
そしてその構造は第３図の従来装置で説明すれ
ば、変位して配置された第１セル１と第２セル２
は互いに絶縁するため、共通の素子分離帯１０、
個別の素子分離帯１１，１２、及び２１，２２，
２３により包囲されている。このような構造の装
置に対し、ワード線ｗ、ホールド線ｈ、ビツト線
bl.brが一点鎖線で示すように配置されている。Prior Art and Problems In general, a semiconductor memory device consists of two cells, a first cell 1 on the left side and a second cell 2 on the right side, as shown in FIG. It is connected to a word line w and a hold line h. In this case, as is clear from FIG. 2, the two cells constitute a flip-flop circuit, and the bases B and collectors C of transistors Q 2 and Q 4 , which are similar to transistors Q 1 and Q 3 for detection and holding, intersect. Therefore, the first cell 1 and the second cell 2 are actually displaced as shown in FIG.
As a result, the base terminal B and the collector terminal C face each other (FIG. 3), making wiring easier.
If the structure is explained using the conventional device shown in FIG. 3, the first cell 1 and the second cell 2 are displaced and arranged.
are insulated from each other, a common element isolation band 10,
individual element isolation bands 11, 12, and 21, 22,
It is surrounded by 23. For a device with such a structure, word line w, hold line h, bit line
bl.br is arranged as shown by the dashed line.
しかし、従来装置に分離帯の幅を自由に変える
ことができない、いわば幅の自由度が少ない素子
分離技術を用いた場合、ビツト線bl，brを配置す
るために斜線で示す（第３図）不必要な領域が形
成され、浮遊容量の一種たるバルク容量が形成さ
れる。即ち、第４図に示すように、斜線領域の直
下は、ｎ層１５と埋め込みバルク層１６と基板Ｐ
層１７で形成され、金属製のビツト線brとその下
方の層間で破線で示す静電容量C1が現れる。 However, when a conventional device uses element isolation technology in which the width of the separation band cannot be freely changed, so to speak, there is little freedom in width, the bit lines bl and br are shown with diagonal lines to arrange them (Figure 3). An unnecessary area is formed, and a bulk capacitance, which is a type of stray capacitance, is formed. That is, as shown in FIG. 4, immediately below the shaded area are the n-layer 15, the buried bulk layer 16, and the substrate P.
A capacitance C 1 shown by a broken line appears between the metal bit line br formed by the layer 17 and the layer below it.
従つてこの容量の存在により、従来技術では読
み出しの高速化が妨げられるという問題点があつ
た。 Therefore, due to the existence of this capacitance, there was a problem in the conventional technology that speeding up the readout was hindered.
発明の目的
本発明の目的は、幅の自由度が少ない素子分離
技術を用いた半導体記憶装置において、セル動作
において不必要な領域の分離帯を二重に形成する
ことによりActive領域から切り離し、浮遊容量
を減少させてデータの読出し書き込みの高速化を
図ることにある。Purpose of the Invention An object of the present invention is to form a double separation band in an area unnecessary for cell operation in a semiconductor memory device using element isolation technology with a small degree of freedom in width, thereby separating the area from the active area and making it floating. The purpose is to reduce the capacity and increase the speed of reading and writing data.
発明の構成
本発明によれば、第１セルと第２セルが互いに
変位して連続的に配列され、両セルの素子分離帯
の幅が固定されている半導体記憶装置において、
それぞれの隣り合う第１セル間及び第２セル間が
二重の分離帯で形成されていることを特徴とする
半導体記憶装置が提供される。Structure of the Invention According to the present invention, in a semiconductor memory device in which a first cell and a second cell are continuously arranged while being displaced from each other, and the width of the element isolation band of both cells is fixed,
There is provided a semiconductor memory device characterized in that double separation bands are formed between adjacent first cells and between adjacent second cells.
発明の実施例
以下、本発明を実施例により添付図面を参照し
て説明する。Embodiments of the Invention The present invention will now be described by way of embodiments with reference to the accompanying drawings.
第５図と第６図は、それぞれ本発明に係る半導
体記憶装置の平面図と第１セル１の縦断面図であ
る。 5 and 6 are a plan view of a semiconductor memory device according to the present invention and a longitudinal cross-sectional view of the first cell 1, respectively.
第１セル１と第２セル２はそれぞれ第５図に示
すように矩形状をしており、互いに変位して配置
されている。ワード線ｗが各セルの負荷トランジ
スタQ5，Q6（第２図）の端子Ｗに、またホールド
線ｈが保持トランジスタQ3，Q4（第２図）の端子
EHに、それぞれ接続されている（第５図）。ま
た検出トランジスタQ1，Q2（第２図）のベース端
子Ｂとコレクタ端子Ｃどうしが対向して接続して
いる（第５図）。 The first cell 1 and the second cell 2 each have a rectangular shape as shown in FIG. 5, and are arranged so as to be displaced from each other. The word line w is connected to the terminals W of the load transistors Q 5 and Q 6 (Fig. 2) of each cell, and the hold line h is connected to the terminals of the holding transistors Q 3 and Q 4 (Fig. 2).
Each is connected to EH (Figure 5). Furthermore, the base terminals B and collector terminals C of the detection transistors Q 1 and Q 2 (FIG. 2) are connected to face each other (FIG. 5).
各セル１，２は分離帯１１，１２，１３，１０
及び２１，２２，２３，１０により絶縁されてい
る。セル１の端子ESにはビツト線blが、セル２
の端子ESにはビツト線brが、それぞれ接続され、
第１セル１のビツト線bl，が配置されている隣り
合う第２セル２間の領域はビツト線blの両側が２
つの分離帯２２と２２′により二重に形成されて
いる。 Each cell 1, 2 has separation strips 11, 12, 13, 10
and 21, 22, 23, and 10. The bit line bl is connected to terminal ES of cell 1, and the bit line bl is connected to terminal ES of cell 1.
The bit wire br is connected to the terminal ES of
In the area between the adjacent second cells 2 where the bit line bl of the first cell 1 is arranged, both sides of the bit line bl are 2
It is formed double by two separation bands 22 and 22'.
第２セル２のビツト線brに関しても、同様に隣
り合う第１セル１間のビツト線brの配置領域が分
離帯１１，１１′により二重に形成されセル領域
より分離されている。 Regarding the bit line br of the second cell 2, similarly, the arrangement area of the bit line br between adjacent first cells 1 is formed in double form by separation bands 11 and 11', and is separated from the cell area.
装置の内部を、第１セル１を例に説明すれば第
６図から明らかなように、Ｐ層１４、Ｎ層１８ｎ
形エピキシヤル層１５及び基板のＰ層１７より成
る。 If the inside of the device is explained using the first cell 1 as an example, as is clear from FIG. 6, the P layer 14, the N layer 18n
It consists of an epitaxial layer 15 and a P layer 17 of the substrate.
端子Ｗ，ＢはＰ層１４に、端子ES，EH及びＣ
はＮ層１８，１５にそれぞれ接続されている。ま
たビツト線brは第６図から見て後に配置した第２
セル２の端子ESに接続している。第６図の断面
図に示す端子Ｗの左側は分離帯１２だけで絶縁さ
れているが、端子Ｃの右方でビツト線brの両側は
２つの分離帯１１′と１１によつて二重に絶縁さ
れている。 Terminals W and B are connected to the P layer 14, and terminals ES, EH and C are connected to the P layer 14.
are connected to the N layers 18 and 15, respectively. Also, the bit line br is the second bit line placed later as seen in Fig.
Connected to terminal ES of cell 2. The left side of the terminal W shown in the cross-sectional view of FIG. Insulated.
このように分離帯を二重に形成したことによ
り、ビツト線br，blの直下の層が他層から切り離
されて、等価的には第６図に示すようにコンデン
サC1とC2が直列接続された状態となり、従来よ
りも浮遊容量が減少する。 By forming a double separation band in this way, the layer immediately below the bit lines br and bl is separated from other layers, and equivalently, capacitors C 1 and C 2 are connected in series as shown in Figure 6. This results in a connected state, and stray capacitance is reduced compared to before.
なお本実施例では、ビツト線blは基板表面上の
第１層目の配線により形成され、ワード線ｗ及び
ホールド線ｈはその上の第２層目の配線により形
成されている。 In this embodiment, the bit line bl is formed by the first layer of wiring on the substrate surface, and the word line w and the hold line h are formed by the second layer of wiring above it.
発明の効果
上記の通り、本発明によればビツト線直下の両
側を２つの分離帯により二重に絶縁したので、浮
遊容量が減少してデータの読出速度が向上する。Effects of the Invention As described above, according to the present invention, since both sides immediately below the bit line are doubly insulated by two separation bands, stray capacitance is reduced and data read speed is improved.
第１図と第２図は、半導体記憶装置の一般的な
回路図、第３図は従来装置の平面図、第４図は第
３図の部分断面図、第５図は本発明装置の平面
図、第６図は第５図の断面図である。
１……第１セル、２……第２セル、１０，１
１，１１′，１２，１３……分離帯、１４……Ｐ
層、１５……Ｎ層、１６……埋込バルク層、１７
……Ｐ形基板、２１，２２，２２′，２３……分
離帯。
1 and 2 are general circuit diagrams of a semiconductor memory device, FIG. 3 is a plan view of a conventional device, FIG. 4 is a partial sectional view of FIG. 3, and FIG. 5 is a plan view of a device of the present invention. 6 is a sectional view of FIG. 5. 1...First cell, 2...Second cell, 10,1
1, 11', 12, 13...separation strip, 14...P
Layer, 15... N layer, 16... Buried bulk layer, 17
...P-type substrate, 21, 22, 22', 23... Separation band.
Claims (1)
に配列され、両セルの素子分離帯の幅が固定され
ている半導体記憶装置において、 それぞれの隣り合う第１セル間及び第２セル間
が二重の分離帯で形成されていることを特徴とす
る半導体記憶装置。[Scope of Claims] 1. In a semiconductor memory device in which a first cell and a second cell are continuously arranged with displacement from each other, and the width of the element isolation band of both cells is fixed, each adjacent first cell A semiconductor memory device characterized in that a double isolation band is formed between the first cell and the second cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59035908A JPS60182160A (en) | 1984-02-29 | 1984-02-29 | Semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59035908A JPS60182160A (en) | 1984-02-29 | 1984-02-29 | Semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60182160A JPS60182160A (en) | 1985-09-17 |
| JPH0580830B2 true JPH0580830B2 (en) | 1993-11-10 |
Family
ID=12455125
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59035908A Granted JPS60182160A (en) | 1984-02-29 | 1984-02-29 | Semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60182160A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5825260A (en) * | 1981-08-08 | 1983-02-15 | Fujitsu Ltd | Junction short-circuit type programmable read only memory |
-
1984
- 1984-02-29 JP JP59035908A patent/JPS60182160A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5825260A (en) * | 1981-08-08 | 1983-02-15 | Fujitsu Ltd | Junction short-circuit type programmable read only memory |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60182160A (en) | 1985-09-17 |
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