JPS60182160A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To accelerate the data reading speed by reducing floating capacity by a method wherein both sides directly below lines are doubly insulated by two groups of separating bands. CONSTITUTION:Two cells are insulated by two groups of separating bands of 11, 12, 13, 10 and 21, 22, 23, 10. In the region between adjoining cells 2, both sides of bit line bl are formed into two parts by two separating bands 22 and 22'. Likewise the region wherein another bit line (br) between adjoining cells 1 are separated by two separating bands 11, 11'. Through these procedures, the floating capacity may be reduced less than conventional one since the layer directly below the bit lines (br), (bl) are separated from other layers by the separating bands doubly formed to make a capacity equivalently connected in series.

Description

[Detailed description of the invention] Technical field of invention The present invention relates to a semiconductor memory device.

Prior Art and Problems In general, a semiconductor memory device consists of two cells, a first cell 1 on the left and a second cell 2 on the right, as shown in FIG. It is connected to the word line W and the hold line. In this case, as is clear from FIG. 2, the two cells constitute a flip-flop circuit, and the transistors QIQ3 and Pace B and collector C of the transistors Qx and Q4, which are similar to the detection and holding transistor QIQ3, must be crossed and connected. Therefore, the first cell 1 and the second cell 2 are actually displaced as shown in FIG.

As a result, the pace terminal B and the collector terminal C face each other (FIG. 3), making wiring easier.

The structure will be explained using the conventional device shown in FIG. 3. In order to insulate the first cell 1 and the second cell 2, which are displaced from each other, from each other, a common element isolation band 10. Individual element isolation band 11
．． 12. and 21, 22, and 23.

For a device with such a structure, word line W, hole tJ
Ihs bit line bl.

br are arranged as shown by the dashed line.

However, when a conventional device uses an element isolation technology in which the width of the separation band cannot be freely changed, so to speak, the degree of freedom in the width is small, the bit lines blzbr are arranged using diagonal lines (shown with diagonal lines). Figure) Unnecessary areas are formed, and bulk capacitance, which is a type of stray capacitance, is formed. That is, as shown in FIG. 4, the area immediately below the hatched area is formed by the n-layer 15, the buried bulk layer 16, and the second substrate layer 17, and the electrostatic charge shown by the broken line is generated between the metal bit line br and the layer below it. A capacitance C1 appears.

Therefore, due to the existence of this capacitance, the conventional device frequently has the problem that speeding up of reading is hindered.

OBJECTS OF THE INVENTION It is an object of the present invention to improve Act, I, and I by forming double isolation bands in areas unnecessary for cell operation in a semiconductor memory device using element isolation technology with less freedom in width.
The purpose is to separate the memory area from the ve area, reduce stray capacitance, and speed up data reading and writing.

According to the present invention, in a semiconductor memory device in which a first cell and a second cell are continuously arranged while being displaced from each other, and the width of the element branch band of both cells is fixed, A semiconductor memory device is provided, characterized in that double separation bands are formed between first cells and between second cells.

Embodiments of the Invention The present invention will now be explained by way of embodiments with reference to the accompanying drawings.

5 and 6 are a plan view of a semiconductor memory device according to the present invention and a longitudinal cross-sectional view of the first cell 1, respectively.

The first cell 1 and the second cell 2 each have a rectangular shape as shown in FIG. 5, and are arranged so as to be displaced from each other. The word line W is connected to the terminal W of the load transistor Qs, Qs (FIG. 2) of each cell, and the hold line is connected to the terminal EH of the holding transistor Q3, Q4 (FIG. 2), respectively. figure).

Furthermore, the pace terminals B and collector terminals C of the detection transistors Ql and Qt (FIG. 2) are connected to face each other (FIG. 5).

Each cell 1.2 has separation strips 11.12, 13.10 and 21
, 22.23.10. The terminal ESK of cell 1 is connected to the bit line b], and the terminal KS of cell 2 is connected to the bit line br. The area is formed by two separation bands 22 and 22' on both sides of the bit line bl.

Regarding the bit line br of the second cell 2, similarly, the arrangement area of the bit line br between the adjacent first cells 1 is in the separation band 11.
, 11' are formed in double form and separated from the cell region.

If the inside of the device is explained using the 9th cell 1 as an example, as is clear from FIG. 6, it consists of two layers 14, an N layer 18, an n-type epitaxial layer 15, and two layers 17 of the substrate.

Terminals W and B are connected to layer 2 14, and terminals ES, EH and C are connected to layer 8 18.15, respectively. The hit line br is connected to the terminal ES of the second cell 2 placed later as viewed in FIG. The left side of the terminal W shown in the cross-sectional view of FIG. 6 is insulated only by the separation strip 12, but on the right side of the terminal C, both sides of the bit line br are doubly insulated by two separation strips 11' and 11. ing.

By forming the separation zone with double pressure in this way, the layer immediately below the bit lines br and bl is separated from the other layers,
Isometrically, when the capacitors C1 and C2 are connected in series as shown in FIG. 6, the stray capacitance is reduced compared to the conventional case.

In this embodiment, the bit line bl is formed in the first layer of wiring on the substrate surface, and the word line W and the hold line are formed in the second layer of wiring above it. .

Effects of the Invention As described above, according to the present invention, since both sides immediately below the bit line are heavily insulated by two separation bands, stray capacitance is reduced and data reading speed is improved.

[Brief Description of the Drawings] Figures 1 and 2 are general circuit diagrams of semiconductor memory devices;
3 is a plan view of the conventional device, FIG. 4 is a partial sectional view of FIG. 3, FIG. 5 is a plan view of the device of the present invention, and FIG. 6 is a sectional view of FIG. 5. 1...First cell, 2...Second cell, 10.11°1
1', 12.13... Separation zone, 14... P layer, 15
... N layer, 16... Buried bulk layer, 17... P type substrate, 21.22, 2□21. -23... Separation zone.

Claims (1)

[Scope of Claims] In a semiconductor memory device in which a first cell and a second cell are continuously arranged while being displaced from each other, and the width of the element isolation band of both cells is fixed, each adjacent first cell A semiconductor memory device characterized in that a double isolation band is formed between the first cell and the second cell.