JPS61140170A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To contrive to increase the integration and capacitance by integrating memory cells made of the MOSFET with source and drain regions formed in the longitudinal direction by utilizing the side wall of projections formed in periodical strips form, and of the MOS capacitor formed in stack on this source region. CONSTITUTION:The titled device uses a wafer with an N<+> layer 12 serving as the drain region of the MOSFET formed on a P-type Si substrate 11 in common to all memory cells, and with a P<-> type layer 13 formed thereon by epitaxial growth. A plurality of stripe projections are formed by digging grooves deep enough to reach the N<+> type layer 12, and a gate electrode 15 is continuous ly formed on the side wall of each projection via gate insulation film 14 and each forms other word lines. The projection top is discretely provided with arrangements of N<+> type layers 16 serving as the source region of the MOSFET independent in every memory cell, along both sides. This N<+> type layer 16 is the first electrode of the MOS capacitor, and the second electrode 19 of the capacitor is formed thereon via capacitor insulation film 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides - (7) MOSFETs, ! Knee pieces (7) M
The present invention relates to a semiconductor memory device in which a memory cell is configured using an OS capacitor.

[Technical background of the invention and its problems] Semiconductor memory devices are becoming more highly integrated and larger in capacity. In particular, a MOS dynamic RA in which a memory cell is configured by - MOSFETs and one MOS capacitor.
M has the most advanced integration due to its memory cell format, and a 256-bit version has already been put into practical use, and a 1M-bit version is currently available at the research stage.

FIG. 7 is a cross section of a conventional memory cell. 31 is p-type 81 substrate, 32.33 is n"/-s, drain, 34
．． 35 is a gate electrode and a capacitor electrode formed of a polycrystalline silicon film, and 36 is an Al1 line (bit line). There are several problems in increasing the integration and capacity of such MOS dynamic RAMs in the future. For example, in the above cell, MOSFET, M
Since the memory cell has contact with the OS capacitor and the bit line, it is difficult to reduce the memory cell size and high integration is not possible. Furthermore, as the capacitor area becomes smaller due to cell size reduction, soft errors due to alpha rays become more likely to occur. That is, U included in the packaging material.

α particles emitted from radioactive elements such as Th generate electron-hole pairs in the substrate, of which electrons reach nodes of memory cells and destroy stored information.

On the other hand, electrons that reach the bit line change its potential, causing malfunction. Such soft errors have already become a serious problem at the 1M bit level.

[Object of the Invention] An object of the present invention is to provide a semiconductor memory device that achieves high integration and large capacity without impairing reliability.

[Summary of the invention]

A semiconductor memory device according to the present invention is a MOSFET in which a source region and a drain region are vertically formed using side walls of convex portions formed in a periodic stripe shape on a semiconductor substrate.
In order to integrate a memory cell consisting of an ET and a MOS capacitor formed over the source region of this MOSFET, and to separate the source region formed for each memory cell on the upper surface of the convex portion, A feature is that a high impurity concentration layer to which a fixed potential is applied is provided on the upper surface of the convex portion.

〔Effect of the invention〕

According to the present invention, the structure is such that a MOS capacitor is stacked on a MOSFET, and the conventional MOS dynamic RA
Compared to M, it is possible to achieve significantly higher integration and larger capacity. Further, the source regions formed independently for each memory cell on the upper surface of the convex portion are separated by a high impurity concentration layer, and by applying a fixed potential to this high impurity concentration layer, a highly reliable dRAM can be obtained. In particular, when the drain region of the MOSFET is formed by a high impurity concentration layer provided on the entire surface of the substrate common to all memory cells, and the capacitor electrode is used as a bit line, the high impurity concentration layer to which the fixed potential is applied is Providing this has an important meaning in preventing the substrate region of the MOSFET from becoming 70-tinged. Furthermore, in the case where the drain region is not used as a bit line as described above and the capacitor electrode is used as a bit line, in the present invention, the train region provided on the bottom surface of the convex portion is set to a desired potential 2, for example, Vcc (+5V) during operation. can be fixed to. The drain region covers all memory cells or
Since it can be provided commonly in the row or column direction, voltage application is easy. Since such a drain region absorbs electrons generated by α rays, soft errors in cell mode can be alleviated. Furthermore, by using the bit line as the capacitor electrode, soft errors in bit line mode are only caused by the board connections in the sense amplifier, so the board area involved in soft errors is reduced, which can be improved. I can do it.

[Embodiments of the invention]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic plan view of a memory cell array section of one embodiment, FIG. 2 is a cross-sectional view taken along line A-A'', and FIG. 3 is a MOSFET
It is a perspective view in the state where ET is formed. As shown in FIG. 2, in this embodiment, a p-type 3i substrate 11 has an n+-type layer 1 which serves as a MOSFET drain region common to all memory cells.
A wafer is used in which a p-type layer 13 is formed on the n-type layer 12 by epitaxial growth.

In such a wafer, grooves deep enough to reach the n+ type layer 12 are formed by anisotropic etching such as RIE, and a plurality of striped convex portions are formed, and a gate insulating film 14 is formed on the sidewall of each convex portion. A gate electrode 15 is continuously formed through the gate electrode. Gate electrode 15 is formed of a first layer polycrystalline silicon film. As is clear from FIG. 1 and FIG.
L3 and WL4,...) are configured. On the upper surface of the convex portion, n+ type layers 16, which serve as source regions of independent MOSFETs for each memory cell, are discretely arranged along both sides. The n+ type layer 16, which is the source region of each MOSFET thus formed, is the first electrode of the MOS capacitor, and the second electrode 19 of the capacitor is formed thereon via the capacitor insulating film 18. . This second electrode 19 is formed of a second@polycrystalline silicon film, and
As shown in the figure, a plurality of bits Wa 8L1. BL2゜BL3.
It consists of... The area surrounded by diagonal lines in FIG. 2 constitutes one memory cell.

On the other hand, on the surface of the p-type layer 13 in the convex portion, M of each memory cell is
p+ to ensure isolation between the source regions of the OSFETs.
A mold layer 17 is formed. As shown in FIG. 1, the p+ type layer 17 on each convex portion is connected to the power source I! via a contact hole at the edge of the substrate. 21, and a fixed potential is applied to the p+ type layer 17 via this power supply wiring.

FIG. 4(a) shows an equivalent circuit of a memory cell. M
As explained in FIG. 2, the drain of OSFET-Q is the n+ type layer 12 common to all bits, and this is connected to Vcc (eg, 5V) and φ.

For this purpose, contact is made between the Vcc line and the n+ type layer 12 around the chip. The gate electrode/word line WL of the MOS FET-Q is connected to the second electrode/pit line BL of the MOS capacitor C by the first layer polycrystalline silicon film.
As described above, is formed of the second layer polycrystalline silicon film.

Writing to this memory cell is shown in FIGS. 4(b) and 4(c).

An example of operating voltage during reading is shown. Vcc is a positive voltage, for example, +5V, and the substrate potential provided by the power supply wiring 21 is, for example, -3. First, as shown in FIG. 4(b), when writing or reading "O'°, the word line WL of the cell is set to 8V.
As a result, the MOSFET is turned on and the bit line BL is set to OV. As a result, the number of nodes Ns becomes approximately 5■. Writing is thereby performed. Then, WL is set to oV, and E3
When L is set to 5■, which is the same as Vcc, the potential of node Ns increases to about 9■. This is precharge. When reading this cell, 8V is applied to WL. As a result, the potential of 8L becomes 5-5X4XCs/(Cdays) [V]. Here, CB is the capacitance of the cell capacitor and Ca is the collateral capacity of BL. Therefore, it is sufficient to compare the potential of this 81 with a reference potential using a sense amplifier.

Similarly, when writing and reading 01'', see Figure 4 (C).
As shown, WL-8V, BL-5V, N5=5
Write as V. 1tWL=O during precharge
V, BL-5V, Ns -5V. Therefore WL=8
When V, 5V appears on BL, and 11111 is read.

The dRAM of this embodiment configured as described above has the following advantages. First, the memory cell of this embodiment consists of a vertical MOSFET formed on the side wall of the convex portion and an MOSFET superimposed on this.
Furthermore, since memory cells are formed on both side walls of the convex portion running in a stripe pattern, high density and high integration can be achieved. Further, since the second electrode of the capacitor formed continuously in one direction is used as a pit line, no contact is required in the memory cell portion, which is very effective for high integration. Furthermore, the distance between the MOS capacitor that stores information charge and the substrate 11 is M
Since they are separated by the n+ type layer 12 which becomes the drain region of the OSFET, they are resistant to soft errors.

Furthermore, when α particles are incident on the p-type layer 13, which is the substrate region of the MOSFET, the generated holes are absorbed by the p+-type layer 17 to which -3V is applied, and the electrons are absorbed by the n+-type layer 17 to which 5V is applied. Since it is absorbed by the mold layer 12, it is also resistant to soft errors in this sense. Furthermore, the p-type layer 13, which is the substrate region of the MOSFET, is separated from the substrate 11 by the n+-type layer 12, but the p+-type layer 17
As a result, stable transistor operation is obtained without floating. Furthermore, the gate electrode, which also serves as a word line, is arranged straight along the side wall of the striped convex portion, and can be formed by RIE without a mask. Therefore, the process is simple and a high yield can be expected.

FIG. 5 shows a cross section corresponding to the cross section of FIG. 2 of another embodiment of the present invention. Portions corresponding to those in the previous embodiment are given the same reference numerals and detailed explanations will be omitted. In this embodiment, a groove 22 is dug between the n+ type layers 16 on both sides of the surface of the convex portion. With such a structure, the n1 type layer 16
Since not only the top surface but also the side surface of the memory cell is used as a capacitor, the capacitance of the capacitor can be increased, and more preferable memory characteristics can be obtained.

FIG. 6 shows a perspective view corresponding to FIG. 3 of still another embodiment. Portions corresponding to those in the previous embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

In the previous embodiment, the MOSFETs were arranged symmetrically on both side walls of the striped convex portion, whereas in this embodiment, the MOSFETs were arranged alternately. Such a structure is effective, for example, when it is desired to realize a large capacitor capacity within a limited stripe width.

The present invention can be implemented with various other modifications.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of a dRAM according to an embodiment of the present invention;
Figure 2 is a cross-sectional view taken along the line A-A'', Figure 3 is a perspective view showing the state in which the MOSFET is formed, and Figures 4 (a) to (C) are equivalent circuit diagrams and operating voltage relationships of the memory cell. figure,
FIG. 5 shows another example 11... p-type 3i substrate, 12...
...n''' type layer (drain region), 13...p- type layer, 14... gate insulating film, 15... gate electrode (word line), 16... n+ type layer (source region 17...p+ type layer (separation layer), 1
8... Capacitor insulating film, 19... Capacitor second electrode (bit line), 20... Contact hole, 2
1...Power wiring. Figure 2 Figure 3 Figure 4 Figure 5 Cause Figure 6 Figure 7

Claims (2)

[Claims] (1) In a semiconductor memory device configured by integrating memory cells consisting of MOSFETs and MOS capacitors on a semiconductor substrate, the memory cells are arranged on the upper surface of a convex portion of the semiconductor substrate on which periodic striped concavities and convexities are formed. This MOSFET consists of a source region formed independently for each memory cell, a drain region provided on the bottom surface of the convex portion, and a gate electrode continuously arranged on the side wall of the convex portion, and this MOSFET.
a MOS capacitor in which the source region of the ET is used as a first electrode and a second electrode is formed thereon via an insulating film, and the source region of each MOSFET is separated in the convex portion; A semiconductor memory device characterized by having a high impurity concentration layer to which a fixed potential is applied. (2) The drain region of the MOSFET is formed of a high impurity concentration layer common to all memory cells, and the gate electrodes continuously arranged on both side walls of one convex portion constitute different word lines, and the 2. The semiconductor memory device according to claim 1, wherein the second electrode of the MOS capacitor is disposed continuously in a direction intersecting the gate electrode to form a bit line.