JPH0580141B2 - - Google Patents
Info
- Publication number
- JPH0580141B2 JPH0580141B2 JP61149582A JP14958286A JPH0580141B2 JP H0580141 B2 JPH0580141 B2 JP H0580141B2 JP 61149582 A JP61149582 A JP 61149582A JP 14958286 A JP14958286 A JP 14958286A JP H0580141 B2 JPH0580141 B2 JP H0580141B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- plating
- bump
- bumps
- current film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000007747 plating Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 30
- 229910000679 solder Inorganic materials 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明はメツキ手段によるフリツプチツプ用
バンプの形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of forming bumps for flip chips by plating means.
（従来の技術）
従来、この種のバンプの形成に関してハンダメ
ツキによる方法が例えば特開昭58−92229号公報
に開示されている。(Prior Art) Conventionally, a method using solder plating for forming this type of bump has been disclosed, for example, in Japanese Patent Laid-Open No. 58-92229.
以下はハンダメツキによるハンダパンプ形成の
一例を説明する。第３図の如く半導体ウエハー例
えばSiウエハー１上に形成された下地電極２を覆
つて導電物質によるカレントフイルム３が形成さ
れ、このカレントフイルム３の上記下地電極２と
対応する部分がハンダメツキする部分５となり、
この部分のレジスト４が除去されてメツキ時に電
流が流れるように露出されている。 An example of forming a solder pump by solder plating will be described below. As shown in FIG. 3, a current film 3 made of a conductive material is formed to cover a base electrode 2 formed on a semiconductor wafer, such as a Si wafer 1, and a portion 5 of the current film 3 corresponding to the base electrode 2 is solder-plated. Then,
This portion of the resist 4 is removed and exposed so that current can flow during plating.
次に第４図により、上記カレントフイルム３に
電流を流すための治具に対するウエハーの支持例
を示す。Siウエハー１は治具６に常法の如くセツ
トされるが電流を流すためのレジスト４の剥離部
分８を図の如く形成し、第５図に拡大して示すよ
うに上記治具６の金具７をカレントフイルム３と
接続させる。以上の如きウエハーは、第６図に示
すように陰極１０側にSiウエハー１を接続してメ
ツキ浴１１に浸漬し陽極９との間に電流を流す
と、上記カレントフイルム３の上記メツキ部５に
メツキが析出し、ハンダメツキバンプ１２が形成
されるのである。 Next, FIG. 4 shows an example of supporting a wafer with respect to a jig for passing a current through the current film 3. The Si wafer 1 is set on a jig 6 in the usual manner, but a peeled-off portion 8 of the resist 4 for passing current is formed as shown in the figure, and the metal fittings of the jig 6 are attached as shown in an enlarged view in FIG. 7 is connected to the current film 3. As shown in FIG. 6, when the Si wafer 1 is connected to the cathode 10 side and immersed in the plating bath 11, and a current is passed between the wafer and the anode 9, the plating portion 5 of the current film 3 Plating is deposited on the solder plating bump 12 to form a solder plating bump 12.
（発明が解決しようとする問題点）
しかしながら、バンプ形成に際して上記の如き
治具６を用いると、第８図に説明図として示すよ
うに電気力線１３の流れがSiウエハー１の端部に
回り込む部分でその密度が高く、即ちその部分で
ハンダメツキの析出量が多くなり、その結果Siウ
エハー１の周囲部分でのハンダバンプ１２ａが大
きく成長しICチツプ中心部のハンダバンプ１２
の大きさに対して不均一になるという問題点があ
つた（第９図）。(Problem to be Solved by the Invention) However, when the jig 6 as described above is used when forming bumps, the flow of the electric lines of force 13 wraps around the edge of the Si wafer 1, as shown in the explanatory diagram in FIG. The solder bump 12a in the peripheral part of the Si wafer 1 grows larger, and the solder bump 12a in the center of the IC chip grows larger.
There was a problem that it became non-uniform with respect to the size of (Fig. 9).
この発明は従来技術におけるかかるバンプの不
均一となる欠点を解決し、Siウエハー上に均一な
大きさのバンプを形成することのできるフリツプ
チツプ用バンプの成形方法を提供するものであ
る。 The present invention solves the drawback of non-uniformity of bumps in the prior art and provides a method for molding bumps for flip chips that can form bumps of uniform size on a Si wafer.
（問題点を解決するための手段）
この発明は上記問題点を解決するために、半導
体ウエハー上にカレントフイルム及びレジストを
順次積層形成し、レジストを選択的に除去してカ
レントフイルムの露出部を設け、この露出部上に
電気メツキ法によりバンプ形成するに際し、半導
体ウエハーの周辺部にもカレントフイルムの露出
部を設けてバンプメタルのメツキを行うようにし
たものである。(Means for Solving the Problems) In order to solve the above problems, the present invention sequentially forms a current film and a resist on a semiconductor wafer, and selectively removes the resist to remove the exposed portion of the current film. When bumps are formed on the exposed portions by electroplating, the exposed portions of the current film are also provided on the periphery of the semiconductor wafer, and bump metal is plated thereon.
（作用）
この発明においては以上のように、バンプのメ
ツキによる形成に際して、半導体ウエハーの周辺
部にカレントフイルムの露出部分を設けることに
より、上述の回り込む電気力線の密度増によるメ
ツキをこの部分に析出させ不均一な大きさのバン
プ形成を回避するようにしたものである。(Function) As described above, in this invention, when forming bumps by plating, by providing an exposed portion of the current film at the periphery of the semiconductor wafer, the plating due to the increase in the density of the electric lines of force that wraps around can be prevented in this portion. This is to avoid the formation of bumps of non-uniform size due to precipitation.
（実施例）
第１図にこの発明の一実施例によるハンダバン
プ形成方法を示す。上記と同様に治具６によりSi
ウエハー１を支持しメツキを行う。この場合Siウ
エハー１の周囲部においてレジストを略環状に全
て除去し、カレントフイルム３の露出部３ａを設
け治具６の金具７をカレントフイルム３と接続さ
せる。このようなウエハーの支持状態において以
下常法の如くSiウエハーへのメツキ作業を行うこ
とにより、ウエハー１の周囲部分に回り込んでく
る上述した電気力線に起因するメツキを上記露出
部３ａ上に析出させ得る。この結果、第２図に示
すようにSiウエハー１上には概ね均一な大きさの
バンプ１２を形成することができる。なお、本発
明の電気メツキ法を用いたバンプ形成方法は、上
記実施例で述べたハンダバンプの形成の外に、他
の金属バンプ例えば金バンプの形成にも適用可能
なものであり、さらにSiウエハーへのバンプ形成
の外に他の半導体ウエハー、例えばGaAsウエハ
ーへのバンプ形成にも適用可能なものである。(Embodiment) FIG. 1 shows a solder bump forming method according to an embodiment of the present invention. In the same way as above, use jig 6 to
The wafer 1 is supported and plated. In this case, the resist is completely removed in a substantially annular shape around the Si wafer 1, an exposed portion 3a of the current film 3 is provided, and the metal fitting 7 of the jig 6 is connected to the current film 3. In this supported state of the wafer, plating is performed on the Si wafer in the usual manner, thereby removing the plating caused by the above-mentioned electric lines of force that wrap around the wafer 1 onto the exposed portion 3a. It can be precipitated. As a result, bumps 12 of approximately uniform size can be formed on the Si wafer 1, as shown in FIG. The bump forming method using the electroplating method of the present invention is applicable not only to the formation of solder bumps as described in the above embodiments, but also to the formation of other metal bumps such as gold bumps. In addition to forming bumps on other semiconductor wafers, such as GaAs wafers, the invention is also applicable to forming bumps on other semiconductor wafers, such as GaAs wafers.
（発明の効果）
以上説明したようにこの発明によれば、半導体
ウエハーの周辺部にカレントフイルムの露出部分
を設け、電気メツキ時にこの露出部分に電気力線
（すなわちメツキ電流）を集中させ、この露出部
分の近傍のバンプ形成部への電気力線（すなわち
メツキ電流）の回り込みを防止することができ、
これによりウエハー全面に均一な大きさのバンプ
の形成を可能とし著しく製品歩留りを向上させ得
る。(Effects of the Invention) As explained above, according to the present invention, an exposed portion of the current film is provided at the periphery of a semiconductor wafer, and lines of electric force (i.e., plating current) are concentrated on this exposed portion during electroplating. It is possible to prevent lines of electric force (i.e. plating current) from going around to the bump forming part near the exposed part,
This makes it possible to form bumps of uniform size over the entire surface of the wafer, thereby significantly improving product yield.
第１図はこの発明におけるバンプ形成方法を実
施するためのバンプ形成前のウエハー支持平面
図、第２図は同バンプ形成後のウエハー平面図、
第３図は従来のハンダバンプ形成方法におけるバ
ンプ形成前のウエハー断面図、第４図は同治具へ
の支持平面部、第５図は同要部の断面図、第６図
は同メツキ時の説明図、第７図は同メツキ後のウ
エハーの断面図、第８図は同メツキ時の電気力線
の流れ説明図、第９図は同ウエハーの不均一ハン
ダバンプ成長の説明図である。
１……Siウエハー、３……カレントフイルム、
３ａ……露出部、６……治具、７……金具、１
２，１２ａ……ハンダバンプ。
FIG. 1 is a plan view of the wafer support before bump formation for carrying out the bump formation method of the present invention, FIG. 2 is a plan view of the wafer after the same bump formation,
Fig. 3 is a cross-sectional view of the wafer before bump formation in the conventional solder bump forming method, Fig. 4 is a flat support part for the same jig, Fig. 5 is a cross-sectional view of the main part, and Fig. 6 is an explanation of the plating process. 7 is a cross-sectional view of the wafer after plating, FIG. 8 is an explanatory diagram of the flow of electric lines of force during plating, and FIG. 9 is an explanatory diagram of non-uniform solder bump growth on the wafer. 1...Si wafer, 3...current film,
3a...Exposed part, 6...Jig, 7...Metal fitting, 1
2, 12a...Solder bump.
Claims (1)
全面上にカレントフイルム及びレジストを順次積
層形成し、バンプ形成部に位置する前記レジスト
の部分を除去して前記カレントフイルムの第１の
露出部を設けると共に、前記半導体ウエハーの周
辺部に位置する前記レジストの部分を除去して前
記カレントフイルムの第２の露出部を設けた後、
電気メツキ法により前記各露出部にバンプメタル
をメツキすることを特徴とするフリツプチツプ用
バンプ成形方法。1. A current film and a resist are sequentially laminated over the entire surface of a semiconductor wafer on which bumps are to be formed, and a first exposed portion of the current film is provided by removing a portion of the resist located in a bump forming area. At the same time, after removing a portion of the resist located at the periphery of the semiconductor wafer to provide a second exposed portion of the current film,
1. A method for forming a bump for a flip chip, comprising plating bump metal on each of the exposed portions using an electroplating method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61149582A JPS636860A (en) | 1986-06-27 | 1986-06-27 | Formation of solder bump for flip chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61149582A JPS636860A (en) | 1986-06-27 | 1986-06-27 | Formation of solder bump for flip chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS636860A JPS636860A (en) | 1988-01-12 |
| JPH0580141B2 true JPH0580141B2 (en) | 1993-11-08 |
Family
ID=15478348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61149582A Granted JPS636860A (en) | 1986-06-27 | 1986-06-27 | Formation of solder bump for flip chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS636860A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0636087B2 (en) * | 1990-04-26 | 1994-05-11 | 旭光学工業株式会社 | Finder device and camera equipped with finder device |
| US6042953A (en) * | 1996-03-21 | 2000-03-28 | Matsushita Electric Industrial Co., Ltd. | Substrate on which bumps are formed and method of forming the same |
| JP4493442B2 (en) * | 2004-08-24 | 2010-06-30 | Ｏｋｉセミコンダクタ株式会社 | Manufacturing method of semiconductor device and manufacturing apparatus used in the manufacturing method |
| JP2007048802A (en) * | 2005-08-08 | 2007-02-22 | Tdk Corp | Wiring board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5817638A (en) * | 1981-07-24 | 1983-02-01 | Hitachi Ltd | Bump forming device |
-
1986
- 1986-06-27 JP JP61149582A patent/JPS636860A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5817638A (en) * | 1981-07-24 | 1983-02-01 | Hitachi Ltd | Bump forming device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS636860A (en) | 1988-01-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4942455A (en) | Lead frame for a semiconductor device and a method for manufacturing a semiconductor device using the lead frame | |
| JPH10125685A (en) | Protruding electrode and its forming method | |
| JP2001168128A (en) | Method for fabricating semiconductor device | |
| JPH0580141B2 (en) | ||
| JPS636850A (en) | Manufacture of electronic component | |
| JP3212266B2 (en) | Bump forming apparatus and bump forming method | |
| JP2004047788A (en) | Method of manufacturing semiconductor device and apparatus for manufacturing semiconductor | |
| JPH03198342A (en) | Manufacture of semiconductor device | |
| JPH0722425A (en) | Manufacture of semiconductor device | |
| JP2882416B2 (en) | Method of forming metal element by electrolytic plating | |
| JP3583878B2 (en) | Electroplating method | |
| JPH0574780A (en) | Bump forming method | |
| JPH02217429A (en) | Plating method and apparatus | |
| JP3440348B2 (en) | Continuous plating method and continuous plating apparatus | |
| JP3360055B2 (en) | Lead plating equipment | |
| JP2643141B2 (en) | Method of manufacturing transfer bump | |
| JPH10135215A (en) | Method of forming bumps | |
| KR100246584B1 (en) | Lead frame and method of electrolytic polishing of leadframe | |
| JPS621249A (en) | Semiconductor device | |
| JPH0645282A (en) | Manufacturing method and device for semiconductor device | |
| JP2004018964A (en) | Semiconductor wafer and production method of semiconductor device | |
| JPH03254130A (en) | Manufacture of semiconductor device | |
| JP2926497B2 (en) | Method for manufacturing semiconductor device | |
| JPS59202643A (en) | Connecting method of large scale integration | |
| JP2001077145A (en) | Semiconductor device manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |