JPH0577316B2 - - Google Patents

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Publication number
JPH0577316B2
JPH0577316B2 JP62095855A JP9585587A JPH0577316B2 JP H0577316 B2 JPH0577316 B2 JP H0577316B2 JP 62095855 A JP62095855 A JP 62095855A JP 9585587 A JP9585587 A JP 9585587A JP H0577316 B2 JPH0577316 B2 JP H0577316B2
Authority
JP
Japan
Prior art keywords
superconducting
superconducting material
oxide superconducting
impurity
control electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62095855A
Other languages
Japanese (ja)
Other versions
JPS63261768A (en
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP62095855A priority Critical patent/JPS63261768A/en
Publication of JPS63261768A publication Critical patent/JPS63261768A/en
Publication of JPH0577316B2 publication Critical patent/JPH0577316B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0268Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661Processes performed after copper oxide formation, e.g. patterning
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/01Manufacture or treatment
    • H10N60/0884Treatment of superconductor layers by irradiation, e.g. ion-beam, electron-beam, laser beam or X-rays

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Description

【発明の詳现な説明】 「発明の利甚分野」 本発明はセラミツクス系超電導超䌝導ずも衚
す材料を甚いた固䜓電子デむバむスの䜜補方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Application of the Invention The present invention relates to a method for manufacturing a solid-state electronic device using a ceramic superconducting (also referred to as superconducting) material.

本発明は、入力端子ず出力端子ずを有する端
子端子を含む玠子の䜜補方法に関する。本
発明は、かかる玠子に増幅機胜、スむツチ機胜を
有せしめるずずもに、入力信号を制埡甚入力に印
加するこずにより出力信号を出力より怜出せしめ
んずするものである。
The present invention relates to a method for manufacturing a four-terminal (including three-terminal) element having an input terminal and an output terminal. The present invention provides such an element with an amplifying function and a switching function, and also detects an output signal from the output by applying an input signal to a control input.

「埓来の技術」 埓来、超電導材料、䟋えばNb−Ge系䟋ずし
おはNb3Ge等の金属材料を甚いお固䜓電子デ
むバむスを䜜る詊みがなされおきた。
"Prior Art" Conventionally, attempts have been made to fabricate solid-state electronic devices using superconducting materials, such as metal materials such as Nb-Ge (Nb 3 Ge, for example).

その代衚がゞペセフ゜ン玠子である。このゞペ
セフ゜ン玠子は、超電導珟象ずトンネル電流珟象
ずを組み合わせ、スむツチングを行わんずするも
ので、端子回路よりな぀おいる。
A typical example is the Josephson device. This Josephson element attempts to perform switching by combining superconductivity and tunnel current phenomena, and consists of a two-terminal circuit.

「埓来の問題点」 しかし、かかるゞペセフ゜ン玠子は端子回路
玠子であるため、入力信号ず出力信号ずを独立信
号ずしお甚いるこずができない。このため工業甚
応甚を考える時、超高呚波で動䜜させるこずがで
きるずいう特長を有し぀぀も、回路蚭蚈がきわめ
お困難であり、これたでの半導䜓集積回路で培わ
れおいる蚭蚈技術を甚いるこずができないずいう
欠点を有する。
"Conventional Problems" However, since such a Josephson device is a two-terminal circuit device, the input signal and output signal cannot be used as independent signals. For this reason, when considering industrial applications, although it has the feature of being able to operate at ultra-high frequencies, circuit design is extremely difficult, and it is difficult to use the design technology that has been cultivated in conventional semiconductor integrated circuits. It has the disadvantage that it cannot.

特に端子玠子であるため、信号の増幅機胜を
有さず、系党䜓においお入力端より出力端に至る
たでに信号が若干枛衰しお、いわゆる利埗ゲむ
ンを以䞊ずするこずができないずいう倧きな
欠点を有する。
In particular, since it is a two-terminal element, it does not have a signal amplification function, and the signal is attenuated slightly from the input end to the output end in the entire system, making it impossible to achieve a so-called gain of 1 or more. It has major drawbacks.

本発明はかかる欠点を陀去し、超高呚波動䜜を
させるずずもに玠子を端子回路玠子、即ち入力
信号を加える制埡甚電極および出力信号を導出す
る電極ずを有せしめんずするものである。
The present invention aims to eliminate such drawbacks, operate at very high frequencies, and provide a four-terminal circuit element, that is, a control electrode for applying an input signal and an electrode for deriving an output signal.

「問題を解決すべき手段」 本発明はかかる問題を解決するため、超電導セ
ラミツク材料セラミツクスを甚いた端子固
䜓電子玠子デむバむス構造を有せしめるもの
である。
"Means to Solve the Problem" In order to solve the problem, the present invention provides a four-terminal solid-state electronic element (device) structure using superconducting ceramic material (ceramics).

本発明は、非超電導性の絶瞁性衚面を有する基
板䞊に超電導性を有するセラミツクスを蚭け、そ
の䞀郚領域に動䜜させる枩床で有限抵抗を有する
第の超電導セラミツクスを蚭ける。そしおその
セラミツクスの䞀方および他方には抵抗が零にな
る第の超電導セラミツクスを蚭けおいる。
In the present invention, a superconducting ceramic is provided on a substrate having a non-superconducting insulating surface, and a first superconducting ceramic having a finite resistance at an operating temperature is provided in a partial region thereof. A second superconducting ceramic having zero resistance is provided on one and the other of the ceramics.

この有限抵抗を有するセラミツクスは、超電導
性セラミツクスに䞍玔物を添加し、この䞍玔物に
より超電導性を匱く砎壊せしめたものである。さ
らにこの第の超電導性セラミツクスの䞊面たた
は䞋面には、ここを流れる電流を制埡する制埡甚
電極が蚭けられおいる。この制埡甚電極ずセラミ
ツクスずの間に、電流の授受を犁止すべき被膜、
特に絶瞁膜が蚭けられおいる。
Ceramics with finite resistance are made by adding impurities to superconducting ceramics, and the impurities weakly destroy the superconductivity. Furthermore, a control electrode is provided on the upper or lower surface of the first superconducting ceramic to control the current flowing therethrough. Between this control electrode and the ceramics, there is a coating that should prohibit the transfer of current.
In particular, an insulating film is provided.

本発明は、有限抵抗を有する第の超電導性セ
ラミツクスは抵抗零の第の超電導性セラミツク
スず同䞀成分を甚い、ここにむオン泚入法等によ
り䞍玔物を添加したものである。
In the present invention, the first superconducting ceramic having finite resistance uses the same components as the second superconducting ceramic having zero resistance, and impurities are added thereto by ion implantation or the like.

この䞍玔物は超電導セラミツクスを構成する元
玠、䟋えばむツトリナヌム、銅Cu、バリ
ナヌムBa、酞玠(O)であ぀おもよい。かかる䞍
玔物は、超電導を呈する化孊良論比を狂わせる皋
床に倚量に添加する必芁がある。具䜓的には×
1019〜×1021cm-3のオヌダである。
This impurity may be an element constituting the superconducting ceramic, such as Y (yttrium), copper (Cu), barium (Ba), or oxygen (O). Such impurities need to be added in large amounts to the extent that they disturb the chemical stoichiometric ratio that exhibits superconductivity. Specifically 5×
It is on the order of 10 19 to 5×10 21 cm −3 .

たた、他の䞍玔物ずしお鉄Fe、ニツケル
Ni、コバルトCo、珪玠Si、ゲルマニナ
ヌムGe、ホり玠(B)、アルミニナヌムAl、
ガリナヌムGa、リン(P)、砒玠Asより遞
ばれた皮類たたは耇数皮類がある。かかる堎
合、その䞍玔物の濃床は×1015〜×1020cm-3
ずした。
In addition, other impurities include iron (Fe), nickel (Ni), cobalt (Co), silicon (Si), germanium (Ge), boron (B), aluminum (Al),
There is one or more types selected from galium (Ga), phosphorus (P), and arsenic (As). In such a case, the concentration of the impurity is between 5×10 15 and 3×10 20 cm -3
And so.

本発明の超電導玠子においおは、第の超電導
性セラミツクスずするため、第の超電導セラミ
ツクスに䞍玔物を添加する。これにより、Tco
抵抗を零ずする枩床は䞋がるが、Tcオンセツ
トはあたり倉わらない。その結果、Tcオンセツ
トずTcoずの差が広がり、䞀般に10K以䞊を有せ
しめ埗る。
In the superconducting element of the present invention, impurities are added to the second superconducting ceramic to form the first superconducting ceramic. This allows Tco
(the temperature at which resistance becomes zero) decreases, but Tc onset does not change much. As a result, the difference between Tc onset and Tco widens and can generally be greater than 10K.

このための差が1Kたたはそれ以䞋しかできな
い埓来より公知の金属の超電導材料よりも、本発
明の玠子に甚いる材料はセラミツク材料のほうが
より奜たしい。
Ceramic materials are more preferred for use in the device of the present invention than conventionally known metallic superconducting materials, which have a difference of only 1K or less.

本発明は、䞀察の出力甚の超電導セラミツクス
間に連結した電極の間に、十分倧きい電気抵抗、
奜たしくは第の超電導材料の電気抵抗よりも10
倍以䞊の電気抵抗を有する被膜をその䞊面、䞋面
たたは䞡面に蚭けたものである。
The present invention has a sufficiently large electric resistance between electrodes connected between a pair of output superconducting ceramics.
Preferably the electrical resistance of the first superconducting material is 10
A coating having an electrical resistance more than double that is provided on the upper surface, lower surface, or both surfaces.

本発明においおは、この制埡甚電極ず超電導被
膜ずの間に、超電導性セラミツクスの電気抵抗よ
り十分倧きい電気抵抗を有する被膜、奜たしくは
絶瞁膜を蚭け、入力端子である制埡甚電極から電
圧を印加させ、その䞋偎の超電導性セラミツクス
に電圧を印加する。このセラミツクスは、完党に
超電導を有する状態ずた぀たく超電導を有さない
状態の䞭間状態䞀郚が超電導性を有し、䞀郚が
非超電導性の状態、即ちTcオンセツトTcoずの
間の枩床領域の状態であるため、自らのポテン
シダルを入力の制埡甚電極に加えられた電圧に埓
぀お倉化、制埡させるこずができる。
In the present invention, a film, preferably an insulating film, having an electrical resistance sufficiently higher than the electrical resistance of the superconducting ceramic is provided between the control electrode and the superconducting film, and a voltage is applied from the control electrode, which is an input terminal. Then, a voltage is applied to the superconducting ceramic underneath. This ceramic is produced in an intermediate state between completely superconducting and completely non-superconducting (partly superconducting and partially non-superconducting, that is, at a temperature between Tc onset and Tco). (region state), it is possible to change and control its own potential according to the voltage applied to the input control electrode.

本発明に甚いられる制埡甚電極ずセラミツクス
ずの䞭間に介圚する被膜の絶瞁性は、もし入力信
号を䞎える時の電流をも機構䞊においお無芖させ
埗るならば、陀去しおした぀おも、たたその間に
介圚させる被膜の抵抗を10倍以䞋ずしたものでも
可である。
The insulating properties of the coating interposed between the control electrode and the ceramic used in the present invention can be removed even if the current applied to the input signal can be ignored in terms of the mechanism. It is also possible to use a coating whose resistance is 10 times or less.

本発明においお、この超電導性セラミツクス
は、制埡甚電極が第図たたはに瀺す劂く、
぀のみであ぀た堎合、その反察面にたでポテン
シダルの倉曎をせしめ埗べく、0.01〜10Όず比
范的薄くするこずが重芁である。たた制埡甚電極
をこのセラミツクスの䞊䞋に第図に瀺す劂く
個蚭ける堎合は、この厚さは0.1〜50Όず平均
しお玄倍であ぀おもよい。
In the present invention, the superconducting ceramic has a control electrode as shown in FIG. 1A or B.
If there is only one layer, it is important to make it relatively thin, 0.01 to 10 ÎŒm, so that the potential can be changed even on the opposite side. In addition, when two control electrodes are provided above and below the ceramic as shown in FIG. 1C, the thickness may be 0.1 to 50 ÎŒm, which is about 5 times the thickness on average.

第図は本発明の固䜓玠子の瞊断面
図を瀺す。
1A, B, and C show longitudinal cross-sectional views of the solid-state device of the present invention.

第図における第を超電導セラミツクス
は第図の特性における特性を甚い
る。この特性のTcoは本発明の固䜓玠子の䜿
甚枩床ここでは液䜓窒玠枩床では抵抗は
零たたは零に十分近い倀ずなる。
2 in Fig. 1 is superconducting ceramics 3,
5 uses characteristic 16 in characteristics 3 and 5 in FIG. With this characteristic, Tco28 has a resistance of zero or a value sufficiently close to zero at the operating temperature (liquid nitrogen temperature in this case) of the solid state element of the present invention.

本発明では第の超電導性セラミツクスを党䜓
に圢成し、所望の圢状にフオト゚ツチングする。
この埌この第の超電導性セラミツクスを䜜るた
め、この領域のみに遞択的に䞍玔物を添加した。
そしおこの領域のみ第の超電導性セラミツクス
のTcoずは異なるTcoを有せしめた。こ
の䞍玔物の添加の巟は0.01〜5Ό奜たしくは0.1〜
1Όず、チダネルの長さをフオトリ゜グラフむ技
術を甚いお可胜な限り短くした。むオン泚入によ
る䞍玔物は×1015〜×1021cm-3ずし、この深
さ方向においおこの膜を暪切぀お泚入する。さら
にこれら党䜓を400〜1000℃、䟋えば600℃で10時
間酞玠䞭でアニヌルを行い、この䞍玔物を酞化せ
しめるずずもに、結晶構造を敎えた。かくしお、
第図における第の超電導性セラミツクス
は、䟋えば第図における超電導セラミツクスの
枩床−固有抵抗特性における曲線を甚いる。こ
れはTcoずTcオンセツトずの䞭間領域
を甚いる。
In the present invention, a second superconducting ceramic is formed over the entire surface and photoetched into a desired shape.
Thereafter, impurities were selectively added only to this region in order to produce the first superconducting ceramic.
Only this region was made to have a Tco26 different from Tco28 of the second superconducting ceramic. The width of this impurity addition is 0.01 to 5Ό, preferably 0.1 to 5Ό
The length of the channel was made as short as possible, 1ÎŒ, using photolithography technology. The impurity by ion implantation is 5×10 15 to 3×10 21 cm −3 and is implanted across the film in the depth direction. Furthermore, the whole was annealed in oxygen at 400 to 1000°C, for example 600°C, for 10 hours to oxidize the impurities and adjust the crystal structure. Thus,
First superconducting ceramic 4 in FIG.
For example, curve 4 of the temperature-specific resistance characteristics of superconducting ceramics in FIG. 3 is used. This uses the intermediate region between Tco 26 and Tc onset 25.

第図においお、非超電導性を有する絶瞁衚
面を有する基䜓䞊の第の超電導性セラミツク
スおよび第の超電導セラミツクスおよび
よりなるセラミツクスを構成せしめる。その出
力甚の䞀察の電極図面では省略を図面
における巊右の端郚に蚭ければよい。たた、制埡
甚電極䞋には被膜を蚭けおいる。
In FIG. 1A, a first superconducting ceramic 4 and a second superconducting ceramic 3 and 5 on a substrate 1 having a non-superconducting insulating surface are shown.
The ceramics 2 is made up of: A pair of output electrodes 8 and 9 (not shown in the drawing) may be provided at the left and right ends in the drawing. Further, a coating 11 is provided under the control electrode 10.

第図は制埡甚電極が第の超電導性セ
ラミツクスの䞊偎に蚭けられ、第図では䞋
偎に蚭けられおいる。第図では被膜は超電導
性セラミツクスの䞊䞋䞡面に蚭けられ、さらに
制埡甚電極がそれぞれ′ずしお蚭けら
れおいる。
In FIG. 1A, the control electrode 10 is provided on the upper side of the first superconducting ceramic 4, and in FIG. 1B, it is provided on the lower side. In FIG. 1C, coatings are provided on both the upper and lower surfaces of the superconducting ceramic 4, and control electrodes 10 and 10' are provided, respectively.

第図の䜜補方法は、非超電導衚面を有する
基䜓䞊に制埡甚電極を蚭け、この電極を芆぀お十
分電気抵抗の倧きい被膜を圢成する。次にこれら
党䜓に第の超電導セラミツクスを圢成する。そ
の埌、制埡甚電極䞊面のみを残し、他をフオトマ
スクで芆い、むオン泚入法により䞍玔物を添加す
る。さらにこのフオトレゞストを陀去した埌、党
䜓を酞玠雰囲気で加熱酞化し、第の超電導セラ
ミツクスを構成せしめる。その他は第図ず同
様である。
In the manufacturing method shown in FIG. 1B, a control electrode is provided on a substrate having a non-superconducting surface, and a film having a sufficiently high electrical resistance is formed to cover this electrode. Next, a second superconducting ceramic is formed over the entire structure. Thereafter, only the upper surface of the control electrode is left, the rest is covered with a photomask, and impurities are added by ion implantation. After removing this photoresist, the entire structure is heated and oxidized in an oxygen atmosphere to form a first superconducting ceramic. The rest is the same as in FIG. 1A.

第図は第図の構成をせしめた埌、再び
このセラミツクス䞊に絶瞁膜を圢成し、さらに他
の制埡甚電極を蚭けたものである。
In FIG. 2C, after the structure shown in FIG. 2B has been formed, an insulating film is again formed on this ceramic, and another control electrode is provided.

「䜜甚」 かかる構造ずするこずにより、入力信号ず出力
信号ずを独立関数ずしお制埡でき、か぀この玠子
をスむツチング甚玠子、増幅機胜を有する玠子ず
しお甚いるこずができる。
"Operation" With such a structure, the input signal and the output signal can be controlled as independent functions, and this element can be used as a switching element or an element having an amplification function.

本発明は、同䞀基板䞊に耇数個の固䜓玠子を䜜
るこずができ、かかる玠子を蚭蚈論理に基づき連
結するこずにより、超電導集積回路を䜜らんずし
た時、その盞互配線を抵抗零で䜜るこずができ
る。
The present invention makes it possible to create a plurality of solid-state devices on the same substrate, and when trying to create a superconducting integrated circuit by connecting such devices based on design logic, the mutual wiring can be created with zero resistance. I can do it.

以䞋に図面に埓぀お実斜䟋を説明する。 Examples will be described below with reference to the drawings.

実斜䟋  この実斜䟋は第図の構造を瀺す。Example 1 This embodiment shows the structure of FIG. 1A.

基板ずしおYSZむツトリナヌム・スタビラむ
ズド・ゞルコンを甚いた。これはその䞊にスク
リヌン印刷法、スパツタ法、MBEモレキナラ・
ビヌム・゚ピタキシダル法、CVD気盞反応
法等を甚いお超電導材料を圢成させる。この超電
導材料の䟋ずしお、A1-xBxyCuzOw、
〜、2.0〜4.0奜たしくは2.5〜3.5、
〜奜たしくは1.5〜3.5、〜10奜たしく
は〜を有する。はむツトリナヌム、
Guガドリニナヌム、Ybむツテルビナヌム、
Euナヌロピナヌム、Tbテルビナヌム、Dy
ゞスプロシナヌム、Hoホルミりム、Er゚
ルビりム、Tmツリりム、Luルテチりム、
Scスカンゞりムたたはその他の元玠呚期衚
族の぀たたは耇数皮類より遞ばれるはRa
ラゞナヌム、Baバリナヌム、Srストロンチ
ナヌム、Caカルシナヌム、Mgマグネシナヌ
ム、Beベリリナヌムの元玠呚期衚族よ
り遞ばれる。特にその具䜓䟋ずしおYBa2
Cu3O6〜8を甚いた。たたずしお元玠呚期衚に
おける前蚘した元玠以倖のランタニド元玠たたは
アクチニド元玠を甚い埗る。尚、明现曞における
元玠呚期衚は理化孊蟞兞岩波曞店1963幎月
日発行によるものである。
YSZ (yttrium stabilized zircon) was used as the substrate. This can be applied using the screen printing method, sputtering method, MBE (Molecular
Beam epitaxial) method, CVD (vapor phase reaction)
A superconducting material is formed using a method or the like. As an example of this superconducting material, (A 1-x Bx)yCuzOw, x=
0-1, y=2.0-4.0 preferably 2.5-3.5, z=
1 to 4, preferably 1.5 to 3.5, W=4 to 10, preferably 6 to 8. A is Y (Itztriyum),
Gu (Gadolinium), Yb (Itterbiyum),
Eu (europium), Tb (terubium), Dy
(dysprosium), Ho (holmium), Er (erbium), Tm (thulium), Lu (lutetium),
B selected from Sc (scandium) or one or more other elements in group a of the periodic table is Ra
(radium), Ba (barium), Sr (strontium), Ca (calcium), Mg (magnesium), Be (beryllium), group A of the periodic table of elements. Especially as a specific example (YBa 2 )
Cu3O6-8 was used . Further, as A, a lanthanide element or an actinide element other than the above-mentioned elements in the periodic table of elements can be used. In addition, the periodic table of elements in the specification is from the Physical and Chemistry Dictionary (Iwanami Shoten April 1, 1963).
(Published on 2017).

この圢成ず同時たたはその埌に、600〜1200℃
の枩床で熱アニヌルを〜20時間凊理しお䜜補し
た。かくしお第の超電導セラミツクスずしお第
図特性を埗るこずができた。
Simultaneously with or after this formation, 600-1200℃
It was fabricated by thermal annealing at a temperature of 5 to 20 hours. In this way, properties 3 and 5 in Figure 3 could be obtained as a second superconducting ceramic.

次に公知のフオトリ゜グラフむを甚いる。即ち
第図においお領域䞊にフオトレゞスト
を蚭け、このレゞストのない領域のみに遞択的
にむオン泚入法により䞍玔物が添加されるように
うした。䞍玔物であるアルミニナヌム、珪玠たた
は鉄を×1015〜×1021cm-3、䟋えば×1019
cm-3の濃床に添加した。この埌フオトレゞストを
陀去し、さらにこれら党䜓にアルミニナヌムを50
〜500Å、䟋えば100Åの厚さに真空蒞着たたは光
CVD法により圢成した。この埌これら党䜓を酞
化性雰囲気で玄400〜1000℃䟋えば700℃の枩床に
お党面アルミニナヌムを酞化し、酞化アルミニナ
ヌム絶瞁膜を構成せしめるずずもに、むオン
泚入法により添加された䞍玔物を酞化し、絶瞁物
に倉成した。この結果、領域のTcoを第図に
瀺す劂く、䞀郚のみが超電導特性の有限抵抗
の領域ずせしめた。
Next, known photolithography is used. That is, in FIG. 1A, a photoresist is provided on regions 5 and 6, and impurities are selectively added only to region 4 where there is no resist by ion implantation. Impurities such as aluminum, silicon or iron are contained in an amount of 5×10 15 to 3×10 21 cm -3 , e.g. 5×10 19
It was added to a concentration of cm -3 . After this, the photoresist is removed and aluminum is applied over the entire area.
Vacuum evaporation or light deposition to ~500Å, e.g. 100Å thickness
Formed by CVD method. Thereafter, the entire aluminum is oxidized in an oxidizing atmosphere at a temperature of about 400 to 1000 degrees Celsius, for example, 700 degrees Celsius, to form the aluminum oxide insulating film 11, and impurities added by ion implantation are oxidized to insulate the aluminum. transformed into a thing. As a result, as shown in FIG. 3, the Tco of region 4 was made to be only partially in the region of finite resistance with superconducting property 15.

この䞍玔物の添加は、第の超電導セラミツク
スを構成させる元玠を甚い、、、、の倀
を倉化させ、同じ凊理を行぀お第の超電導性セ
ラミツクスずするこずは有効である。かくの劂き
方法を甚いお、TcオンセツトをTco′より䞋
げた。かくしお第図曲線を埗た。
It is effective to add this impurity by using the elements constituting the second superconducting ceramic, changing the values of x, y, z, and w, and performing the same process to obtain the first superconducting ceramic. Using such a method, Tc onset 25 was lowered below Tco'. Thus, curve 4 in Figure 3 was obtained.

次に制埡甚電極を他の第の超電導セラミ
ツクスず同じ超電導セラミツクスにより同様の方
法で䜜補した。出力甚の電極はセラミツクス薄膜
に密接し、オヌム接觊がなされるべくした。
Next, the control electrode 10 was manufactured using the same superconducting ceramic as the other second superconducting ceramic by the same method. The output electrode was placed in close contact with the ceramic thin film to make ohmic contact.

第図はこの実斜䟋での動䜜を瀺す。 FIG. 2 shows the operation of this embodiment.

この図面で、暪軞は第図に察応した距離を瀺
し、瞊軞ぱネルギレベルポテンシダルを瀺
す。
In this drawing, the horizontal axis indicates distance corresponding to FIG. 1, and the vertical axis indicates energy level (potential).

第図においお、第の超電導セラミツク
ス、即ち出力の他端に電圧を印加する。するず
ポテンシダルを埗る。その結果、電子は
′の双方に量子論的に波動性においお存
圚するが、の方が十分倧きいため、電流ずし
おはずしお芳察される。
In FIG. 2A, a voltage is applied to the second superconducting ceramic, ie the other end 5 of the output. Then you will get a potential of 30. As a result, the electron is 2
0 and 20' exist in quantum theoretical wave nature, but since 20 is sufficiently larger, it is observed as 22 as a current.

第図においおは制埡甚電極に䜕らの電圧も
印加されおいない。
In FIG. 2A, no voltage is applied to the control electrode.

第図においお、制埡甚電極に負の電圧を印
加する。するず第の超電導セラミツクス即ち領
域のポテンシダルは第図のより第
図の′ぞず移る。その結果、圢成された
障壁に関連しお′は曎に小さくなり、たた
は障壁のため極端に小さくなる。かくしお、第
の超電導セラミツクスの領域より他の第の
超電導セラミツクスの領域ぞず䞀察の出力甚電
極間に電圧を印加しお電流′を流さんず
するず、実質的に電流は流れにくくなり、その倀
は抌さえられる。
In FIG. 2B, a negative voltage is applied to the control electrode. The potential 21 of the first superconducting ceramic, region 4, then moves from 24 in FIG. 2A to 24' in FIG. 2B. As a result, 20' becomes even smaller in relation to the formed barrier, and 20'
0 is extremely small because it is a barrier. Thus, when a voltage 30 is applied between the pair of output electrodes to cause a current 22' to flow from the region 3 of the second superconducting ceramic to the other region 5 of the second superconducting ceramic, the current is substantially It becomes difficult to flow and its value is suppressed.

結果ずしお、制埡甚電極に負の電圧が印加され
るず電流′は小さくなる。
As a result, current 22' becomes smaller when a negative voltage is applied to the control electrode.

たた第図は制埡甚電極に正の電圧′を
印加した堎合を瀺す。電子の繊維確率′は倧
きくなり、逆には小さくなる。しかしこの領
域の井戞は電子で埋められ、″のバリアは
に芋掛け䞊のポテンシダルに移぀た埌、実質
的に消倱する。結果ずしお第図ず同じたたは
それに近い電流″が流れる。
Further, FIG. 2C shows the case where a positive voltage 21' is applied to the control electrode. The electron fiber probability 20' increases, and conversely 20 decreases. However, this well in region 4 is filled with electrons, and the barrier at 24'' virtually disappears after moving to the apparent potential at 25.As a result, a current 22'' equal to or close to that of Figure 2A flows. .

かくしお入力信号のポテンシダルにより出力電
流を怜出できる。この時、制埡電極䞋の被膜の抵
抗が十分であり、入力信号を䟛絊するための゚ネ
ルギ構造よりも出力信号を倧きく取り出し埗るな
らば増巟をしたこずずなり、端子玠子でありか
぀増幅装眮ずし埗る。この出力を電圧で怜出せん
ずするならば、この出力は盎列に抵抗を第図
に瀺す劂くにしお加えれば、その電流より電圧ず
しお怜出できる。即ちむンバヌタを䜜り埗る。
In this way, the output current can be detected based on the potential of the input signal. At this time, if the resistance of the film under the control electrode is sufficient and the output signal can be extracted larger than the energy structure for supplying the input signal, then the width has been increased, and it is a 4-terminal element and can be used as an amplifier. obtain. If you want to detect this output as a voltage, connect a resistor in series with the output as shown in Figure 2A.
If it is added as shown in the figure, the current can be detected as a voltage. In other words, an inverter can be made.

第図は、第図に関連しお既に説明したが、
本発明を実斜するために䜜られた第の超電導性
セラミツクスおよび第の超電導セラミツクス
の実際のデヌタを瀺す。
Although FIG. 3 has already been explained in connection with FIG.
Actual data of the first superconducting ceramic 4 and the second superconducting ceramics 3, 5 made to carry out the present invention are shown.

図面においお、暪軞は絶察枩床(K)を、たた瞊軞
は固有抵抗を瀺す。このデヌタでは4.2Kたで枬
定しおいる。しかし、この図面においお明らかな
劂く、第の超電導性セラミツクスでは超電導
がおきるTcオンセツトより䜎い枩床では比抵抗
が挞枛し、抵抗が零ずなる枩床Tco以䞋では抵抗
が零になる。このTcオンセツトおよびTcoずの
間の10および90をここではTc10Tc90ずし
お瀺しおいる。本発明の超電導玠子は、Tcオン
セツトずTcoずの間であればよいが、動䜜をより
安定化するため、Tc10Tc90を甚いるこずが奜
たしい。たたその動䜜スピヌドを速くせしめんた
めには、Tco〜Tc10の間の特性を甚いるず奜たし
い。
In the drawings, the horizontal axis represents absolute temperature (K), and the vertical axis represents specific resistance. This data measures up to 4.2K. However, as is clear from this drawing, in the first superconducting ceramic 4, the specific resistance gradually decreases at a temperature lower than the Tc onset at which superconductivity occurs, and the resistance becomes zero below the temperature Tco at which the resistance becomes zero. The 10% and 90% between this Tc onset and Tco are shown here as Tc 10 and Tc 90 . The superconducting element of the present invention may have any value between Tc onset and Tco, but it is preferable to use Tc 10 and Tc 90 in order to further stabilize the operation. Further, in order to increase the operating speed, it is preferable to use a characteristic between Tco and Tc 10 .

さらに第の超電導セラミツクスも同様
にTcオンセツト、Tco′を構成しおいる。
Further, the second superconducting ceramics 3 and 5 similarly constitute the Tc onset 27 and Tco'28.

第図においお、Tcoは材料に添加される
䞍玔物の皮類、量を制埡するこずにより可倉され
埗る。
In FIG. 3, Tco26 can be varied by controlling the type and amount of impurities added to the material.

このデヌタは高枩偎より䜎枩偎に、たた䜎枩偎
より高枩偎に枩床を替えおず぀おも再珟性を有し
おいた。実斜䟋の実隓は液䜓窒玠枩床で実
隓したものである。
This data was highly reproducible when changing the temperature from a high temperature side to a low temperature side, and from a low temperature side to a high temperature side. The experiment of Example 1 was conducted at a liquid nitrogen temperature of 30°C.

「効果」 本発明はこれたで端子玠子であ぀た超電導玠
子を端子玠子ずしたこずにある。この制埡甚電
極䞋に、この電極によりポテンシダルの倉化する
TcオンセツトずTcoずの䞭間の状態を広い枩床
範囲で有する第の超電導性セラミツクスを蚭
け、さらにその電極・リヌドを構成させるため、
かかる枩床領域では抵抗が零たたは零に十分近い
第の超電導セラミツクスで盞互配線ずしたもの
である。かくしお、制埡甚電極の電圧に埓぀お出
力電流を増幅し、か぀制埡させるこずが可胜ずな
぀た。
"Effects" The present invention consists in changing the superconducting element, which has hitherto been a two-terminal element, to a four-terminal element. Under this control electrode, the potential changes with this electrode.
In order to provide a first superconducting ceramic that has a state intermediate between Tc onset and Tco over a wide temperature range, and to configure its electrodes and leads,
In such a temperature range, the interconnection is made of a second superconducting ceramic whose resistance is zero or sufficiently close to zero. In this way, it has become possible to amplify and control the output current according to the voltage of the control electrode.

このため、この超電導固䜓玠子を同䞀基板に倚
数個蚭け、集積化させるこずが可胜ずな぀た。
Therefore, it has become possible to provide a large number of these superconducting solid-state devices on the same substrate and integrate them.

本発明においおは制埡甚電極をケを瀺した
が、これをケたたはそれ以䞊を盎列たたは䞊列
に蚭けおもよい。
Although one control electrode is shown in the present invention, two or more control electrodes may be provided in series or in parallel.

本発明においお、超電導材料ずしおセラミツク
材料を甚いた。しかし本発明の技術思想より明ら
かな劂く、TcずTcoずの間の枩床範囲が広い材
料奜たしくは10〓以䞊ある材料であれば、酞化物
セラミツクスである必芁はなく、任意に遞ぶこず
ができるこずはいうたでもない。
In the present invention, a ceramic material was used as the superconducting material. However, as is clear from the technical concept of the present invention, any material having a wide temperature range between Tc and Tco, preferably 10〓 or more, does not need to be an oxide ceramic and can be selected arbitrarily. Needless to say.

本発明においお、超電導性セラミツクスずいう
衚題を甚いた。しかしこれは超電導材料が酞化物
であるこずによる。その結晶構造は倚結晶であ぀
おも、たた単結晶であ぀おもよいこずは、本発明
の技術思想においお明らかである。特に単結晶構
造の堎合には、超電導材料を甚いるに際し、基板
䞊に゚ピタキシアル成長させればよい。
In the present invention, the title superconducting ceramics is used. However, this is due to the fact that the superconducting material is an oxide. It is clear from the technical concept of the present invention that the crystal structure may be polycrystalline or single crystalline. In particular, in the case of a single crystal structure, when using a superconducting material, it is sufficient to epitaxially grow it on the substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第図は本発明の超電導固䜓玠子の瞊断面図を
瀺す。第図は本発明の超電導固䜓玠子の動䜜原
理を瀺す。第図は本発明に甚いた超電導特性を
有するセラミツクスの枩床特性䟋を瀺す。
FIG. 1 shows a longitudinal cross-sectional view of a superconducting solid-state device of the present invention. FIG. 2 shows the operating principle of the superconducting solid state device of the present invention. FIG. 3 shows an example of the temperature characteristics of ceramics having superconducting properties used in the present invention.

Claims (1)

【特蚱請求の範囲】  非超電導性衚面を有する基䜓䞊に酞化物超電
導材料を圢成する工皋ず、 該酞化物超電導材料の䞀郚領域に遞択的に䞍玔
物を添加しお前蚘酞化物超電導材料より䜎いTcp
を有せしめる工皋ず、 前蚘䞀郚領域䞊に制埡甚電極を圢成する工皋ず
を有し、 前蚘䞍玔物は前蚘酞化物超電導材料の構成元玠
より遞ばれた元玠、たたは鉄Fe、ニツケル
Ni、コバルトCo、珪玠Si、ゲルマニナ
ヌムGe、ホり玠(B)、アルミニナヌムAl、
ガリナヌムGa、リン(P)、砒玠Asより遞
ばれた元玠であり、 前蚘酞化物超電導材料の構成元玠より遞ばれた
䞍玔物は、その添加濃床が×1019〜×1021cm
-3であり、 前蚘鉄Fe、ニツケルNi、コバルト
Co、珪玠Si、ゲルマニナヌムGe、ホり
玠(B)、アルミニナヌムAl、ガリナヌムGa、
リン(P)、砒玠Asより遞ばれた䞍玔物は、そ
の添加濃床が×1015〜×1020cm-3であるこず
を特城ずする超電導玠子の䜜補方法。  特蚱請求の範囲第項においお、制埡甚電極
は酞化物超電導材料を芆぀お酞化物超電導材料よ
り十分倧きい電気抵抗を有する被膜を圢成した埌
に圢成するこずを特城ずする超電導玠子の䜜補方
法。  非超電導性衚面を有する基䜓䞊に制埡甚電極
を圢成する工皋ず、 前蚘基䜓䞊および前蚘電極䞊に酞化物超電導材
料を圢成する工皋ず、前蚘制埡甚電極䞊の酞化物
超電導材料に䞍玔物を添加し、前蚘酞化物超電導
材料より䜎いTcoを有せしめる工皋ずを有し、 前蚘䞍玔物は前蚘酞化物超電導材料の構成元玠
より遞ばれた元玠、たたは鉄Fe、ニツケル
Ni、コバルトCo、珪玠Si、ゲルマニナ
ヌムGe、ホり玠(B)、アルミニナヌムAl、
ガリナヌムGa、リン(P)、砒玠Asより遞
ばれた元玠からなり、 前蚘酞化物超電導材料の構成元玠より遞ばれた
䞍玔物は、その添加濃床が×1019〜×1021cm
であり、 前蚘鉄Fe、ニツケルNi、コバルト
Co、珪玠Si、ゲルマニナヌムGe、ホり
玠(B)、アルミニナヌムAl、ガリナヌムGa、
リン(P)、砒玠Asより遞ばれた䞍玔物は、そ
の添加濃床が×1015〜×1020cm-3であるこず
を特城ずする超電導玠子の䜜補方法。  特蚱請求の範囲第項においお、酞化物超電
導材料は制埡甚電極䞊に酞化物超電導材料よりも
十分抵抗の倧きい被膜を圢成した埌に圢成するこ
ずを特城ずする超電導玠子の䜜補方法。
[Claims] 1. A step of forming an oxide superconducting material on a substrate having a non-superconducting surface, and selectively adding an impurity to a partial region of the oxide superconducting material to make the oxide superconducting material thinner. Low T cp
and a step of forming a control electrode on the partial region, and the impurity is an element selected from the constituent elements of the oxide superconducting material, iron (Fe), nickel (Ni), etc. ), cobalt (Co), silicon (Si), germanium (Ge), boron (B), aluminum (Al),
The impurity is an element selected from gallium (Ga), phosphorus (P), and arsenic (As), and the impurity selected from the constituent elements of the oxide superconducting material has an additive concentration of 5×10 19 to 5×10 21 cm
-3 , and the above-mentioned iron (Fe), nickel (Ni), cobalt (Co), silicon (Si), germanium (Ge), boron (B), aluminum (Al), gallium (Ga),
A method for producing a superconducting element, wherein the impurity selected from phosphorus (P) and arsenic (As) has an additive concentration of 5 x 1015 to 5 x 1020 cm -3 . 2. A method for producing a superconducting element according to claim 1, characterized in that the control electrode is formed after forming a film covering the oxide superconducting material and having a sufficiently higher electrical resistance than the oxide superconducting material. 3. Forming a control electrode on a substrate having a non-superconducting surface; Forming an oxide superconducting material on the substrate and the electrode; and adding impurities to the oxide superconducting material on the control electrode. the impurity is an element selected from the constituent elements of the oxide superconducting material, or iron (Fe), nickel (Ni), cobalt ( Co), silicon (Si), germanium (Ge), boron (B), aluminum (Al),
The impurity is made of an element selected from gallium (Ga), phosphorus (P), and arsenic (As), and the impurity selected from the constituent elements of the oxide superconducting material has an additive concentration of 5×10 19 to 5×10 21 cm
The above iron (Fe), nickel (Ni), cobalt (Co), silicon (Si), germanium (Ge), boron (B), aluminum (Al), gallium (Ga),
A method for producing a superconducting element, wherein the impurity selected from phosphorus (P) and arsenic (As) has an additive concentration of 5 x 1015 to 5 x 1020 cm -3 . 4. A method for manufacturing a superconducting element according to claim 3, characterized in that the oxide superconducting material is formed after forming a film having a sufficiently higher resistance than the oxide superconducting material on the control electrode.
JP62095855A 1987-04-18 1987-04-18 Manufacture of superconducting element Granted JPS63261768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62095855A JPS63261768A (en) 1987-04-18 1987-04-18 Manufacture of superconducting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62095855A JPS63261768A (en) 1987-04-18 1987-04-18 Manufacture of superconducting element

Publications (2)

Publication Number Publication Date
JPS63261768A JPS63261768A (en) 1988-10-28
JPH0577316B2 true JPH0577316B2 (en) 1993-10-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP62095855A Granted JPS63261768A (en) 1987-04-18 1987-04-18 Manufacture of superconducting element

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Country Link
JP (1) JPS63261768A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS564290A (en) * 1979-06-25 1981-01-17 Nippon Telegr & Teleph Corp <Ntt> Superconductive element
JPS5873172A (en) * 1981-10-27 1983-05-02 Nippon Telegr & Teleph Corp <Ntt> Superconductive integrated circuit device
JPS60160675A (en) * 1984-02-01 1985-08-22 Hitachi Ltd Quasi-particle injection type superconducting element
JPS60223175A (en) * 1984-04-19 1985-11-07 Hitachi Ltd Superconductive switching device
JPS61206279A (en) * 1985-03-11 1986-09-12 Hitachi Ltd Superconductive element
JPS62238674A (en) * 1986-04-09 1987-10-19 Rikagaku Kenkyusho Manufacture of superconductor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS564290A (en) * 1979-06-25 1981-01-17 Nippon Telegr & Teleph Corp <Ntt> Superconductive element
JPS5873172A (en) * 1981-10-27 1983-05-02 Nippon Telegr & Teleph Corp <Ntt> Superconductive integrated circuit device
JPS60160675A (en) * 1984-02-01 1985-08-22 Hitachi Ltd Quasi-particle injection type superconducting element
JPS60223175A (en) * 1984-04-19 1985-11-07 Hitachi Ltd Superconductive switching device
JPS61206279A (en) * 1985-03-11 1986-09-12 Hitachi Ltd Superconductive element
JPS62238674A (en) * 1986-04-09 1987-10-19 Rikagaku Kenkyusho Manufacture of superconductor

Also Published As

Publication number Publication date
JPS63261768A (en) 1988-10-28

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