JPH0575123A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a high-density integrated circuit in which MOS transistors are formed on an SOI structure, while preventing substrate bias effects. CONSTITUTION:A semiconductor device includes a substrate 10, an oxide film 12 on the substrate, a semiconductor layer 14 on the oxide film, a channel region 14a in the semiconductor layer, a source region 14b and a drain region 14c formed on opposite sides of the channel region in the semiconductor layer, a gate oxide film 16 on the channel region, and a gate electrode 18 on the gate oxide film. The oxide film 12 forms a tunneling oxide film 13 under the channel region 14a in the semiconductor layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, especially SOI.
The present invention relates to a semiconductor device in which a MOS transistor is formed on a semiconductor layer having a structure.

[0002]

2. Description of the Related Art A conventional semiconductor device having an SOI structure will be described with reference to FIG. An oxide film 12 having a film thickness of about 1 μm is formed on the support substrate 10, and a film thickness of 2 μm is formed on the oxide film 12.
The p-type semiconductor layer 14 of m is formed, and SO
I structure. The semiconductor layer 14 is the element isolation layer 2
The element region is defined by 0. A p-type channel region 14a is formed at the center of the element region in the semiconductor layer 14, and an n-type source region 14b and a drain region 14c are formed opposite to each other with the channel region 14a interposed therebetween. .. A gate electrode 18 is formed on the channel region 14a via a gate oxide film 16 having a film thickness of 20 to 50 nm.

In the case of such an SOI structure NMOS transistor, the channel region 14a in the semiconductor layer 14 is
The holes of opposite charge to the electrons that are carriers are trapped,
A substrate bias effect is generated by the trapped holes. In order to suppress this substrate bias effect, a p-type back gate region 28 is formed in a part of the source region 14b of the semiconductor layer 14, for example. Back gate area 28
Are formed so as to be continuous with the channel region 14a so that holes generated in the channel region 14a are extracted.

[0004]

As described above, in the conventional transistor having the SOI structure, the substrate bias effect caused by the holes or electrons trapped in the channel region 14a in the semiconductor layer 14 is suppressed. In order to do so, the back gate region 28 may be formed in a part of the source region 14b of the semiconductor layer 14 and holes or electrons trapped in the channel layer 14a may be extracted to the outside of the channel layer 14a.

However, since the back gate region 28 needs to be formed continuously with the channel region 14a,
As shown in FIG. 4, the source region 14b is reduced to narrow the channel width of the NMOS transistor to sacrifice the characteristics of the device, or the same channel width is secured to enlarge the device region and sacrifice high integration. There was a problem of not having.

It is an object of the present invention to provide a semiconductor device capable of preventing the occurrence of the substrate bias effect and achieving high integration of elements.

[0007]

The above object is to provide a supporting substrate, an oxide film formed on the supporting substrate, a semiconductor layer formed on the oxide film, and a channel formed in the semiconductor layer. Region, a source region and a drain region formed in the semiconductor layer with the channel region sandwiched therebetween, a gate oxide film formed on the channel region of the semiconductor layer, and the gate oxide film. In a semiconductor device having a gate electrode formed above, the oxide film under a channel region of the semiconductor layer is thinned to be a tunnel oxide film.

[0008]

According to the present invention, the oxide film below the channel region of the semiconductor layer is thinned to form a tunnel oxide film, so that holes or electrons trapped in the channel region are transferred to the supporting substrate through the tunnel oxide film. Since it is pulled out, it is possible to suppress the substrate bias effect without providing the back gate region and expanding the element region.

[0009]

EXAMPLE A semiconductor device according to an example of the present invention will be described with reference to FIG. An oxide film 12 having a film thickness of about 1 μm is formed on the support substrate 10, and a film thickness of 2 μm is formed on the oxide film 12.
The p-type semiconductor layer 14 of m is formed, and the SOI
Make up the structure. The semiconductor layer 14 is an element isolation layer 20.
Defines the element region. A p-type channel region 14a is formed at the center of the element region in the semiconductor layer 14, and an n-type source region 14b and a drain region 14c are formed opposite to each other with the channel region 14a interposed therebetween. .. A gate electrode 18 is formed on the channel region 14a via a gate oxide film 16 having a film thickness of 20 to 50 nm.

A portion of the semiconductor layer 14 below the channel region 14a constitutes a tunnel oxide film 13 having a thickness of 10 nm while the thickness of other portions is 1 μm. The holes trapped in the channel region 14a in the semiconductor layer 14 are extracted from the tunnel oxide film 13 to the supporting substrate 10 by the tunnel effect. As described above, according to this embodiment, the holes trapped in the channel region 14a can be extracted to the supporting substrate 10 through the tunnel oxide film 13 directly below, so that the element region can be expanded and the device can be highly integrated. It is possible to prevent the occurrence of the substrate bias effect without interfering with the above.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. First, the oxide film 12 having a film thickness of about 1 μm is formed on the element substrate 22 (FIG. 2A). Next, a resist 24 is applied on the oxide film 12, and the resist 24 is patterned so that a portion where a tunnel oxide film is to be formed is opened (FIG. 2B). Next, using the resist 24 as a mask, the portion of the oxide film 12 where the tunnel oxide film is to be formed is removed by etching to remove the element substrate 2.
2 The surface is exposed (FIG. 2 (c)). Next, resist 2
4 is removed, and then a film thickness of 1 is formed on the exposed element substrate 22.
A tunnel oxide film 13 of 0 nm is formed by thermal oxidation (FIG. 2 (d)).

Next, a polysilicon layer 26 whose surface is flattened is formed on the entire surface (FIG. 3A). Next, the polysilicon layer 26 is buried only in the opened portion, and the polysilicon layer 26 is lapped until the surrounding oxide film 12 is exposed (FIG. 3B). Next, a silicon support substrate 10 is formed on the surface flattened by lapping.
(Fig. 3 (c)). Next, the semiconductor substrate 14 is formed by lapping the element substrate 22 until the film thickness becomes the same as the desired S / D, and the SOI substrate is completed (FIG. 3).
(D)).

Next, an NMOS transistor is formed on the semiconductor layer 14. First, the element isolation layer 2 is formed on the semiconductor layer 14.
A 0 is formed to define the element region. Next, the semiconductor layer 14
A gate oxide film 16 is formed on the gate oxide film 16, and a gate electrode 18 is formed on the gate oxide film 16. Impurity ions are implanted into the semiconductor layer 14 using the gate electrode 18 as a mask to form a source region 14b and a drain region 14c (FIG. 3).
(E)).

The present invention is not limited to the above embodiment, but various modifications are possible. In the above embodiment, the semiconductor element is an NMOS
Although it is a transistor, it is not limited to an NMOS transistor and may be a PMOS transistor. However, in the case of a PMOS transistor, the electrons trapped in the channel region are extracted from the tunnel oxide film.

[0015]

As described above, according to the present invention, by thinning the oxide film below the channel region of the semiconductor layer to form a tunnel oxide film, holes or electrons trapped in the channel region are tunnel oxide film. Since it is pulled out to the support substrate through the substrate, the substrate bias effect can be suppressed without increasing the element region by the back gate region, and the device can be highly integrated.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process diagram (1) showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a process diagram (2) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a diagram showing a semiconductor device according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Support substrate 12 ... Oxide film 13 ... Tunnel oxide film 14 ... Semiconductor layer 14a ... Channel region 14b ... Source region 14c ... Drain region 16 ... Gate oxide film 18 ... Gate electrode 20 ... Element isolation layer 22 ... Element substrate 24 ... Resist 26 ... Polysilicon layer 28 ... Back gate region

Claims (1)

[Claims] 1. A support substrate, an oxide film formed on the support substrate, a semiconductor layer formed on the oxide film, a channel region formed in the semiconductor layer, and a semiconductor layer formed in the semiconductor layer. A source region and a drain region formed so as to sandwich the channel region, a gate oxide film formed on the channel region of the semiconductor layer, and a gate electrode formed on the gate oxide film. A semiconductor device having: a tunnel oxide film, wherein the oxide film below the channel region of the semiconductor layer is thinned to be a tunnel oxide film.