JP3096831B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, a thin film S.
The present invention relates to a method for isolating a MOS integrated circuit on an OI substrate.

[0002]

2. Description of the Related Art Conventionally, a LOCOS method in which a silicon single crystal thin film device formation layer is oxidized and a method of etching and removing a silicon single crystal thin film device formation layer are known for element isolation of a MOS type integrated circuit on an SOI substrate. Had been.

[0003]

As shown in FIG. 3, a conventional method for isolating elements between MOS transistors of a MOS integrated circuit on an SOI substrate involves oxidizing a silicon single crystal thin film device forming layer to form a field. A LOCOS method in which an oxide film is formed to perform element isolation, and a method of etching and removing a silicon single crystal thin film device formation layer (not shown) have been used.

However, the above-described LOCOS method and the method of etching and removing a silicon single crystal thin film device forming layer involve complicated manufacturing steps and the width of the element isolation region cannot be accurately controlled at the submicron level.
There is a problem that the area occupied by the C chip becomes large, which becomes an obstacle to downsizing the whole IC chip.

An object of the present invention is to provide a semiconductor device having an element isolation method capable of reducing the element isolation width as compared with the conventional method by a simple manufacturing method which solves the above problem.

[0006]

The main means adopted by the semiconductor device of the present invention to achieve the above object is that, in a MOS integrated circuit on an SOI substrate, the element isolation between adjacent MOS transistors is thin. MO on silicon oxide film
By arranging the source region and the drain region of the S-type transistor and the polycrystalline silicon containing the impurity of the reverse conductivity type with a high concentration, the work function between the silicon single crystal thin film device forming layer and the polycrystalline silicon containing the impurity is formed. It is characterized in that electrical isolation is performed by utilizing the difference.

[0007]

According to the semiconductor device of the present invention, a MOS on an SOI substrate is provided.
In the type integrated circuit, element isolation between adjacent MOS transistors is performed by disposing polycrystalline silicon containing a high concentration impurity of a reverse conductivity type with a source region and a drain region of the MOS transistor on a thin silicon oxide film. Performed by

[0008] Due to the work function difference between the silicon single crystal thin film device forming layer and the polycrystalline silicon containing a high concentration of impurities, the source region and the drain region of the MOS transistor contain a high concentration of impurities of the reverse conduction type. In the silicon single crystal thin film device forming layer in the element isolation region on the lower surface of the polycrystalline silicon, it is extremely difficult to form an inversion layer as compared with the channel region of the adjacent MOS transistor, and wiring and the like are formed on the element isolation region. Even when various potentials are applied, electrical isolation between adjacent MOS transistors can be maintained. Further, the element isolation width can be reduced with better controllability as compared with the conventional method.

[0009]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a schematic sectional view showing one embodiment of the semiconductor device of the present invention. N channel M on SOI substrate
The case where an OS transistor is formed is described.

A silicon single crystal thin film device forming layer 102 is formed on a silicon single crystal substrate 101 via a buried insulating film 112. In the silicon single crystal thin film device formation layer 102, two adjacent N-channel MOS
Type transistors 201 and 202 are formed,
Source region 104, 106 and drain region 10 respectively
5 and 107, and a gate electrode 301 containing an N-type impurity made of polycrystalline silicon on the gate oxide film 103.

On the gate oxide film 103 between two adjacent N-channel MOS transistors 201 and 202, a polycrystalline silicon layer 302 containing a high concentration of P-type impurities is formed. Here, the silicon single-crystal thin-film device forming layer 102 existing below the polycrystalline silicon layer 302 containing the P-type impurity at a high concentration via the gate oxide film 103 is originally formed by the N-channel MOS transistors 201 and 202. Although a P-type impurity having the same concentration as that of the channel region is included, a polycrystalline silicon layer 302 containing a P-type impurity having a high concentration via the gate oxide film 103 is disposed above, Specifically, this is equivalent to a state where the P-type impurity concentration is increased.

This will be described with reference to FIGS. 4 (a) and 4 (b). FIGS. 4A and 4B are schematic diagrams of energy bands in the vertical direction of the element isolation region 401 in FIG. FIG. 4A shows a polycrystalline silicon layer 302 still containing P-type impurities on the gate oxide film 103.
Shows an energy band in a state where is not formed.

[0013] Silicon single crystal thin film device forming layer 102
The inside is a low-concentration P-type semiconductor having a certain impurity concentration. Here, as shown in FIG. 1, when the polycrystalline silicon layer 302 containing the P-type impurity at a high concentration is arranged via the gate oxide film 103, as shown in FIG. The energy band in the silicon single crystal thin film device forming layer 102 is pushed up and becomes substantially equal to a state in which the P-type impurity concentration is increased.

As a result, an inversion layer is not easily formed in the silicon single crystal thin film device forming layer 102 in the element isolation region 401, and two adjacent N shown in FIG.
It becomes possible to electrically isolate the channel MOS transistors 201 and 202 from each other.

FIG. 2 shows a P-channel MO on an SOI substrate.
FIG. 3 is a schematic cross-sectional view showing one embodiment of the semiconductor device of the present invention when an S-type transistor is formed. The difference from the example in which the N-channel MOS type transistor is formed on the SOI substrate shown in FIG. 1 is that two adjacent P-channel MOS type transistors 203 and 204 are formed in the silicon single crystal thin film device forming layer 102.
Are formed, each having source regions 104 and 106 and drain regions 105 and 107, and a gate oxide film 10
3 has a gate electrode 303 containing a P-type impurity made of polycrystalline silicon, and a gate oxide film 103 between two adjacent P-channel MOS transistors 203 and 204 has a high concentration. The point is that a polycrystalline silicon layer 304 containing N-type impurities is formed.
About the other point, the same code | symbol as FIG. 1 is described and it replaces with description.

In the case of the P-channel MOS transistor shown in FIG. 2, although not shown, the energy band in the silicon single crystal thin film device forming layer 102 in the element isolation region 401 is depressed, and is substantially N-type. This is equivalent to a state where the impurity concentration is high.

As a result, an inversion layer is not easily formed in the silicon single crystal thin film device forming layer 102 in the element isolation region 401, and two adjacent P shown in FIG.
Electrical isolation of the channel MOS transistors 203 and 204 becomes possible.

When a CMOS integrated circuit is formed in the silicon single crystal thin film device forming layer 102, N
The gate electrodes of the channel MOS transistor and the P channel MOS transistor can be used as polycrystalline silicon having a high impurity concentration for element isolation of a transistor of the opposite conductivity type.

1 and 2, the gate electrode 301 containing an N-type impurity in FIG. 1 is the same as the polycrystalline silicon layer 304 containing a high concentration of N-type impurity in FIG. The polycrystalline silicon layer 302 containing a high concentration of P-type impurities in FIG. 1 and the gate electrode 303 containing P-type impurities in FIG. 2 may be formed of the same material.

[0020]

As described above, according to the present invention, the SOI
In a MOS integrated circuit on a substrate, element isolation between adjacent MOS transistors is performed on a thin silicon oxide film.
This is performed by arranging polycrystalline silicon containing a high impurity concentration of a reverse conductivity type with the source region and the drain region of the OS transistor.

Due to the work function difference between the silicon single crystal thin film device forming layer and the polycrystalline silicon containing the high concentration impurity, the source region and the drain region of the MOS transistor contained the reverse conduction type high concentration impurity. In the silicon single crystal thin film device formation layer in the element isolation region on the lower surface of the polycrystalline silicon, it is extremely difficult to form an inversion layer as compared with the channel region of an adjacent MOS transistor, and wiring and the like are formed on the element isolation region. Even when various potentials are applied, it is possible to maintain the electrical isolation between adjacent MOS transistors.

Further, the manufacturing process can be simplified as compared with the conventional LOCOS method or the element isolation method by etching and removing the silicon single crystal thin film device forming layer, and the element isolation width is smaller than the conventional method with better controllability. , An integrated circuit having a submicron level element isolation width can be formed, and the entire IC chip can be reduced in size.
Can be produced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing one embodiment of a semiconductor device of the present invention.

FIG. 2 is a schematic sectional view showing another embodiment of the semiconductor device of the present invention.

FIG. 3 is a schematic cross-sectional view of a conventional semiconductor device.

FIGS. 4A and 4B are schematic diagrams of energy bands in a vertical direction of an element isolation region according to one embodiment of the semiconductor device of the present invention shown in FIG.

[Explanation of symbols]

Reference Signs List 101 silicon single crystal substrate 102 silicon single crystal thin film device forming layer 103 gate oxide film 104 source region 105 drain region 106 source region 107 drain region 112 buried insulating film 201 n-channel transistor 202 n-channel transistor 203 p-channel transistor 204 p-channel transistor 301 Gate electrode containing N-type impurity 302 Polycrystalline silicon layer containing P-type impurity with high concentration 303 Gate electrode containing P-type impurity 304 Polycrystalline silicon layer containing N-type impurity with high concentration 401 Element isolation region 501 Field oxide film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/76 H01L 27/08 331 H01L 27/12

Claims (2)

(57) [Claims] 1. A MOS-type integrated circuit on SOI substrate Tona
In the semiconductor device, the gate electrode of the MOS transistor is made of polycrystalline silicon containing impurities of the same conductivity type as the source region and the drain region of the MOS transistor.
And one of the MOS transistors of the adjacent MOS transistor.
The source region of the transistor and the gate of the other MOS transistor
A silicon single crystal thin film between the rain regions , and a silicon oxide film on the silicon single crystal thin film;
Polycrystalline silicon layer containing high reverse conductivity type impurities
Semiconductor device. 2. The semiconductor device according to claim 1, wherein said silicon oxide film is formed of said MOS type transistor.
2. The semiconductor device according to claim 1, which is a gate oxide film of a transistor.
Place.