JPH0778881A - Semiconductor device - Google Patents

Abstract

PURPOSE:To set a potential in a first conductivity type well in a potential different from a substrate potential by a method wherein the same conductivity type channel is formed in the substrate of the MOSFET on one side of MOSFETs of a CMOS structure, a second conductivity type well is formed in the surface layer of a first conductivity type substrate and this first conductivity type well is formed in the surface layer of the second conductivity type well. CONSTITUTION:In an N-channel MOSFET 40 on one side of MOSFETs of a logic circuit part CMOS 10, an N-type well 3 is formed in the surface layer of a P-type substrate 1 and a P-type well 4 is formed in the surface layer of the well 3. An N-type impurity-doped gate electrode 43 consisting of a polycrystalline silicon film is provided on the surface of the well 4 via a gate oxide film 71. An N<+> region 41, which is used as a source, and an N<+> region 42, which is used as a drain, are formed. Thereby, a potential in the well 3, which is a first conductivity type, can be set at an arbitrary value different from that of a substrate potential, is made equipotential with a source potential and can avoid a back gate bias.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is particularly applicable to liquid crystal displays.
The present invention relates to a semiconductor device used for a driving integrated circuit (hereinafter abbreviated as LCD).

[0002]

2. Description of the Related Art Some ICs, such as LCD driving ICs, having a level shift circuit that receives a logic circuit signal and converts it into a high-level logic amplitude are shown in FIGS. 2 (a) and 2 (b). 20V and 15V logic part signals of + side respectively
Some have level shift to 40V and 0V on one side. Figure 3
Shows a logic circuit section CMOS10 and a high voltage drive circuit section CMOS20 on a semiconductor substrate of an IC in which such a logic circuit section and a high voltage drive circuit section are integrated. In the figure, the logic part CMOS10 includes an N well 3 formed in a surface layer of a P-type silicon substrate 1, P ⁺ source / drain layers 31 and 32 formed in the surface layer, and a gate oxide film on the surface between them.
P-channel MOSFET 30 having a gate electrode 33 formed via 71, P well 4 formed in the surface layer of P substrate 1 and N ⁺ source formed in the surface layer.
N-channel M having drain layers 41, 42 and a gate electrode 43 formed on the surface between them by a gate oxide film 71
It consists of OSFET40. High voltage drive circuit CMOS20
Is a P channel M formed similarly using the N well 5.
It comprises an OSFET 50 and an N-channel MOSFET 60 formed in a P well 6 of the same conductivity type of the P substrate 1. However, for higher breakdown voltage, the P ⁺ source / drain layers 51 and 52 of the MOSFET 50 are surrounded by the P offset layer 54,
The N ⁺ source / drain layers 61 and 62 of the MOSFET 60 are surrounded by an N offset layer 64, and an N ⁺ guard ring 55 and a P ⁺ guard ring 65 are provided around each offset layer 54 and 64. The surface of the substrate 1 is covered with a field oxide film 72 except for the gate oxide film 71. In addition, although not shown, contact holes to each source / drain layer, wiring, and a surface protection film are formed.

To manufacture such an IC, a P-type (100) silicon substrate 1 having a resistivity of about 10 Ω · cm by the CZ method is used.
N wells 3 and 5 and P wells 4 and 6 are formed in the surface layers of the above, and P offset diffusion layers 54 and N offset diffusion layers 64 are formed in the surface layers of the N wells 5 and 6, respectively. Then, for each MOSFET, a field oxide film 72, a gate oxide film 71 and gate electrodes 43, 5
3, 63, 73 are formed, and the gate electrode thereof is used as a mask to form an N ⁺ source
P ⁺ source / drain layers 41, 42, 61, 62 are formed for the drain layers 31, 32, 51, 52 and the N-channel MOSFET. After that, a contact hole forming step, a wiring forming step, and a protective film forming step are completed.

[0004]

As shown in FIG. 2, this IC is for level-shifting a signal having an amplitude of 15 to 20 V from a logic circuit section to an amplitude of a high voltage driving circuit section 0 to 40 V. . In that case, the potential of each part is 0V for the P substrate grounded, that is, 0V for the P wells 4 and 6, and the
20V, of the P ⁺ source / drain regions 31, 32, the source is 20V, the drain is 15 to 20V, and of the N ⁺ source / drain regions 41, 42, the source is 15V, the drain is 15 to 20V,
Gate electrodes 33 and 43 are 15 to 20V, N well 5 is 40V, P ⁺
Of the source / drain regions 51 and 52, the source is 40 V, the drain is 0 to 40 V, and of the N ⁺ source / drain regions 61 and 62, the source is 0 V, the drain is 0 to 40 V, and the gate electrode
53 and 63 are 0 to 40V. That is, the N-channel MOSFET 40 in the logic circuit section has a source potential of 15V, but has a P-well potential of 0V, and is used in a state in which a back gate voltage is applied. Furthermore, this M
Since a voltage of 15 to 20 V is applied between each of the gate, source and drain electrodes of the OSFET and the P-well 4, in order to suppress the electric field applied to the gate oxide film 71 to the normal level of about 4 MV / cm or less, gate oxidation is required. The film 71 cannot be made thinner than about 250 Å, and it is necessary to take measures to secure the withstand voltage between the source and drain.
It has become difficult to meet the demand for miniaturization accompanying the increase in operating speed and the reduction in chip size for CD driving ICs and the like.

An object of the present invention is to solve the above problems and to provide a semiconductor device which enables fine processing and high speed operation.

[0006]

In order to achieve the above object, the present invention provides a CM on the surface of a first conductivity type semiconductor substrate.
In a semiconductor device in which an OS structure is integrated and a potential different from the substrate potential is applied to the gate, source, and drain of each MOSFET during operation, a second conductivity type well is formed in the surface layer of the semiconductor substrate, and a well of the second conductivity type is formed between the wells. The source / drain region of the first conductivity type in which the one conductivity type channel is formed is in the surface layer of the second conductivity type well, and the source / drain region of the second conductivity type in which the second conductivity type channel is formed is , Provided on the surface layer of the first conductivity type well formed on the surface layer of the second conductivity type well. Low-voltage drive CMO to which a potential different from the gate, source, and drain substrate potentials of each MOSFET is applied
High-voltage-driven CMOS on an S-structure integrated semiconductor substrate
It is effective that the structures are integrated. It is conceivable that the low voltage drive CMOS structure of such a semiconductor device is an element of the logic circuit section and the high voltage drive CMOS structure is an element of the high voltage drive circuit section. In that case, low voltage drive C
The first conductivity type well of the MOS structure has the same surface impurity concentration and the same depth as the first conductivity type offset layer surrounding the first conductivity type source / drain region in which the first conductivity type channel is formed between the wells of the high voltage driving CMOS structure. It is a good way to have

[0007]

[Operation] Each MOSFET gate and source during operation
A channel of the same conductivity type as the substrate of one MOSFET of the CMOS structure in which a potential having a value different from the potential of the semiconductor substrate is applied to the drain is formed in the well of the second conductivity type formed in the surface layer of the substrate of the first conductivity type. Further, by forming the well of the first conductivity type formed on the surface layer, the potential of the well of the first conductivity type can be set to a potential different from that of the substrate. Bias can be avoided. Therefore, the thickness of the gate oxide film can be reduced, which enables high-speed operation and fine processing.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. 1 in which parts common to those in FIG.
In the figure, a CMOS 10 driven as a logic circuit with a voltage amplitude of 15 to 20 V is provided on the surface of a P-type silicon substrate 1.
And an LCD drive IC composed of a high voltage drive circuit CMOS20 driven by a voltage amplitude of 0 to 40V. The CMOS 10 is composed of a P channel MOSFET 30 and an N channel MOSFET 40, and the CMOS 20 is a high voltage P channel MOSFET 50 and a high voltage N channel MO.
It is composed of SFET60.

N-channel MOSFET for logic circuit section
40 is a thickness of 25 on the surface of the P well 4 formed on the surface layer of the N well 3 formed on the surface layer of the P substrate 1.
It has a gate electrode 43 made of polycrystalline silicon doped with N-type impurities, provided through a 0 Å gate oxide film 71, an N ⁺ region 41 used as a source, and an N ⁺ region 42 used as a drain. . The P-channel MOSFET 30 for the logic circuit part has a thickness of 250 on the surface of the N well 3.
It has a gate electrode 33 made of polycrystalline silicon doped with N-type impurities, provided with a gate oxide film 71 of Å, a P ⁺ region 31 used as a source, and a P ⁺ region 32 used as a drain.

N-channel MOSFE for high voltage drive circuit
T60 has a thickness on the surface of P well 6 of the same conductivity type as substrate 1.
A gate electrode 63 made of polycrystalline silicon similar to the above, provided via a 1500 Å gate oxide film 73, and two N-type offset layers 64 formed on the surface layer of the P well 6,
Each surface layer further has an N ⁺ region 61 used as a source and an N ⁺ region 62 used as a drain. P-channel MOS for high voltage drive circuit
The FET 50 is an N well 5 formed on the surface layer of the P substrate 1.
A gate electrode 53 made of polycrystalline silicon similar to the above, which is provided on the surface of the gate electrode through a gate oxide film 73 having a thickness of about 1500Å, and two P-type offset layers 54 formed on the surface layer of the N well. And a P ⁺ region 51 used as a source and a P ⁺ region 52 used as a drain, which are further formed on the respective surface layers. Thus, in the logic circuit section 10, the thickness of the gate oxide film 71 is 250 Å,
The logic circuit section is operating at high speed and is downsized. On the other hand, in the high voltage drive circuit unit 20, the twin gate oxide film structure in which the thickness of the gate oxide film 73 is 1500Å is
The OSFETs 50 and 60 have a high breakdown voltage. N ⁺ guard ring 55 and P ⁺ guard ring 6 for higher breakdown voltage.
5 is provided as in the case of FIG. 3, and the thick field oxide film 72 is provided except for the gate oxide films 71 and 73.
Covering with is also the same as in the case of FIG.

Such an IC was manufactured as follows. The substrate 1 has a resistivity of 10 Ω · cm (100) by the CZ method.
Using a silicon wafer, N-type impurities were introduced and diffused from one surface thereof to form N wells 3 and 5 having a depth of about 5 μm. Next, a P-type impurity is introduced and diffused, and the N well 3
P well 4 and N well 5 with a depth of about 1.5 μm on the surface layer of
P-type offset layer 54, N having a depth of about 1.5 μm on the surface layer of
P wells 6 each having a depth of about 2 μm were formed in the surface layer of the P substrate 1 at the portion of the channel MOSFET 60. The surface impurity concentration of the P well 4 and the offset layer 54 is 2.0 to 8.0 ×
Since it can be the same in the range of 10 ¹⁶ / cm ^-3 , they can be formed at the same time. An N-type offset layer 64 was formed in the surface layer of the P-well 6 to a depth of about 1.5 μm by introducing and diffusing N-type impurities. Furthermore, an N ⁺ guard ring is formed on the surface layer of the N well 5.
55. After forming the P ⁺ guard ring 65 on the surface layer of the P well 6, the field oxide film 72 is selectively formed using the silicon nitride film as a mask. After this, the field oxide film
The oxide film covering the part where 72 is not formed is removed,
Wet oxidation was performed at about 900 ° C. for 70 minutes to form a gate oxide film 73 of about 1500 Å. In addition, about 4500Å by the CVD method
After depositing a polycrystalline silicon layer with a thickness of about 100 ° C and annealing it in an inert gas atmosphere at a temperature of about 900 ° C, patterning is performed by dry etching and the high voltage drive circuit CMOS20.
P-channel MOSFET 50, N-channel MOSFET
The polycrystalline silicon layer was left in the portions of the gate electrodes 60 and 60 that were to become the gate electrodes 53 and 63. Then, using the polycrystalline silicon layer as a mask, the P channel MOSFET of the logic circuit CMOS is formed.
After removing the gate oxide film in the regions of 30 and N-channel MOSFET 40, wet oxidation was performed at a temperature of about 80 ° C. for about 40 minutes to form a gate oxide film 71 having a thickness of 250 Å. A polycrystalline silicon layer having a thickness of 4500 Å was formed thereon by a CVD method, and annealed and then patterned by dry etching to leave the polycrystalline silicon layer in the portions to be the gate electrodes 33 and 43. The remaining polycrystalline silicon layer is
Gate electrodes 53, 63, 33, and 43 were formed by doping phosphorus and making them conductive.

M of the logic circuit section CMOS10 and the high voltage drive circuit section CMOS20 during circuit operation of this semiconductor device
Well portions and sources of the OSFETs 30, 40, 50, 60,
Table 1 shows the potentials of the gate and drain terminals.

[0013]

[Table 1] As can be seen from this table, each MOSFET has the same well potential and source potential, and no back gate bias is applied. In the logic circuit CMOS, the maximum voltage between the terminals is 5 V, the gate oxide film can be formed thin, the device size of the logic circuit CMOS can be reduced, and high-speed operation is facilitated.

[0014]

According to the present invention, CMOS MOSFE is used.
In T, in which a channel having a conductivity type different from that of the semiconductor substrate is formed, the source / drain regions are not formed in the surface layer of the substrate, and the substrate is further formed in the surface layer of the well of a conductivity type different from the substrate. By forming in the well of the same conductivity type, the potential of the well can be set to an arbitrary value different from the substrate potential to be grounded, for example, and the potential can be made equal to the source potential to avoid back gate bias. . As a result, since the gate oxide film can be made thin, high-speed operation and device miniaturization are possible. When the high breakdown voltage CMOS is integrated on the same semiconductor substrate, such a double well structure can be formed in the same step as that of the offset layer, so that no additional step is required.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a semiconductor device for driving an LCD according to an embodiment of the present invention.

2A and 2B are diagrams for explaining a level shift signal during operation of the semiconductor device of FIG. 1, where FIG. 2A is a level diagram and FIG. 2B is a signal waveform diagram.

FIG. 3 is a sectional view of a main part of a conventional LCD driving semiconductor device.

[Explanation of symbols]

 1 P-type silicon substrate 10 Logic circuit section CMOS 20 High voltage drive circuit section CMOS 30, 50 P-channel MOSFET 40, 60 N-channel MOSFET 3, 5 N-well 4, 6 P-well 31, 41, 51, 61 Source region 32, 42, 52, 62 Drain region 33, 43, 53, 63 Gate electrode 54, 64 Offset layer 71, 73 Gate oxide film

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (4)

[Claims] 1. A CMOS is provided on the surface of a first conductivity type semiconductor substrate.
In a structure in which a potential different from the substrate potential is applied to the gate, source and drain of each MOSFET during operation, a second conductivity type well is formed in the surface layer of the semiconductor substrate, and the first conductivity type well is formed between them. The source / drain region of the first conductivity type in which the channel of the second conductivity type is formed is in the surface layer of the well of the second conductivity type, and the source / drain region of the second conductivity type in which the channel of the second conductivity type is formed is the first layer. A semiconductor device provided on a surface layer of a first conductivity type well formed on a surface layer of a second conductivity type well. 2. The high voltage drive CMOS structure is integrated on a semiconductor substrate on which a low voltage drive CMOS structure to which a potential different from the gate, source and drain substrate potentials of each MOSFET is applied. Semiconductor device. 3. The semiconductor device according to claim 2, wherein the low voltage drive CMOS structure is an element of the logic circuit section, and the high voltage drive CMOS structure is an element of the high voltage drive circuit section. 4. A first conductivity type offset layer surrounding a first conductivity type source / drain region in which a first conductivity type well of a low voltage driving CMOS structure forms a first conductivity type channel between them in a high voltage driving CMOS structure. 4. The semiconductor device according to claim 2, which has the same surface impurity concentration and the same depth as the above.