JPH0574854A - Semiconductor-element mounting method - Google Patents
Semiconductor-element mounting methodInfo
- Publication number
- JPH0574854A JPH0574854A JP23192491A JP23192491A JPH0574854A JP H0574854 A JPH0574854 A JP H0574854A JP 23192491 A JP23192491 A JP 23192491A JP 23192491 A JP23192491 A JP 23192491A JP H0574854 A JPH0574854 A JP H0574854A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- board
- electrode
- electrode pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子を基板に実
装する半導体素子実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting method for mounting a semiconductor element on a substrate.
【０００２】[0002]
【従来の技術】半導体素子を基板に実装するための従来
の半導体素子実装方法には、半導体素子に設けられてい
る電極と、基板に設けられている電極とを対向させ密着
させて接合し、電気的に接続するフェースダウン方式の
実装方法がある。2. Description of the Related Art In a conventional semiconductor element mounting method for mounting a semiconductor element on a substrate, an electrode provided on the semiconductor element and an electrode provided on the substrate are made to face each other and closely adhered to each other. There is a face-down type mounting method for electrically connecting.
【０００３】図３は従来のフェースダウン方式の半導体
素子実装方法により形成された半導体装置の断面図であ
る。FIG. 3 is a sectional view of a semiconductor device formed by a conventional face-down type semiconductor element mounting method.
【０００４】同図に示すように、従来の半導体素子実装
方法により形成された半導体装置は、基板11上に半導体
素子12をフェースダウンの状態で直接実装することによ
り形成されている。As shown in FIG. 1, a semiconductor device formed by a conventional semiconductor element mounting method is formed by directly mounting a semiconductor element 12 on a substrate 11 in a face-down state.
【０００５】即ち、同図の半導体素子12のエッジ部Ａを
拡大した図に示すように、基板11上に接続電極引き出し
用の配線パターン16に接続されている電極用配線13を形
成し、電極用配線13にメッキ若しくは半田等によりバン
プを配置して突起電極14を形成する。That is, as shown in an enlarged view of the edge portion A of the semiconductor element 12 in the same figure, the electrode wiring 13 connected to the wiring pattern 16 for drawing out the connection electrode is formed on the substrate 11, and the electrode wiring 13 is formed. Bumps are arranged on the wiring 13 for plating by soldering or the like to form the protruding electrodes 14.
【０００６】一方で、半導体素子12に突起電極15を形成
する。そして、基板11上に形成された突起電極14と、半
導体素子12に形成された突起電極15とをマイクロ半田接
合して電気的に接続することにより、この半導体装置は
形成されている。On the other hand, the protruding electrode 15 is formed on the semiconductor element 12. Then, the bump electrode 14 formed on the substrate 11 and the bump electrode 15 formed on the semiconductor element 12 are micro-soldered and electrically connected to each other to form the semiconductor device.
【０００７】尚、基板11上に突起電極14を形成せずに、
電極用配線13上に親和性を有しない材料から成る接続用
材料18を塗布して電極用配線13の部分（図３の拡大図に
おいて突起電極14が形成されている部分）に開口を形成
し、半田接続を行う場合もある。しかしながら、異方性
接着剤17を用いて接続を行う場合には一般に、突起電極
14及び突起電極15を基板11上及び半導体素子12上にそれ
ぞれ設けた方が、信頼性の高い接続をより確実に行うた
めに有利である。In addition, without forming the protruding electrode 14 on the substrate 11,
A connection material 18 made of a material having no affinity is applied on the electrode wiring 13 to form an opening in a portion of the electrode wiring 13 (a portion where the protruding electrode 14 is formed in the enlarged view of FIG. 3). In some cases, solder connection is performed. However, when the connection is made using the anisotropic adhesive 17, the protruding electrode is generally used.
Providing the bump 14 and the bump electrode 15 on the substrate 11 and the semiconductor element 12, respectively, is advantageous for more reliable connection.
【０００８】[0008]
【発明が解決しようとする課題】このような従来の半導
体素子実装方法では、基板11上に突起電極14を形成する
ために、基板形成工程において精度よくマスク等を重ね
合わせ、複雑な工程を追加しなければならない。そのた
め、基板を形成するためのコストが増大する。In such a conventional semiconductor element mounting method, in order to form the protruding electrodes 14 on the substrate 11, masks and the like are accurately overlapped in the substrate forming step, and complicated steps are added. Must. Therefore, the cost for forming the substrate increases.
【０００９】更に基板の高さの面内バラツキを抑えるた
めには、従来の基板形成工程に比較して複雑で高度な工
程が必要となり、結果的に半導体素子の実装に用いられ
る基板の収率が低下するという問題点がある。Further, in order to suppress the in-plane variation in the height of the substrate, a complicated and sophisticated process is required as compared with the conventional substrate forming process, and as a result, the yield of the substrate used for mounting the semiconductor element is increased. There is a problem in that
【００１０】又、基板11の電極用配線13上に突起電極14
が形成されており、このような基板11に半導体素子12を
実装すると、半導体素子12のエッジ部分Ａにおいて電流
リークの発生が起き易いという問題点がある。In addition, a protruding electrode 14 is formed on the electrode wiring 13 of the substrate 11.
When the semiconductor element 12 is mounted on such a substrate 11, there is a problem that a current leak is likely to occur at the edge portion A of the semiconductor element 12.
【００１１】従って、本発明は、容易に且つ高信頼度で
半導体素子を基板に実装することのできる半導体素子実
装方法を提供するものである。Therefore, the present invention provides a semiconductor element mounting method capable of mounting a semiconductor element on a substrate easily and with high reliability.
【００１２】[0012]
【課題を解決するための手段】基板に設けられている配
線電極と半導体素子に設けられているチップ電極とを接
合して半導体素子を基板に実装する半導体素子実装方法
であって、配線電極を塑性変形させることにより配線電
極に突起部を形成し、突起部とチップ電極とを接合す
る。A semiconductor element mounting method for mounting a semiconductor element on a substrate by bonding a wiring electrode provided on a substrate and a chip electrode provided on a semiconductor element, A protrusion is formed on the wiring electrode by plastic deformation, and the protrusion and the chip electrode are joined.
【００１３】[0013]
【作用】基板に設けられている配線電極を塑性変形させ
ることにより、配線電極に突起部を形成し、突起部と半
導体素子に設けられているチップ電極とを接合して半導
体素子を基板に実装する。このように、配線電極の一部
に突起部が形成されるので、従来のように基板の配線電
極上に更に突起電極を形成する必要がなくなり、従っ
て、半導体素子を基板に容易に且つ高い信頼度で実装す
ることができる。[Function] The wiring electrode provided on the substrate is plastically deformed to form a projection on the wiring electrode, and the projection is joined to the chip electrode provided on the semiconductor element to mount the semiconductor element on the substrate. To do. In this way, since the protrusion is formed on a part of the wiring electrode, it is not necessary to further form the protrusion electrode on the wiring electrode of the substrate as in the conventional case. Therefore, the semiconductor element can be easily and highly reliable on the substrate. Can be implemented in degrees.
【００１４】[0014]
【実施例】以下、図面を参照して本発明の実施例を説明
する。Embodiments of the present invention will be described below with reference to the drawings.
【００１５】図１は本発明に係る半導体素子実装方法の
一実施例において塑性変形により形成された配線電極パ
ターンを説明するための断面図、及び図２は基板上の配
線電極パターンと半導体素子上の突起電極を重ね合わせ
る際の断面図である。FIG. 1 is a sectional view for explaining a wiring electrode pattern formed by plastic deformation in one embodiment of a semiconductor element mounting method according to the present invention, and FIG. 2 is a wiring electrode pattern on a substrate and a semiconductor element. FIG. 7 is a cross-sectional view when the protruding electrodes of FIG.
【００１６】尚、図２の基板上の配線電極パターン26は
模式的に示されており、図１に示されている配線電極パ
ターン26と実質的には同じものである。The wiring electrode pattern 26 on the substrate of FIG. 2 is schematically shown, and is substantially the same as the wiring electrode pattern 26 shown in FIG.
【００１７】これらの図に示すように、この実施例の半
導体素子実装方法では、先ず、配線済みの例えば、ガラ
スエポキシプリント配線板から成る基板21に接続電極引
き出し用の配線電極パターン26を形成した後に金メッキ
等を施して、基板を形成する。As shown in these figures, in the semiconductor element mounting method of this embodiment, first, a wiring electrode pattern 26 for drawing out a connection electrode is formed on a substrate 21 made of, for example, a glass epoxy printed wiring board. After that, gold plating or the like is applied to form a substrate.
【００１８】次いで、図示していないフェースダウンタ
イプの半導体素子実装デバイスに上述のようにして形成
された基板21を載せ、基板21の配線電極パターン26を認
識した後、専用ツールを基板21の配線電極パターン26上
のボンディングポイントに押し当て、パルス的に熱を加
え、加圧することにより配線電極パターン26を塑性変形
させ、配線電極パターン26の一部に突起部28を形成す
る。Next, the substrate 21 formed as described above is placed on a face-down type semiconductor device mounting device (not shown), the wiring electrode pattern 26 of the substrate 21 is recognized, and then a dedicated tool is used for wiring the substrate 21. The wiring electrode pattern 26 is plastically deformed by pressing it against a bonding point on the electrode pattern 26, applying heat in a pulsed manner, and applying pressure to form a protrusion 28 on a part of the wiring electrode pattern 26.
【００１９】次いで、基板21の配線電極パターン26及び
その突起部28が形成された部分に、図示していない異方
性導電性樹脂を接続用材料として塗布し、基板21上の突
起部28と、半導体素子22上に形成された突起電極25とを
重ね合わせてボンディング（接合）し、電気的に接続す
る。Next, an anisotropic conductive resin (not shown) is applied as a connecting material to the portion of the substrate 21 where the wiring electrode pattern 26 and the protruding portion 28 are formed, to form the protruding portion 28 on the substrate 21. , And the bump electrodes 25 formed on the semiconductor element 22 are superposed and bonded (electrically connected).
【００２０】基板21は本発明の基板の一実施例である。
半導体素子22は本発明の半導体素子の一実施例である。
突起電極25は本発明のチップ電極の一実施例である。配
線電極パターン26は本発明の配線電極の一実施例であ
る。突起部28は本発明の突起部の一実施例である。The substrate 21 is an example of the substrate of the present invention.
The semiconductor element 22 is an example of the semiconductor element of the present invention.
The protruding electrode 25 is an example of the chip electrode of the present invention. The wiring electrode pattern 26 is an example of the wiring electrode of the present invention. The protrusion 28 is an example of the protrusion of the present invention.
【００２１】この実施例によれば、半導体素子22を取り
付けるために基板21に設けられた配線電極パターン26を
ボンディング前にプレス（加圧、加熱）することにより
塑性変形させ、配線電極パターン26の引き出し線の一部
に突起部28を形成する。これにより、半導体素子22に設
けられている突起電極25と基板21の突起部28を有する電
極の接続を容易に且つ高い信頼性の下に行うことができ
る。According to this embodiment, the wiring electrode pattern 26 provided on the substrate 21 for mounting the semiconductor element 22 is plastically deformed by pressing (pressurizing, heating) before bonding to form the wiring electrode pattern 26. The protrusion 28 is formed on a part of the lead line. This makes it possible to connect the protruding electrode 25 provided on the semiconductor element 22 and the electrode having the protruding portion 28 of the substrate 21 easily and with high reliability.
【００２２】例えば、基板21上の配線電極パターン26に
突起部28を形成したことにより、この基板21に半導体素
子22を実装すると、半導体素子22のエッジ部分での電流
リークの発生が起きる可能性がなくなり、この実施例の
実装方法により形成された半導体装置の品質及び信頼性
を向上させることができる。しかも実装に用いられる基
板21は従来と同様に形成されたものを利用することがで
きるため、安価に実現させることができる。For example, when the semiconductor element 22 is mounted on the substrate 21 by forming the protrusion 28 on the wiring electrode pattern 26 on the substrate 21, current leakage may occur at the edge portion of the semiconductor element 22. And the quality and reliability of the semiconductor device formed by the mounting method of this embodiment can be improved. Moreover, since the substrate 21 used for mounting can be formed in the same manner as the conventional one, it can be realized at low cost.
【００２３】配線電極パターン26に突起部28を形成する
ための形成方法として、半導体素子22を実装する際に、
半導体素子実装デバイスによってボンディングポイント
を認識しながら、ボンディング直前にプレスユニットを
用いて加圧、加熱し、基板の平滑性及び電極の高さの面
内分布のバラツキを低く抑えながら精度良く基板21上の
配線電極パターン26を塑性変形させ、半導体素子22上に
形成された突起電極25との配線電極パターン26の接続部
分に、所望の突起部28を容易に形成することができる。As a forming method for forming the protrusion 28 on the wiring electrode pattern 26, when the semiconductor element 22 is mounted,
While recognizing the bonding point by the semiconductor device mounting device, pressurizing and heating using the press unit immediately before bonding, and accurately controlling the smoothness of the substrate and the in-plane distribution of the height of the electrode on the substrate 21 with low variations. The wiring electrode pattern 26 can be plastically deformed to easily form a desired protrusion 28 at the connection portion of the wiring electrode pattern 26 with the protrusion electrode 25 formed on the semiconductor element 22.
【００２４】[0024]
【発明の効果】以上説明したように、本発明は、基板に
設けられている配線電極と半導体素子に設けられている
チップ電極とを接合して半導体素子を基板に実装する半
導体素子実装方法であって、配線電極を塑性変形させる
ことにより配線電極に突起部を形成し、突起部とチップ
電極とを接合するので、従って、半導体素子を基板に容
易に且つ高い信頼度で実装することができる。As described above, the present invention is a semiconductor element mounting method for mounting a semiconductor element on a substrate by joining a wiring electrode provided on the substrate and a chip electrode provided on the semiconductor element. Since the protrusion is formed on the wiring electrode by plastically deforming the wiring electrode and the protrusion and the chip electrode are joined, therefore, the semiconductor element can be easily mounted on the substrate with high reliability. .
【図１】本発明に係る半導体素子実装方法の一実施例に
おいて塑性変形により形成された配線電極パターンを説
明するための断面図である。FIG. 1 is a cross-sectional view for explaining a wiring electrode pattern formed by plastic deformation in an embodiment of a semiconductor element mounting method according to the present invention.
【図２】基板上の配線電極パターンと半導体素子上の突
起電極を重ね合わせる際の断面図である。FIG. 2 is a cross-sectional view when a wiring electrode pattern on a substrate and a protruding electrode on a semiconductor element are superposed on each other.
【図３】従来のフェースダウン方式の半導体素子実装方
法により形成された半導体装置の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device formed by a conventional face-down type semiconductor element mounting method.
21 基板 22 半導体素子 25 突起電極 26 配線電極パターン 28 突起部 21 Substrate 22 Semiconductor element 25 Projection electrode 26 Wiring electrode pattern 28 Projection
Claims (1)
素子に設けられているチップ電極とを接合して該半導体
素子を該基板に実装する半導体素子実装方法であって、
前記配線電極を塑性変形させることにより該配線電極に
突起部を形成し、該突起部と前記チップ電極とを接合す
ることを特徴とする半導体素子実装方法。1. A semiconductor element mounting method for mounting a semiconductor element on a substrate by bonding a wiring electrode provided on the substrate to a chip electrode provided on a semiconductor element, the method comprising:
A method for mounting a semiconductor element, comprising: forming a protrusion on the wiring electrode by plastically deforming the wiring electrode, and joining the protrusion and the chip electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23192491A JPH0574854A (en) | 1991-09-11 | 1991-09-11 | Semiconductor-element mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23192491A JPH0574854A (en) | 1991-09-11 | 1991-09-11 | Semiconductor-element mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0574854A true JPH0574854A (en) | 1993-03-26 |
Family
ID=16931199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23192491A Pending JPH0574854A (en) | 1991-09-11 | 1991-09-11 | Semiconductor-element mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0574854A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11202723B2 (en) | 2016-07-01 | 2021-12-21 | The Procter & Gamble Company | Absorbent articles with improved topsheet dryness |
-
1991
- 1991-09-11 JP JP23192491A patent/JPH0574854A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11202723B2 (en) | 2016-07-01 | 2021-12-21 | The Procter & Gamble Company | Absorbent articles with improved topsheet dryness |
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