JPH0574765A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0574765A JPH0574765A JP3232717A JP23271791A JPH0574765A JP H0574765 A JPH0574765 A JP H0574765A JP 3232717 A JP3232717 A JP 3232717A JP 23271791 A JP23271791 A JP 23271791A JP H0574765 A JPH0574765 A JP H0574765A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- aluminum wiring
- aluminum
- aluminum layer
- signal interference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路装置に関
し、特に第１層アルミニウム配線の周囲にシールド用の
Ｐ型ウェルおよび第１層アルミニウム，第２層アルミニ
ウムを設けた内部構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an internal structure in which a P-type well for shielding and a first layer aluminum and a second layer aluminum are provided around a first layer aluminum wiring.
【０００２】[0002]
【従来の技術】第１層アルミニウム配線である被信号１
０のシールドは、図２で示すように、両側に、低電位に
固定されたシールド用第１層アルミニウム配線１１を設
ける構造であった。この構造により、両隣の他の第１層
アルミニウム配線１２との線間容量による他信号の干渉
を防ぐ事ができた。2. Description of the Related Art Signal 1 which is a first layer aluminum wiring
As shown in FIG. 2, the 0 shield had a structure in which the shield first layer aluminum wiring 11 fixed at a low potential was provided on both sides. With this structure, it is possible to prevent other signals from interfering with the other first layer aluminum wirings 12 on both sides due to the line capacitance.
【０００３】[0003]
【発明が解決しようとする課題】この従来の第１層アル
ミニウム配線のシールド方法は、低電位に固定した第１
層アルミニウム配線を両側に設けるだけの構造であった
為、両隣の第１層アルミニウム配線同志の線間容量によ
る信号の干渉は防ぐ事ができるが、第１層アルミニウム
配線の下部の基板より伝わってくる信号の干渉は防ぐ事
ができない。又、第１層アルミニウム配線の上部より飛
び込んでくる信号の干渉も防げない。という問題点があ
った。The conventional method for shielding the first layer aluminum wiring is the first method for fixing the first layer aluminum wiring to a low potential.
Since the structure is such that only the first layer aluminum wiring is provided on both sides, it is possible to prevent signal interference due to the line capacitance between the adjacent first layer aluminum wirings. The interference of incoming signals cannot be prevented. In addition, it is not possible to prevent the interference of signals that jump in from above the first-layer aluminum wiring. There was a problem.
【０００４】本発明の目的は、半導体集積回路上におけ
る第１アルミニウム配線のシールド方法で、隣接する第
１アルミニウム配線との線間容量による信号の干渉だけ
でなく、基板からの信号干渉、第１アルミニウム配線の
上側よりの信号干渉を遮断する構造を提供することにあ
る。It is an object of the present invention to provide a shield method for a first aluminum wiring on a semiconductor integrated circuit, in which not only signal interference due to line capacitance with an adjacent first aluminum wiring but also signal interference from a substrate, It is to provide a structure for blocking signal interference from the upper side of the aluminum wiring.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体集積回路
装置は、第１層アルミニウム配線のシールド法にして、
第１層アルミニウム配線の下部のＮ型基板上にＰ型ウェ
ルを形成する構造とする。さらに、Ｎ側に高電位、Ｐ側
に低電位を与える事により、ＰＮ接合面に逆バイアスを
かけておく。A semiconductor integrated circuit device according to the present invention uses a shield method for a first layer aluminum wiring,
The structure is such that a P-type well is formed on the N-type substrate below the first layer aluminum wiring. Further, a high potential is applied to the N side and a low potential is applied to the P side to reverse bias the PN junction surface.
【０００６】さらに、そのＰ型ウェルと同電位を与えた
第２層アルミニウムで第１層アルミニウム配線の上側を
覆う構造とする。Furthermore, the upper side of the first-layer aluminum wiring is covered with the second-layer aluminum applied with the same potential as that of the P-type well.
【０００７】[0007]
【実施例】次に、本発明について、図面を参照して説明
する。図１は本発明の一実施例の半導体集積回路装置の
平面図およびそのＸ−Ｘ1 断面図並びにＹ−Ｙ1 断面図
である。Next, the present invention will be described with reference to the drawings. Figure 1 is a plan view and a X-X 1 cross-sectional view and Y-Y 1 cross-sectional view of a semiconductor integrated circuit device of one embodiment of the present invention.
【０００８】まず図１（ａ），（ｂ）に示すようにＮ型
シリコン基板９の上にＰ型ウェル５を形成し、Ｐ型拡散
層６を設ける。さらに、酸化膜７を形成しそこにコンタ
クトを開孔し第１層アルミニウム２を設ける。その上に
さらに絶縁膜８を形成し、第２層アルミニウム４を前記
第１層アルミニウム２を覆うように設ける。First, as shown in FIGS. 1A and 1B, a P-type well 5 is formed on an N-type silicon substrate 9, and a P-type diffusion layer 6 is provided. Further, an oxide film 7 is formed, a contact is opened therein, and a first layer aluminum 2 is provided. An insulating film 8 is further formed thereon, and a second layer aluminum 4 is provided so as to cover the first layer aluminum 2.
【０００９】次に図１（ｃ）に示すように、前記第１層
アルミニウム２のうちの左右の２本にスルーホールにて
絶縁膜を開孔し、前記第２層アルミニウム４を接続す
る。Next, as shown in FIG. 1 (c), an insulating film is opened in two left and right of the first layer aluminum 2 by through holes, and the second layer aluminum 4 is connected.
【００１０】なお、図１に示す通り、前記コンタクトと
スルーホールは、交互に配置する様にする。As shown in FIG. 1, the contacts and the through holes are arranged alternately.
【００１１】[0011]
【発明の効果】以上、説明したように本発明は、第１層
アルミニウム配線のシールド用に、下部のＮ型基板にＰ
型ウェルを設けそのウェルを低電位に固定した第１層ア
ルミニウム配線で低電位にし、Ｎ型基板を高電位にし
て、ＰＮ接合面に逆バイアスをかける事によって、基板
より伝わってくる信号の干渉を防ぐ事ができる。As described above, according to the present invention, the lower N-type substrate is provided with a P layer for shielding the first layer aluminum wiring.
Interference of signals transmitted from the substrate by providing a type well and setting the well to a low potential with the first-layer aluminum wiring that fixes the potential to a low potential, setting the N-type substrate to a high potential, and applying a reverse bias to the PN junction surface. Can be prevented.
【００１２】さらに、上側を低電位に固定した第２層ア
ルミニウムで覆うことにより、上側より伝わってくる信
号の干渉を防ぐ事ができる。Further, by covering the upper side with the second layer aluminum fixed at a low potential, it is possible to prevent the interference of the signal transmitted from the upper side.
【図１】本発明の一実施例の平面図およびそのＸ−Ｘ1
断面図並びにＹ−Ｙ1 断面図である。FIG. 1 is a plan view of an embodiment of the present invention and its XX 1
It is a cross-sectional view and Y-Y 1 cross section.
【図２】従来の半導体集積回路装置の一例の断面図であ
る。FIG. 2 is a sectional view of an example of a conventional semiconductor integrated circuit device.
１ スルーホール ２ 第１層アルミニウム配線 ３ コンタクト ４ 第２層アルミニウム配線 ５ Ｐ型ウェル ６ 拡散層 ７，１４ 酸化膜 ８，１５ 絶縁膜 ９，１３ Ｎ型基板 １０ 被信号線（第１層アルミニウム配線） １１ シールド用第１層アルミニウム配線 １２ 他の第１層アルミニウム配線 1 Through Hole 2 First Layer Aluminum Wiring 3 Contact 4 Second Layer Aluminum Wiring 5 P-type Well 6 Diffusion Layer 7,14 Oxide Film 8,15 Insulating Film 9,13 N-type Substrate 10 Signal Line (First Layer Aluminum Wiring) ) 11 shield first layer aluminum wiring 12 other first layer aluminum wiring
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 7342−4Ｍ 27/08 ３１１ Ｂ ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location 7342-4M 27/08 311 B
Claims (2)
アルミニウム配線の下部のＮ型半導体基板上にＰ型ウェ
ルを形成し、前記第１の第１層アルミニウム配線の両側
に、第２および第３の第１層アルミニウム配線を具備
し、前記第１〜第３の第１層アルミニウム配線の上部を
覆う第２アルミニウム配線を具備し、前記第２および第
３の第１層アルミ配線と拡散層を介してＰ型ウェルを接
続するウェルコンタクトと、前記第２および第３の第１
層アルミニウム配線と第２層アルミニウム配線を接続す
るスルーホール孔とを交互に設ける構造を備えることを
特徴とする半導体集積回路装置。1. In a semiconductor integrated circuit, a P-type well is formed on an N-type semiconductor substrate below a first first-layer aluminum wiring, and a P-type well is formed on both sides of the first first-layer aluminum wiring. A third aluminum wiring layer of the first layer, a second aluminum wiring layer covering the upper portions of the first to third aluminum wiring layers of the first to third layers, and a diffusion layer of the second and third aluminum wiring layers of the first layer. A well contact connecting a P-type well via a layer, and the second and third first contacts
A semiconductor integrated circuit device having a structure in which a layer aluminum wiring and a through hole connecting a second layer aluminum wiring are alternately provided.
位とし、ＰＮ接合面に逆バイアスをかけておくことを特
徴とする請求項１記載の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein the N-type substrate is set to a high potential, the P-type well is set to a low potential, and the PN junction surface is reverse-biased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3232717A JPH0574765A (en) | 1991-09-12 | 1991-09-12 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3232717A JPH0574765A (en) | 1991-09-12 | 1991-09-12 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0574765A true JPH0574765A (en) | 1993-03-26 |
Family
ID=16943684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3232717A Pending JPH0574765A (en) | 1991-09-12 | 1991-09-12 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0574765A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0869547A3 (en) * | 1997-03-31 | 1998-10-21 | Nec Corporation | Semiconductor device and manufacture method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6329962A (en) * | 1986-07-23 | 1988-02-08 | Sony Corp | Semiconductor device |
| JPH01125956A (en) * | 1987-11-11 | 1989-05-18 | Mitsubishi Electric Corp | Semiconductor device |
| JPH01290238A (en) * | 1988-05-18 | 1989-11-22 | Matsushita Electron Corp | Semiconductor device |
| JPH02302075A (en) * | 1989-05-16 | 1990-12-14 | Nec Ic Microcomput Syst Ltd | Semiconductor device |
-
1991
- 1991-09-12 JP JP3232717A patent/JPH0574765A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6329962A (en) * | 1986-07-23 | 1988-02-08 | Sony Corp | Semiconductor device |
| JPH01125956A (en) * | 1987-11-11 | 1989-05-18 | Mitsubishi Electric Corp | Semiconductor device |
| JPH01290238A (en) * | 1988-05-18 | 1989-11-22 | Matsushita Electron Corp | Semiconductor device |
| JPH02302075A (en) * | 1989-05-16 | 1990-12-14 | Nec Ic Microcomput Syst Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0869547A3 (en) * | 1997-03-31 | 1998-10-21 | Nec Corporation | Semiconductor device and manufacture method thereof |
| KR100285002B1 (en) * | 1997-03-31 | 2001-07-12 | 가네꼬 히사시 | Semiconductor device and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980224 |