JPH05145021A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPH05145021A
JPH05145021A JP3331132A JP33113291A JPH05145021A JP H05145021 A JPH05145021 A JP H05145021A JP 3331132 A JP3331132 A JP 3331132A JP 33113291 A JP33113291 A JP 33113291A JP H05145021 A JPH05145021 A JP H05145021A
Authority
JP
Japan
Prior art keywords
power supply
analog
supply wiring
digital
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3331132A
Other languages
Japanese (ja)
Inventor
Toshihiko Muramatsu
利彦 村松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Corp
Original Assignee
Yamaha Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Corp filed Critical Yamaha Corp
Priority to JP3331132A priority Critical patent/JPH05145021A/en
Publication of JPH05145021A publication Critical patent/JPH05145021A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To reduce noise which permeates from the power supply wiring of a digital IC part into the power supply wiring of an analog IC part via a semiconductor substrate, in the power supply wiring structure of a digital-analog mixed mounting IC. CONSTITUTION:The non-earth side power supply wiring layer 14A, of an analog IC part is formed on an insulating film 11 covering the surface of a semiconductor substrate 10, via a conducting layer 20 and an insulating film 22. The conducting layer 20 is connected with an earth side power supply terminal 16A2 of the analog IC part. The non-earth side power supply wiring layer 14D1 of a digital IC part is connected with the substrate 10. Digital system operation noise is to permeate into the power supply wiring layer 14A1 of the analog IC part via the substrate 10. However the conducting layer 20 acts as a shield layer, so that permeation noise is reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、ディジタルIC(集
積回路)部及びアナログIC部を共通の半導体基板に形
成したディジタル−アナログ混載型の集積回路装置に関
し、特にアナログIC部の非接地側電源配線を半導体基
板から電気的に分離し且つ電磁的にシールドしたことに
よりディジタルIC部から基板を介してアナログIC部
に混入するノイズを低減したものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-analog mixed type integrated circuit device in which a digital IC (integrated circuit) part and an analog IC part are formed on a common semiconductor substrate, and more particularly to a non-grounded power supply for the analog IC part. By electrically separating the wiring from the semiconductor substrate and electromagnetically shielding it, noise mixed in the analog IC portion from the digital IC portion through the substrate is reduced.

【0002】[0002]

【従来の技術】従来、DA変換器又はAD変換器等のデ
ィジタル−アナログ混載ICとしては、図2に示すよう
なチップ構成のものが提案されている。
2. Description of the Related Art Conventionally, as a digital-analog mixed IC such as a DA converter or an AD converter, a chip structure as shown in FIG. 2 has been proposed.

【0003】図2において、シリコン等の半導体基板1
0の表面にはディジタルIC部12D及びアナログIC
部12Aが形成されている。ディジタルIC部12Dに
は、一対の電源配線層14D1 及び14D2 が設けられ
ると共にこれらの配線層14D1 及び14D2 に接続さ
れた電源端子(ボンディングパッド)16D1 及び16
2 が設けられている。電源端子16D1 及び16D2
は、電源電位VDD及びVSSがそれぞれ付与されるもの
で、この例では電位VSSとして接地電位が与えられる。
なお、配線層14D1 は、図3について後述するのと同
様にして複数の個所で基板10と接続されている。
In FIG. 2, a semiconductor substrate 1 made of silicon or the like is used.
On the surface of 0, digital IC section 12D and analog IC
The portion 12A is formed. The digital IC portion 12D is provided with a pair of power supply wiring layers 14D 1 and 14D 2 and power supply terminals (bonding pads) 16D 1 and 16 connected to these wiring layers 14D 1 and 14D 2.
D 2 is provided. Power supply terminals 16D 1 and 16D 2
Are provided with power supply potentials V DD and V SS , respectively, and in this example, a ground potential is provided as the potential V SS .
The wiring layer 14D 1 is connected to the substrate 10 at a plurality of points in the same manner as described later with reference to FIG.

【0004】アナログIC部12Aにあっては、一対の
電源配線層14A1 及び14A2 が設けられると共にこ
れらの配線層14A1 及び14A2 にそれぞれ接続され
た電源端子(ボンディングパッド)16A1 及び16A
2 が設けられている。電源端子16A1 及び16A2
は、電源電位VDD及びVSSがそれぞれ付与されるもの
で、この例では電位VSSとして接地電位が与えられる。
配線層14A1 は、複数の個所で図3に示すように絶縁
膜11の接続孔を介してN型基板10に接続されてい
る。これは、配線によるインピーダンス増加を抑制する
ためである。
In the analog IC portion 12A, a pair of power supply wiring layers 14A 1 and 14A 2 are provided, and power supply terminals (bonding pads) 16A 1 and 16A connected to these wiring layers 14A 1 and 14A 2 , respectively.
Two are provided. Power supply terminals 16A 1 and 16A 2
Are provided with power supply potentials V DD and V SS , respectively, and in this example, a ground potential is provided as the potential V SS .
The wiring layer 14A 1 is connected to the N-type substrate 10 at a plurality of points through the connection holes of the insulating film 11 as shown in FIG. This is to suppress an increase in impedance due to wiring.

【0005】[0005]

【発明が解決しようとする課題】上記した従来技術によ
ると、ディジタルIC部の非接地側電源配線(14
1,16D1 )とアナログIC部の非接地側電源配線
(14A1 ,16A1 )と基板10とが相互に接続さ
れ、これらには同一の電位VDDが与えられる。
According to the above-mentioned prior art, the power supply wiring (14) on the non-ground side of the digital IC section is used.
D 1 , 16D 1 ) and the non-grounded power supply wiring (14A 1 , 16A 1 ) of the analog IC section and the substrate 10 are connected to each other, and the same potential V DD is applied to them.

【0006】このような状態において、ディジタルIC
部12Dの動作に伴い配線層14D1 乃至基板10の電
位が変動すると、この電位変動はそのまま配線層14A
1 に伝達され、ノイズとしてアナログIC部12Aに混
入する。この結果、アナログIC部12Aでは、アナロ
グ的性能が劣化し、特にDA変換器等では変換誤差の増
大を招く不都合があった。
In such a state, the digital IC
When the potential of the wiring layer 14D 1 to the substrate 10 changes due to the operation of the portion 12D, this potential change remains as it is.
1 is transmitted to the analog IC unit 12A as noise. As a result, in the analog IC section 12A, the analog performance is deteriorated, and particularly in the DA converter or the like, there is a disadvantage that the conversion error increases.

【0007】この発明の目的は、ディジタルIC部の電
源配線から基板を介してアナログIC部の電源配線に混
入するノイズを低減することにある。
An object of the present invention is to reduce noise mixed from the power supply wiring of the digital IC section to the power supply wiring of the analog IC section through the substrate.

【0008】[0008]

【課題を解決するための手段】この発明は、上記したよ
うな集積回路装置において、アナログIC部の非接地側
電源配線を半導体基板から電気的に分離し且つ電磁的に
シールドする手段を設けたことを特徴とするものであ
る。
According to the present invention, in the integrated circuit device as described above, means for electrically separating the non-grounded power supply wiring of the analog IC portion from the semiconductor substrate and electromagnetically shielding it is provided. It is characterized by that.

【0009】[0009]

【作用】この発明の構成によれば、アナログIC部の非
接地側電源配線を基板から電気的に分離し且つ電磁的に
シールドしたので、ディジタルIC部から基板を介して
アナログIC部に混入するノイズが大幅に低減される。
According to the structure of the present invention, since the non-grounded power supply wiring of the analog IC section is electrically separated from the board and electromagnetically shielded, the digital IC section is mixed into the analog IC section through the board. Noise is greatly reduced.

【0010】[0010]

【実施例】図1は、この発明の一実施例によるディジタ
ル−アナログ混載ICにおけるアナログIC部の電源配
線構造を示すもので、図2〜3と同様の部分には同様の
符号を付して詳細な説明を省略する。
1 shows a power supply wiring structure of an analog IC portion in a digital-analog mixed IC according to an embodiment of the present invention. Parts similar to those in FIGS. Detailed description is omitted.

【0011】半導体基板10の表面を覆う絶縁膜11の
上には、例えばポリシリコンからなる導電層20が形成
されると共に、この導電層20の上には、シリコンオキ
サイド等の絶縁膜22を介してアナログIC部の非接地
側電源配線層14A1 が形成される。配線層14A1
は、電源電位VDDが付与される電源端子16A1 に接続
される一方、導電層20は、接地電位が付与される電源
端子16A2 に接続される。
A conductive layer 20 made of, for example, polysilicon is formed on the insulating film 11 covering the surface of the semiconductor substrate 10, and an insulating film 22 such as silicon oxide is provided on the conductive layer 20. As a result, the non-grounded power supply wiring layer 14A 1 of the analog IC section is formed. Wiring layer 14A 1
Is connected to the power supply terminal 16A 1 to which the power supply potential V DD is applied, while the conductive layer 20 is connected to the power supply terminal 16A 2 to which the ground potential is applied.

【0012】基板10には、ディジタルIC部の非接地
側の電源配線層14D1 が接続される。このため、ディ
ジタル系動作ノイズが基板10から配線層14A1 に混
入しようとするが、配線層14A1 が基板10から絶縁
膜11,22により電気的に分離され且つ導電層20に
より電磁的にシールドされているので、混入ノイズは大
幅に低減される。
A power supply wiring layer 14D 1 on the non-grounded side of the digital IC section is connected to the substrate 10. Therefore, although the digital system operating noise is to contamination from the substrate 10 to the wiring layer 14A 1, the wiring layer 14A 1 are electrically isolated by insulating films 11, 22 from the substrate 10 and electromagnetically shielded by the conductive layer 20 Therefore, the mixed noise is greatly reduced.

【0013】なお、配線層14A1 を基板10から電気
的に分離したのに伴って配線インピーダンスが上昇する
のを防ぐため、一例として配線層14A1 の幅を図3の
場合の2倍又はそれ以上に増大させるとよい。また、配
線層14A1 の厚さを増大させるか又は抵抗率を減少さ
せてもよい。
In order to prevent the wiring impedance from increasing due to the electrical separation of the wiring layer 14A 1 from the substrate 10, the width of the wiring layer 14A 1 is , for example, twice that of FIG. It is better to increase the above. Further, the thickness of the wiring layer 14A 1 may be increased or the resistivity may be decreased.

【0014】[0014]

【発明の効果】以上のように、この発明によれば、アナ
ログIC部の非接地側電源配線を基板から分離し且つシ
ールドすることによりアナログIC部への混入ノイズを
低減したので、アナログIC部のS/N比又は精度が向
上する効果が得られるものである。
As described above, according to the present invention, the noise mixed into the analog IC section is reduced by separating and shielding the non-grounded power supply wiring of the analog IC section from the substrate. The effect of improving the S / N ratio or accuracy of is obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】 この発明の一実施例によるアナログIC部の
電源配線構造を示す断面図である。
FIG. 1 is a cross-sectional view showing a power supply wiring structure of an analog IC section according to an embodiment of the present invention.

【図2】 従来のディジタル−アナログ混載ICチップ
の一例を示す斜視図である。
FIG. 2 is a perspective view showing an example of a conventional digital-analog mixed IC chip.

【図3】 図2のICチップにおけるアナログIC部の
電源配線構造を示す断面図である。
3 is a cross-sectional view showing a power supply wiring structure of an analog IC section in the IC chip of FIG.

【符号の説明】[Explanation of symbols]

10:半導体基板、11,22:絶縁膜、14A1 ,1
4A2,14D1 ,14D2 :電源配線層、16A1
16A2 ,16D1 ,16D2 :電源端子、20:シー
ルド用導電層。
10: Semiconductor substrate, 11, 22: Insulating film, 14A 1 , 1
4A 2 , 14D 1 , 14D 2 : power supply wiring layer, 16A 1 ,
16A 2, 16D 1, 16D 2 : power supply terminal, 20: shielding conductive layer.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/04 H 8427−4M ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 27/04 H 8427-4M

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 ディジタル集積回路部及びアナログ集積
回路部を共通の半導体基板に形成すると共に該ディジタ
ル集積回路部の非接地側電源配線を該半導体基板に接続
して成る集積回路装置において、 前記アナログ集積回路部の非接地側電源配線を前記半導
体基板から電気的に分離し且つ電磁的にシールドする手
段を設けたことを特徴とする集積回路装置。
1. An integrated circuit device in which a digital integrated circuit section and an analog integrated circuit section are formed on a common semiconductor substrate and the non-grounded power supply wiring of the digital integrated circuit section is connected to the semiconductor substrate. An integrated circuit device comprising means for electrically separating and electromagnetically shielding the non-grounded power supply wiring of the integrated circuit portion from the semiconductor substrate.
JP3331132A 1991-11-20 1991-11-20 Integrated circuit device Pending JPH05145021A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3331132A JPH05145021A (en) 1991-11-20 1991-11-20 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3331132A JPH05145021A (en) 1991-11-20 1991-11-20 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPH05145021A true JPH05145021A (en) 1993-06-11

Family

ID=18240229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3331132A Pending JPH05145021A (en) 1991-11-20 1991-11-20 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPH05145021A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6472747B2 (en) * 2001-03-02 2002-10-29 Qualcomm Incorporated Mixed analog and digital integrated circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6472747B2 (en) * 2001-03-02 2002-10-29 Qualcomm Incorporated Mixed analog and digital integrated circuits

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