JPH0569295B2 - - Google Patents
Info
- Publication number
- JPH0569295B2 JPH0569295B2 JP60238819A JP23881985A JPH0569295B2 JP H0569295 B2 JPH0569295 B2 JP H0569295B2 JP 60238819 A JP60238819 A JP 60238819A JP 23881985 A JP23881985 A JP 23881985A JP H0569295 B2 JPH0569295 B2 JP H0569295B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- wiring layer
- layer
- semiconductor integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010410 layer Substances 0.000 claims description 40
- 239000004065 semiconductor Substances 0.000 claims description 24
- 239000011229 interlayer Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路装置に関し、特に半
導体基板上に集積回路の各素子を組み込んで構成
する多層配線を用いた半導体集積回路装置の改良
に係るものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to improvement of a semiconductor integrated circuit device using multilayer interconnection formed by incorporating each element of an integrated circuit on a semiconductor substrate. This is related.
従来からこの種の半導体集積回路装置において
は、配線部、殊にAl配線層の配置態様の如何な
どによつて、装置の回路特性に影響を受けること
が知られている。すなわち、例えば微小電流レベ
ルによる信号処理に際し、外部から到来して回路
内に侵入するノイズの問題とか、パワーICなど
に見られるGNDの浮き上りの問題などがそれで、
それぞれに半導体集積回路装置の特性劣化をもた
らすものである。
It has been known that in this type of semiconductor integrated circuit device, the circuit characteristics of the device are affected by the arrangement of the wiring portion, especially the Al wiring layer. In other words, for example, when processing signals using minute current levels, there is the problem of noise coming from the outside and entering the circuit, or the problem of GND floating in power ICs.
Each of these causes deterioration of the characteristics of the semiconductor integrated circuit device.
このように従来の半導体集積回路装置にあつて
は、その回路機能に対応してAl配線層の配置態
様の仕方に十分な留意が必要であるとされ、この
ため回路設計などに大きな制約を受けるという問
題点があつた。
As described above, for conventional semiconductor integrated circuit devices, it is necessary to pay close attention to the layout of the Al wiring layer in accordance with the circuit function, and this imposes significant restrictions on circuit design. There was a problem.
この発明はこのような従来の問題点を改善する
ためになされたものであつて、その目的とすると
ころは、集積回路を外来ノイズから防護し、併せ
てGNDの浮き上りによる特性劣化を阻止し得る
ようにした、この種の半導体集積回路装置を提供
することである。 This invention was made to improve these conventional problems, and its purpose is to protect integrated circuits from external noise and also to prevent characteristic deterioration due to GND floating. An object of the present invention is to provide a semiconductor integrated circuit device of this type.
前記目的を達成するために、この発明に係る半
導体集積回路装置は、多層配線による半導体集積
回路装置にあつて、コレクタ領域,ベース領域お
よびエミツタ領域を有する半導体素子を含む集積
回路を構成する少なくとも各素子、ならびに下層
部側の各Al配線層の表面部全面を、層間絶縁膜
を介して、実質的にGNDとなる上層部のAl配線
層により被覆させるとともにAl配線層が層間絶
縁膜を貫通してエミツタ領域に接続させたもので
ある。
In order to achieve the above object, a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device with multilayer wiring, in which at least each of the integrated circuits constituting the integrated circuit includes a semiconductor element having a collector region, a base region, and an emitter region. The entire surface of the element and each of the lower Al wiring layers is covered with the upper Al wiring layer, which is essentially GND, via the interlayer insulating film, and the Al wiring layer penetrates the interlayer insulating film. and connected to the emitter area.
この発明においては、集積回路を構成している
各素子、および下層部側の各Al配線層の表面部
の全面を、GNDとしての上層部のAl配線層によ
り、層間絶縁膜を介し被覆させるとともにAl配
線層が層間絶縁膜を貫通してエミツタ領域に接続
させることによつて、結果的には、集積回路の構
成自体を、回路動作の一つの基準となるGNDに
よりシールドし得るのである。
In this invention, each element constituting an integrated circuit and the entire surface of each lower Al wiring layer are covered with the upper Al wiring layer as GND via an interlayer insulating film. By penetrating the interlayer insulating film and connecting the Al wiring layer to the emitter region, the integrated circuit structure itself can be shielded by GND, which is one of the standards for circuit operation.
以下、この発明に係る半導体集積回路装置の一
実施例につき、添付図面を参照して詳細に説明す
る。
Hereinafter, one embodiment of a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the accompanying drawings.
添付図面は、この実施例をバイポーラ型の多層
配線構造を用いる半導体集積回路装置に適用した
場合の要部構成を示す部分断面図である。 The accompanying drawing is a partial cross-sectional view showing the configuration of main parts when this embodiment is applied to a semiconductor integrated circuit device using a bipolar multilayer wiring structure.
同添付図面において、符号1はシリコン半導体
基板、2は素子間分離拡散層、3はフローテイン
グコレクタ拡散層である。また4はベース拡散な
どによる抵抗素子領域、5,6、および7は
NPNトランジスタを構成するコレクタ,ベース,
およびエミツタの各領域であり、さらに8は第1
層のAl配線層、9はこれらの少なくとも必要と
される各素子、ならびに第1層のAl配線層など
の表面部のほゞ全面を、層間絶縁膜10の介在に
よつて覆う第2層のAl配線層である。 In the accompanying drawings, reference numeral 1 indicates a silicon semiconductor substrate, 2 an element isolation diffusion layer, and 3 a floating collector diffusion layer. In addition, 4 is a resistive element region formed by base diffusion, etc., and 5, 6, and 7 are
The collector, base, and
and each area of the emitter, and 8 is the first
The Al wiring layer 9 is a second layer that covers at least each of the required elements as well as almost the entire surface of the first layer Al wiring layer etc. with an interlayer insulating film 10 interposed. This is an Al wiring layer.
なお、この第2層Al配線層9をその一部分が
層間絶縁膜10を貫通してシリコン半導体基板1
の表面に形成されたエミツタ形成領域7に電気的
に接続されている。 Note that a part of the second Al wiring layer 9 penetrates through the interlayer insulating film 10 to form the silicon semiconductor substrate 1.
It is electrically connected to an emitter formation region 7 formed on the surface of the emitter.
すなわち、この実施例による装置構成にあつて
は、集積回路を構成するところの、抵抗素子とか
トランジスタ、それにAl配線層などの表面部に
関し、これを全体的にGNDとなるAl配線層の被
覆によつて、実質的にシールドすることができる
のである。 In other words, in the device configuration according to this embodiment, the surface parts of the resistive elements, transistors, and Al wiring layers that make up the integrated circuit are covered with an Al wiring layer that serves as the overall GND. Therefore, it can be substantially shielded.
なお、前記実施例においては、この発明をバイ
ポーラ型半導体集積回路装置に適用する場合につ
いて述べたが、その他、例えばMOS型半導体集
積回路装置などにも適用できることは勿論であ
り、また上下2層のAl配線層のみに限らず、よ
り以上多層のAl配線層を有する場合にも適用可
能であつて、同様な作用効果を得られる。 In the above embodiments, the case where the present invention is applied to a bipolar type semiconductor integrated circuit device has been described, but it is of course applicable to other types of semiconductor integrated circuit devices, such as a MOS type semiconductor integrated circuit device. It is applicable not only to Al wiring layers but also to cases where there are more than one Al wiring layer, and similar effects can be obtained.
以上詳述したようにこの発明によるときは、多
層配線による半導体集積回路装置にあつて、コレ
クタ領域,ベース領域およびエミツタ領域を有す
る半導体素子を含む集積回路を構成するところ
の、少なくとも必要とされる各素子領域、それに
下層部側の各Al配線層などの表面部の全面を、
上層部のAl配線層により層間絶縁膜を介して被
覆させるとともにAl配線層が層間絶縁膜を貫通
してエミツタ領域に接続させるようにしたから、
この上層部のAl配線層がGNDとして、これらの
回路構成要素を外部に対して実質的にシールドす
ることができるのであり、この構成によつて集積
回路内への外来ノイズの侵入を防止し得ると共
に、GNDの浮き上りによる回路特性の劣化をも
効果的に阻止でき、併せてAl配線層による電圧
降下も少なくて済み、しかも構成的にも極めて簡
単で容易に実施可能であるなどの特長を有するも
のである。
As detailed above, according to the present invention, in a semiconductor integrated circuit device with multilayer wiring, at least the necessary The entire surface area of each element area and each Al wiring layer on the lower layer side,
Since it is covered by the upper Al wiring layer via the interlayer insulating film, and the Al wiring layer penetrates the interlayer insulating film and connects to the emitter region,
This upper Al wiring layer acts as a GND and can essentially shield these circuit components from the outside, and this configuration can prevent external noise from entering the integrated circuit. At the same time, it can effectively prevent the deterioration of circuit characteristics due to GND floating, and the voltage drop due to the Al wiring layer is also small, and the structure is extremely simple and can be easily implemented. It is something that you have.
添付図面はこの発明に係る半導体集積回路装置
の一実施例による概要構成を示す要部断面図であ
る。
1……シリコン半導体基板、2……素子間分離
拡散層、3……フローテイングコレクタ拡散層、
4……抵抗素子領域、5,6、および7……
NPNトランジスタを構成するコレクタ,ベース、
およびエミツタ領域、8……第1層(下層)Al
配線層、9……第2層(上層)Al配線層、10
……層間絶縁膜。
The accompanying drawing is a sectional view of a main part showing a schematic configuration of an embodiment of a semiconductor integrated circuit device according to the present invention. 1... Silicon semiconductor substrate, 2... Inter-element isolation diffusion layer, 3... Floating collector diffusion layer,
4...Resistance element area, 5, 6, and 7...
The collector, base, and
and emitter region, 8...first layer (lower layer) Al
Wiring layer, 9... Second layer (upper layer) Al wiring layer, 10
...Interlayer insulating film.
Claims (1)
よびエミツタ領域が形成された半導体素子を含む
集積回路の各素子を組み込んで構成する多層配線
を用いた半導体集積回路装置において、 前記集積回路の少なくとも各素子、ならびに下
層部部側の各Al配線層の表面部を、層間絶縁膜
を介して、実質的にGNDとなる上層部のAl配線
層により被覆させるとともに前記上層部のAl配
線層が前記層間絶縁膜を貫通して前記エミツタ領
域に接続させたことを特徴とする半導体集積回路
装置。[Scope of Claims] 1. A semiconductor integrated circuit device using multilayer wiring configured by incorporating each element of an integrated circuit including a semiconductor element in which a collector region, a base region, and an emitter region are formed on a semiconductor substrate, comprising: At least each element of the circuit and the surface part of each Al wiring layer on the lower layer side are covered with the upper Al wiring layer which becomes substantially GND via an interlayer insulating film, and the Al wiring layer on the upper layer A semiconductor integrated circuit device characterized in that a layer passes through the interlayer insulating film and is connected to the emitter region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23881985A JPS6297351A (en) | 1985-10-23 | 1985-10-23 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23881985A JPS6297351A (en) | 1985-10-23 | 1985-10-23 | Semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6297351A JPS6297351A (en) | 1987-05-06 |
JPH0569295B2 true JPH0569295B2 (en) | 1993-09-30 |
Family
ID=17035748
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23881985A Granted JPS6297351A (en) | 1985-10-23 | 1985-10-23 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6297351A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50102280A (en) * | 1974-01-09 | 1975-08-13 | ||
JPS5214387A (en) * | 1975-07-25 | 1977-02-03 | Hitachi Ltd | Semiconductor device |
-
1985
- 1985-10-23 JP JP23881985A patent/JPS6297351A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50102280A (en) * | 1974-01-09 | 1975-08-13 | ||
JPS5214387A (en) * | 1975-07-25 | 1977-02-03 | Hitachi Ltd | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS6297351A (en) | 1987-05-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |