JPH0571912U - Controller for reactive power compensator - Google Patents

Abstract

(57) [Summary] [Purpose] The bus voltage V _in of the power system is passed through the low-pass filter 10 only for the purpose of suppressing the voltage fluctuation ΔV due to the load fluctuation, and its long-period component is extracted as the target reference voltage V _ref. In the SVC that performs the AVR control so that the system voltage V _in (V _l ) follows the voltage drop ΔV.
The error of the target reference voltage V _ref due to is removed. A low-pass filter for extracting a long-period component of a bus voltage V _l and setting it as a target reference voltage V _ref, and an output of this low-pass filter as an input signal, and is obtained by differentiating a difference voltage between the bus voltage and the target reference voltage. Hold pulse H and sampling signal S
In addition, from the time when the hold signal is generated to the time when the sampling signal is generated, the sample hold circuit 18 is provided which changes the hold value to the output of the low pass filter 10 as the target reference voltage V _ref and outputs it.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

The present invention relates to a control device for a reactive power compensator (hereinafter referred to as SVC) which controls a reactive power compensator installed in an AC power system so that a system voltage V ₁ follows a target reference voltage V _ref .

[0002]

[Prior Art]

If the SVC is installed in a power system such as the Shinkansen where the load current cannot be detected, the reactive power of the load cannot be calculated. Therefore, this fluctuation is immediately compensated to stabilize the reactive power of the entire system. I can't. Therefore, in such a system, voltage control (AVR control) is performed to make the system voltage V ₁ follow the target reference voltage V _ref by increasing / decreasing the reactive power compensation amount. There are long-term fluctuations of the power supply and short-term fluctuations of the power supply, and the power supply voltage is managed and controlled by the LRT of the substation and the voltage adjustment mechanism of the phase adjusting equipment. From the viewpoint of equipment efficiency, it is required that the SVC that operates behaves so as to suppress only voltage fluctuations due to load fluctuations. The target reference voltage V _{ref in} this case is ideally a long-period component of the voltage at the power transmission end in a substation or the like that manages the power supply voltage. However, SVCs are installed far away from the above substations, and in many cases they cannot receive them.

Therefore, in such a case, as shown in FIG. 4, the system bus voltage V _l is input to a low-pass filter (first-order lag element) to extract a long-period component of the power supply voltage and set as a target reference voltage V _ref. There is.

In FIG. 4, reference numeral 1 denotes a system bus, which is connected to a substation power source E _S through a substation-side impedance X _S and supplies power to a train load 2 which is a variable load. Reference numeral 3 is an SVC connected to the system bus 1, which is a parallel connection of a thyristor control reactor (hereinafter referred to as TCR) and a filter (hereinafter referred to as FC). The TCR is composed of an anti-parallel connection thyristor 4 and a reactor X _L such as a high impedance transformer that generates a lagging power Q _TCR , and FC is a capacitor 5 that generates a constant leading power Q _FC. It is composed of a capacitor 5 and a small-capacity series reactor 6 that absorbs harmonics. Two FCs in the illustrated example are provided corresponding to different harmonics.

The principle of this SVC voltage control is that a constant advanced power Q _FC is supplied by _FC and the lagging power Q _TCR supplied by _TCR is increased or decreased so that the total amount of SVC applied to the system bus 1 is increased. The reactive power is increased or decreased to adjust the reactance drop ΔV at the substation-side impedance X _S =% Z of the system bus 1. When increasing the voltage, the lagging power Q _TCR generated by _TCR is decreased. When the voltage is lowered by increasing the phase-advancing power, the lag-phase power Q _TCR generated by the _TCR is increased.

A PLL circuit 7 is connected to the system bus 1 via a step-down transformer PT ₁ and an input transformer PT _2, and produces a voltage synchronization signal from the system voltage V _l . A logic circuit 8 generates a block zone signal that determines the non-firing period of the thyristor 4 from the power supply synchronizing signal. Reference numeral 9 denotes a voltage detection circuit, which detects the system bus voltage V ₁ as an effective value V _in via the step-down transformer PT ₁ and the input transformer PT ₃ . Reference numeral 10 is a low-pass filter having 1 / (1 + ST ₁ ) as a transfer function, which extracts a long-period component corresponding to the power supply voltage fluctuation from the detected value V _in of the bus voltage. A subtracter 11 subtracts the target reference voltage V _ref from the detected system voltage V _in and outputs it. Reference numeral 12 is a controller circuit for performing AVR control, which amplifies the subtracted value with a tunable time constant ST ₂ and an amplification factor K ₂ . A function circuit 13 receives the output of the controller circuit 12 and linearly converts the corresponding current I _TCR into an ignition phase angle signal β flowing through the thyristor 4. A pulse generator 14 generates positive and negative trigger pulses from the firing phase angle signal β under the restriction of the block zone signal. Reference numeral 15 is a pulse amplifier which outputs a trigger pulse to the gates G ₁ and G ₂ of the thyristor.

In the above configuration, the long-pass component of the system voltage V _l is extracted by the low-pass filter 10 and is used as the target reference voltage V _ref , and the difference (V _in −V _ref ) between this and the detected value V _in of the system voltage. Is subtracted by the subtracter 11 and this difference is input to the controller circuit 12 to increase or decrease the delayed power Q _TCR of the TCR so that the detected value V _in (V _l ) of the system voltage approaches the target reference voltage V _ref. AVR control is performed. Since the voltage fluctuation ΔV due to the fluctuation of the load to be controlled is generated by being superimposed on this long-period component, only this voltage fluctuation ΔV can be suppressed.

[0008]

[Problems to be solved by the device]

In the above control method, the target reference voltage V _ref is obtained by passing the system voltage through the low-pass filter 10, which is a first-order lag element. Therefore, as shown in FIG. 5, the target reference voltage V _ref (dashed-dotted line) decreases with a rate according to the time constant of the low-pass filter with respect to the voltage drop ΔV during the transition when the train load 2 arrives, and , Even after the train load 2 passes, it will return with a delay. This has an error with respect to the ideal target reference voltage V _ref ′ (two-dot chain line) when there is no voltage drop ΔV. AVR control of SVC is feedback control, the system voltage V _l Since changes following the target reference voltage V _ref (one point chain line) with the error, the precision of finish voltage V _l is deteriorated, optimal control I couldn't say that.

Therefore, in the present invention, in the SVC of the AVR control system in which the system voltage V _l is passed through the low-pass filter 10 to obtain the target reference voltage V _ref , the accuracy of the SVC is not affected by the voltage fluctuation Δ V due to the load fluctuation. It is an object to provide a control device that can obtain a high target reference voltage V _ref .

[0010]

[Means for Solving the Problems]

 The present invention detects the difference between the target reference voltage and the system voltage, uses this as a control signal to increase or decrease the reactive power supplied to the system bus by the reactive power compensator, and causes the system voltage to follow the target reference voltage. A low-pass filter that extracts the long-period component of the voltage and outputs it as the target reference voltage, a differentiation circuit that differentiates the difference voltage between the system voltage and the target reference voltage, the output of the low-pass filter as the input signal, and the falling pulse of the differentiation circuit output. And a rising pulse as a hold signal and a sampling signal, and from the time when the hold signal is generated until the time when the sampling signal is generated, the hold value is changed to the output of the low pass filter and output as the target reference voltage. We propose a controller for the reactive power compensator.

[0011]

[Action]

The above configuration is a differentiation circuit that detects a sudden change in the system voltage, that is, a voltage drop due to train entry and a voltage rise due to passage, and the output of the low-pass filter is held by the sample hold circuit at the start of this voltage drop until the train passes by. , This hold value is used as the target reference voltage instead of the output of the low pass filter. As a result, the voltage fluctuation due to the load is input, and the target reference voltage V _ref during the period in which an error occurs in the output of the low pass filter is maintained in the state immediately before the error.

[0012]

【Example】

An example of the configuration of this invention will be described with reference to FIG. FIG. 1 shows a system bus 1 that is connected to a substation power source E _S through a substation impedance X _S and that is provided with a SVC and a control device 16 of the present invention on a system bus 1 that feeds a load 2. Items are given the same reference numerals.

The SVC is configured by connecting a TCR and an FC in parallel to a bus 1. The TCR is composed of an anti-parallel connection thyristor 4 and a reactor X _L such as a high impedance transformer that generates a lagging power Q _TCR. Composed. In addition, instead of a high-impedance transformer, a normal transformer and a series reactor may be used. The FC is composed of a capacitor 5 that generates a constant lead reactive power Q _FC, and a series reactor 6 that absorbs harmonics of the busbar with the capacitor 5. In the illustrated example, FCs for the second and third harmonics are provided.

Reference numeral 16 is an SVC controller, and an improvement over the conventional configuration shown in FIG. 3 is the addition of a correction circuit 17 for fixing the output of the low-pass filter 10 to a value immediately before the start of fluctuation during the load fluctuation period.

Listed below are the parts equivalent to those of the conventional device, a step-down transformer PT ₁ , an input transformer PT ₂ , an input transformer PT ₃ , a PLL circuit 7 for obtaining a voltage synchronization signal from the system voltage V _l, and an ignition inhibition period of the thyristor 4. A logic circuit 8 for generating a block zone signal for determining the voltage, a voltage detection circuit 9 for detecting the bus voltage V _{l of the} system with an effective value, a low-pass filter 10 for extracting a long-period component from the detected value V _in of the bus voltage, and the detected system A subtractor 11 that subtracts the target reference voltage V _ref from the voltage V _in and outputs it, has an adjustable amplification factor K ₂ and a first-order time constant ST ₂ , and outputs the output of the subtractor 11 by proportionally integrating the AVR control. The controller circuit 12 for performing the adjustment, the function circuit 13 for linearly converting the output of the controller circuit 12 into the firing phase angle signal β of the thyristor 4, the firing phase angle signal β and the block A pulse generator 14 for generating positive and negative trigger pulses from a zone signal and a pulse amplifier 15 for outputting the trigger pulse to the gate of the thyristor 4.

The correction circuit 17, which is a feature of the present invention, is configured as follows. Reference _numeral 18 denotes a sample hold circuit, which receives the low-pass filter 10 as an input signal and outputs its output as a target reference voltage V _ref . A subtracter 19 subtracts the output V _ref of the sample hold circuit 18 from the detected value V _in of the system voltage V _l and outputs it. 20 is a differentiating circuit, which differentiates the subtracted value and generates falling and rising pulses corresponding to the sudden drop and sudden rise of the voltage due to the arrival and passage of the train, and holds it in the sample hold circuit 18. The signal H and the sampling signal S are output. The subtractor 19 is for taking out the voltage fluctuation due to the load without being affected by the long-period component of the power supply.

The operation of the correction circuit 17 will be described with reference to the waveform chart of FIG.

When the train load 2 arrives and passes by, the system voltage V _l drops sharply as shown by the solid line in FIG. 2a and recovers after a predetermined time. This voltage fluctuation ΔV is detected by the differentiating circuit 20, and the falling pulse P _down and the rising pulse P _up are generated. These pulses are output to the sample hold circuit 18 as a hold signal H and a sampling signal S. Due to this hold signal H, the output of the sample hold circuit 8 is fixed to the output of the low pass filter immediately before that which is not affected by the voltage drop ΔV. When the sampling signal S is generated, the hold is released, and the output of the low pass filter 10 is output as it is as the target reference voltage V _ref . Therefore, the conventional device of FIG. 3 uses the output of the low-pass filter 10 as the target reference voltage V _ref as it is without any error, and the target reference voltage V _ref is the voltage as shown by the chain line in FIG. 2a. It becomes an ideal one that is not affected by the fluctuation ΔV, and the finishing voltage V ₁ by the AVR control of SVC follows this and is also controlled with high precision.

FIG. 3 is a diagram showing an operation example of the sample hold circuit 8. The system voltage V _l is increased by the AVR control of S VC so as to eliminate the voltage drop ΔV as shown in FIG. 2a with a predetermined time constant S T ₂ . Therefore, if this time constant ST ₂ is made sufficiently small with respect to the period during which the voltage drop ΔV occurs, the recovered voltage is input to the low-pass filter 10 while the train is passing, and the sampling signal S immediately after the train is passing. At the generation timing, the output of the sample hold circuit 10 can be made to substantially match the ideal target reference voltage V _ref as shown in FIG. In this case, the constants of the control device 16 are, for example, the time constant ST ₁ of the low pass filter 10 of several tens of seconds, the time constant ST ₂ of the adjustment circuit 12 of several seconds, and the time constant ST ₃ of the differentiating circuit 20 of several. m seconds

[0020]

[Effect of the device]

This invention, in reactive power compensator of the voltage control method to obtain a target reference voltage V _{r ef} through system voltage V _in the (V _l) to the low-pass filter, to the voltage fluctuation due to load fluctuation is input to the low pass filter By replacing the period in which an error occurs with the hold value of the sample hold circuit and using it, the target reference voltage V _ref can be taken out without being affected by the voltage fluctuation ΔV due to load fluctuation, and optimal control is possible. become.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a controller for a reactive power compensator according to the present invention.

FIG. 2 is a target reference voltage in the control device shown in FIG.
The wave form diagram which shows the relationship of a differentiating circuit output, hold, and the timing of sampling.

FIG. 3 is a waveform diagram showing an operation example of a sample hold circuit of the control device shown in FIG.

FIG. 4 shows an example of a conventional reactive power compensator.

5 is a waveform diagram explaining the reason why an error occurs in the target reference voltage in the device shown in FIG.

[Explanation of symbols]

1 system bus 2 load 3 SVC 9 voltage detector 10 low-pass filter 11 subtractor 16 controller 17 correction circuit 18 sample hold circuit 19 subtractor _Vl system voltage V _in system voltage detection value (effective value) V _ref target reference voltage ΔV Voltage drop due to load fluctuation

Claims (1)

[Scope of utility model registration request] 1. A difference between a target reference voltage and a system voltage is detected,
With this as a control signal, the reactive power compensator increases or decreases the reactive power supplied to the system bus to make the system voltage follow the target reference voltage.A low-pass filter that extracts the long-period component of the system voltage and outputs it as the target reference voltage , A differentiation circuit that differentiates the difference voltage between the system voltage and the target reference voltage, the output of the low-pass filter is the input signal, the falling pulse and the rising pulse of the differentiation circuit output are the hold signal and the sampling signal, and when the hold signal is generated, A control device for a reactive power compensator, comprising a sample hold circuit for changing the hold value to the output of the low pass filter and outputting it as a target reference voltage until a sampling signal is generated.