JPH05199660A - Controller for voltage fluctuation suppressor - Google Patents

Abstract

PURPOSE:To reduce a facility capacity and to improve a facility utilization ratio by suppressing only a voltage fluctuation due to a load fluctuation without being influenced by a power source fluctuation in a TSC(Thyristor Switched Capacitor) for suppressing the voltage fluctuation by controlling open or close of a plurality of phase advancing capacitors disposed on a system bus. CONSTITUTION:A TSC has a plurality of capacitors C1-Cn for supplying phase advancing powers to a power source system and stepwisely switch the number of the applying capacitors to suppress a voltage fluctuation DELTAV due to a load fluctuation of the system. A detected value Vin of a system voltage detected by a voltage detector 9 is passed through a low pass filter 15, its long period component is output as a voltage reference value VS, and applying level Vref and removing level Vrefo of the capacitors C1-Cn are decided to be proportional to the value VS by a level deciding circuit 16. The number of the applying capacitors C1-Cn in so increased or decreased by a capacitor switching controller 17 that the detected value Vin of the system voltage V1 falls between both the levels.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a voltage fluctuation suppressing device installed in an AC power supply system, and more particularly to a TSC suppressing a voltage fluctuation by controlling opening / closing of a plurality of phase advancing capacitors installed in a system bus. (Thyristor Switched Capacit
or)) control method.

[0002]

2. Description of the Related Art As shown in FIG. 5, a TSC used for the purpose of suppressing voltage fluctuations on a system bus has phase-advancing capacitors C ₁ -C _n installed on a system bus 1 and thyristors Th _1- .
The switching control is performed at Th _n , and the phase-advancing power according to the voltage fluctuation is supplied to the system to suppress the voltage fluctuation due to the variable load 2 and the like.

In FIG. 5, a system bus 1 is a substation power source E.
_{It is} connected to _S through the substation side impedance XS and supplies power to the load 2 such as an incoming train. 3 _{1 to} 3 _n are system bus 1
In the TSC connected to, a reactor L having a capacity of several% of the capacity of the capacitors C _{1 to} C _{n.
1 to} L _n , thyristors Th _{1 to} Th _n and diode D
It constituted a parallel circuit 4 ₁ to 4 _n of ₁ to D _n are connected in series.
The parallel circuit 4 ₁ to 4 _n, by on-off control of the current half-wave period in the thyristor Th ₁ to TH _n, and performs off-on-pulling capacitor C ₁ -C _n, in the OFF The capacitors C _{1 to} C _n stand by while being charged in the forward direction of the diodes D _{1 to} D _n .

Reference numeral 6 denotes a TSC control device, which sets the detected value V _in of the system voltage V _{l to} a supply level V _ref1 to which is set for each TSC.
Compared with V _refn , if it falls below this, the corresponding TSC
3 ₁ was charged to 3 _n capacitors C ₁ -C _n of, exceeds this level recovered voltage, tripping it.

In the control device 6, a power supply synchronizing circuit 7 is connected to the system bus 1 via a step-down transformer PT ₁ and an input transformer PT ₂ and produces a voltage synchronizing signal from a system voltage V _l . 8 is a block zone circuit, for generating a block zone signal defining a non-ignition period of the thyristor Th ₁ to TH _n from the power source synchronization signal. 9 is a voltage detection circuit,
The bus voltage V _{l of the} system is detected via the voltage transformer PT ₁ and the input transformer PT ₃ , and the effective value thereof is output as the voltage detection value V _in . Reference numerals 10 ₁ to 10 _n are _setters that set the input levels V _{ref1 to} V _refn corresponding to the TSCs 3 _{1 to} 3 _n , 11 ₁
In to 11 _n are subtracters, charged level V from the voltage detection value V _in
Subtract _{ref1 to Vrefn} . Reference numerals 12 _{1 to} 12 _{n denote} adders, which add the block zone signal to the subtracted value to raise the subtracted value during the block zone period, in which the system voltage V _l is sufficiently high and it is not necessary to turn on the capacitor. It corresponds to. Reference numerals 13 _{1 to} 13 _{n denote} comparators provided with a hysteresis function to prevent chattering, and adders 12 ₁ to 1
When the output of 2 _n is a voltage below a certain level (indicating that the voltage detection value V _in has fallen below the input levels V _{ref1 to} V _refn ), a thyristor trigger signal is generated and the corresponding TS is generated.
The gate of the thyristor Th ₁ to TH _n of C3 ₁ to 3 _n, and outputs through the amplifiers A ₁ to A _n. By this output, the number of phase advancing capacitors C _{1 to} C _n corresponding to the amount of decrease in the system voltage V _l
Is input to the system bus 1 to suppress voltage fluctuations.

[0006]

In the above conventional control method, the input levels (tripping levels) of the phase advancing capacitors C _{1 to} C _n are fixed values V _{ref1 to} V _refn , and only the voltage variation ΔV due to the load variation. It also responds to changes in the power supply E _S.

For this reason, as shown in FIG. 6, there is a case where the system does not respond to the voltage variation ΔV due to the load variation which is the original control target, or the capacity becomes insufficient. For example, if the voltage of the substation power supply E _S is large, even if there is a voltage dip ΔV due to load fluctuation, the voltage value is a,
As shown in b, the maximum value V of the input levels V _{ref1 to} V _refn
May exceeds the _MAX, not been made up of the phase advancing capacitor C ₁ -C _n is about that exceed the portion, not compensated. When the voltage of the substation power supply E _S is low,
Since a corresponding number of phase-advancing capacitors are always turned on, even if there is a voltage dip ΔV due to a load change as shown in c of FIG. Cannot be compensated.

In this case, if the total capacitance of the capacitors is increased, it is possible to suppress the voltage dip ΔV when the system voltage E _S is low, but it is difficult to suppress the voltage dip ΔV when the system voltage E _S is high. There is a problem that equipment costs will increase.

As described above, since the conventional equipment responds to the fluctuation of the power supply voltage E _S , the voltage fluctuation ΔV due to the load fluctuation, which is the original control purpose, cannot be completely compensated, and the equipment is used for this purpose. There was a problem that the rate was low. Therefore, an object of the present invention is to provide a control device capable of reliably compensating for voltage fluctuation ΔV due to load fluctuation, provided that a phase advancing capacitor having a capacity corresponding to the magnitude of load fluctuation is provided.

[0010]

SUMMARY OF THE INVENTION According to the present invention, a plurality of capacitors installed in a power supply system and supplying reactive power are controlled to be opened and closed, and the number of the capacitors is switched in stages to prevent voltage fluctuation due to load fluctuation of the system. In the suppression, a voltage detection circuit that detects a system voltage, a low-pass filter that extracts a long-period component of the detected system voltage and uses it as a voltage reference value,
A level determination circuit that determines the closing level and the tripping level of the capacitor that follows the long-period component of the system voltage from this voltage reference value, and these levels are compared with the detected system voltage. There is provided a control device for a voltage fluctuation suppressing device, comprising: a control circuit for increasing or decreasing the number of capacitors to be inserted so as to be in between.

[0011]

With the above construction, the long-period component of the power supply voltage that is not to be suppressed is detected by the low-pass filter, and this is used as the reference value, and the closing level and tripping level of the phase-advancing capacitor are determined so as to follow this. Since the voltage fluctuation ΔV due to the load fluctuation to be controlled occurs in the form of being superimposed on this long-period component, if the number of leading capacitors is increased or decreased depending on these levels, only the voltage fluctuation due to the load fluctuation is compensated. it can. Furthermore, the TSC can achieve its intended purpose if it has a capacitor capacity large enough to cope with load fluctuations.
High capacity factor can be obtained.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention is shown in FIG. 1 and will be described below. The same parts as those in FIG. 5 are designated by the same reference numerals. In FIG. 1, 1 is a system bus that is fed from the substation power supply E _S through the substation-side impedance X _S , 2
Is the variable load such as train load. 3 _{1 to} 3 _n are TSC,
The phase-advancing capacitors C _{1 to} C _n are provided with reactors L _{1 to} L _n having a capacity of about several percent of the phase advancing capacitors, diodes D _{1 to} D _n, and antiparallel circuits 4 ₁ to 4 of thyristors Th _{1 to} Th _n. It is configured by connecting _n in series. This TSC3
The total capacity of _{1 to} 3 _n is a size capable of suppressing the voltage fluctuation ΔV due to the load fluctuation occurring in the system, that is,% Z (=
ΔV) = (total capacity of TSC) / (short-circuit capacity P _S of the system)
It should be set to the relationship of. In this embodiment, as an opening and closing circuit of a capacitor C ₁ -C _n, but using reverse parallel circuit 4 ₁ to 4 _n diode and a thyristor, it is used after reverse parallel connection pairs thyristor Good.

Reference numeral 14 is a control device for controlling the opening and closing of the thyristors Th _{1 to} Th _n of the TSC according to the load fluctuation of the system bus 1. In this control device 14, 7 is a power supply synchronizing circuit composed of a PLL circuit, which is a step-down transformer P.
It is connected to the system bus 1 via T ₁ and the input transformer PT _2, and takes out the power supply synchronizing signal of the bus voltage V _l . A block zone circuit 8 receives the power supply synchronizing signal and energizes the diodes D _{1 to} D _n as shown in FIG.
to h ₁ to TH _n period of not energized (hatched portion) for generating a block zone signal V _B. In addition, the thyristors Th _{1 to} Th
During the energization period of _n (gate pulse generation period), the current flowing through the capacitors C _{1 to} C _n is approximately 90 ° with respect to the bus voltage V _l .
Because of the advancing relationship, the period shown by the diagonal lines in FIG. 2 is set.

A voltage detection circuit 9 receives the bus voltage V _l through the step-down transformer PT ₁ and the input transformer PT ₃ , and outputs its effective value as a voltage detection value V _in . A low-pass filter 15 receives the detected voltage value V _in and outputs the long-period component as a voltage reference value V _S. For example, a low-pass filter having a gain of K ≧ 1 and a time constant ST ₁ of several tens of seconds is used.

Reference numeral 16 is a level determining circuit, which is composed of a voltage dividing circuit in which resistors R ₁ , R ₂ and R ₃ are connected in series as shown in the figure, and a voltage reference value V _s output from the low pass filter 15 is set to a predetermined value. by applying in a ratio minutes, phase advancing capacitor C ₁ ~
Determining a charged level V _REFI and trip level V _REFO of C _n. In this embodiment, the input level is V _refI.
= K · V _in · R ₃ / (R ₁ + R ₂ + R ₃ ), the trip level is V _refO = K · V _in · (R ₂ + R ₃ ) / (R ₁ + R ₂ + R
₃ ) However, K · V _in = V _S.

Reference numeral 17 denotes a first and a second comparator 18 ₁ , 1
8 ₂ , an up / down counter 19, and an open / close control circuit for a capacitor, which is composed of an output circuit 20, compares the voltage detection value V _in with a closing level V _refI and a trip level V _refO ,
The number of capacitors C _{1 to} C _{n to} be _{turned on} is increased or decreased so that the detected voltage value V _in falls between these levels V _refI and V _refO .

In the open / close control circuit 17, the first comparator 18 ₁ outputs a count-up signal to the up-down counter 19 when the voltage detection value V _in falls below the _closing level V _refI . The second comparator 18 ₂ outputs a countdown signal to the up / down counter 19 when the voltage detection value V _in exceeds the trip level V _refO . The up / down counter 19 has a decode output that sets the output terminals from the lowest digit to the digit corresponding to the count value to high level (capacitor input command), and each digit ₁ to _n of the output terminal is each TSC3 _{1 to} 3. _There is a one-to-one correspondence with _n . The output circuit 20 includes an adder 2 forcibly setting the decode output during the generation period of the block zone signal V _B to a low level.
1 _{1 to} 21 _n, and amplifiers A _{1 to} A _n that amplify the decoded output that has passed through this adder and output as a trigger pulse to the gates of the corresponding TSC thyristors Th _{1 to} Th _n . .. This configuration is used for TSC thyristors Th _{1 to} Th corresponding to the high-level digit of the decoded output.
_n is turned on at a predetermined timing shown in FIG. 2, and the capacitors C _{1 to} C _n are put into the system bus 1.

The operation of the apparatus shown in FIG. 1 will be described with reference to the waveform charts shown in FIGS. As shown in FIG. 3, when the power supply E _S that fluctuates in a long cycle (several minutes) is supplied to the system bus 1, the train load 2 arrives and the voltage dip ΔV such as a, b, and c in the figure is reached. Consider the case in which the occurrence of the above occurs when it is suppressed by the device of the present invention. In this case, the total capacitance of the TSC capacitor is equal to this voltage drop Δ, as described above.
Since they are set on the assumption of the magnitude of V, these are in the voltage adjustable range of the capacitors C _{1 to} C _n .

The charged level V _REFI and trip level V _REFO output by the level determining circuit 16, so follow the bus voltage V _l to the voltage reference value V _S is taken out of the long-period component, the voltage dip a, b, c At any point of time, the detected voltage value V _{in of} these levels V _refI and V _refO and the bus voltage V _l
And have a relationship as shown in FIG.

When the train load 2 arrives and the voltage dip ΔV starts to cause the voltage detection value V _in to fall _{below the} input level V _refI , the first comparator 18 ₁ detects this and
The up / down counter 19 is incremented by one.
As a result, only the least significant digit of the output terminal goes high,
The output circuit 20 corresponds to the thyristor Th of the corresponding TSC.
_{At 1} , the trigger pulse output at the timing shown in FIG. 2 is started. Thus, the system voltage V _l, the capacitor C ₁
And the voltage fluctuation is suppressed. When the power supply to the load 2 further increases and the bus voltage V _l drops and the detected voltage value V _in tries to fall _{below the closing} level V _refI again, the first comparator 18 ₁ again goes up and down. The counter 19 is incremented by one. As a result, the output circuit 20 becomes a TSC thyristor Th _1, Th _2.
Is made conductive, the number of capacitors inserted in the system bus 1 increases by 1, and the voltage dip ΔV is suppressed again. This additional charging operation of the capacitors is performed in response to the increase in the power supply to the load 2, and when the power supplied to the load does not change, the number of capacitors to be charged does not increase or decrease. When the train load 2 moves away and the supply power starts to decrease, the system voltage V _l rises, so that the voltage detection value V _in tries to exceed the trip level V _refo . This is detected by the second comparator 18 ₂ , each time the up-down counter 1
9 is counted down one by one, and the number of the TSC capacitors C _{1 to} C _n input to the system bus 1 is reduced by one,
It is possible to prevent the bus voltage V _l from becoming larger than that. As described above, the capacitors C ₁ to
Since the number of inputs of C _n is increased / decreased stepwise, the finish voltage V _l of the system bus 1 is changed to the input level V _refI and the _trip level V _ref.
can be maintained during _refO , and voltage fluctuation due to load fluctuation Δ
V can always be suppressed.

[0021]

According to the present invention, only the voltage fluctuation ΔV due to the load fluctuation can be suppressed without being affected by the power fluctuation. Particularly, since the capacitors C _{1 to} C _n of the TSC are used only for the voltage fluctuation ΔV due to the load fluctuation, if the capacitor capacity is determined according to the load fluctuation of the system, this voltage fluctuation ΔV can be surely achieved. Compared with the conventional equipment that can be suppressed and responds to power fluctuations, it is possible to reduce the installed capacity of capacitors and improve the equipment utilization rate.

[Brief description of drawings]

FIG. 1 is a block diagram showing a voltage fluctuation suppressing device according to an embodiment of the present invention.

2 is a conduction timing diagram of the thyristor and the diode of the capacitor switching circuit in FIG.

3 is a voltage waveform diagram showing a state in which voltage fluctuation is suppressed by opening and closing a phase advancing capacitor in the voltage fluctuation suppressing device shown in FIG.

FIG. 4 is an enlarged waveform diagram showing a portion of the voltage waveform diagram shown in FIG. 3 corresponding to load fluctuations in correspondence with the number of phase-advancing capacitors inserted.

FIG. 5 is a block diagram showing a conventional voltage fluctuation suppressing device using a phase-advancing capacitor.

6 is a bus voltage waveform diagram when voltage fluctuations are suppressed by the device shown in FIG.

[Explanation of symbols]

1 System Bus 2 Variable Load 9 Voltage Detection Circuit 15 Low Pass Filter 17 Control Circuit 3 _{1 to} 3 _n TSC C _{1 to} C _n Phase Advancing Capacitor Th _{1 to} Th ₂ Thyristor

Claims (1)

[Claims] Claim: What is claimed is: 1. In a system for controlling the opening and closing of a plurality of capacitors installed in a power supply system for supplying phase-advancing power, and switching the number of inputs in stages to suppress voltage fluctuations due to load fluctuations in the system. A voltage detection circuit that detects the voltage, a low-pass filter that extracts the long-period component of the detected system voltage and uses it as a voltage reference value, and a level determination circuit that determines the closing level and tripping level of the capacitor corresponding to this voltage reference value. ,
A control device for a voltage fluctuation suppressing device, comprising: a control circuit that compares the above two levels with the detected system voltage and increases or decreases the number of capacitors that are inserted so that the system voltage falls between the two levels. ..