JPH0570043U - Logic data transfer error detection device - Google Patents

Abstract

(57) [Summary] [Purpose] Data transmission and data transfer between receiving devices are normal and abnormal. [Structure] The data transmitted from the data transmission device 1 and the data returned from the data reception device 4 are compared, and normality or abnormality of data transfer between the both devices 1 and 4 is detected based on whether or not both data match. The comparison / detector 5 is provided on the transmission side.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an apparatus for transmitting and receiving logic data (information) in a digital logic circuit application field by a data transmission / reception apparatus, and more particularly to a logic data transfer abnormality detection apparatus.

[0002]

[Prior Art]

 FIG. 3 is a structural explanatory view showing an example of conventional data transfer, and FIG. 4 is an operational explanatory view thereof. In this conventional example, logic data and its access control signal are transferred from the data transmitter 1 through the data bus 2 and the signal line 3, respectively, and the data receiving device 4 receives and reads the data in the period when the access control signal is at the L level. (See Figure 4).

[0003]

[Problems to be solved by the device]

 There is an even or odd parity check method for conventional data transfer abnormality detection. For example, a 1-bit parity code is added to every 8 bits of data (information) to be transferred. In the case of the odd parity check method, "1" is given if the total number of "1" s in the data is even, and "0" if it is odd. If the total number of "1" in the data including "added" and parity bit is 1 bit dropped or 1 bit picked up and becomes an odd number, a data transfer error can be detected, but an even number of errors can be detected. When an error occurs, not only is it impossible to detect a data transfer error, but a parity line for sending a check parity code is necessary. Further, even if the data receiving side can detect a transfer abnormality, a separate mechanism is required to notify the data transmitting side that there is a transfer abnormality, such as re-transferring the data when the transfer abnormality occurs. become.

[0004]

In order to solve the above problems, the device of the present invention sends logic data and its access control signal from a data transmitting device 1 through a data bus and a signal line 3, respectively, as shown in FIG. In the data transfer in which these are received by the data receiving device 4 and read and held, the data bus is the bidirectional transfer data bus 2, and the data transmitted from the data transmitting device 1 and the data bus 2 from the data receiving device 4 are used. The comparison / detector 5 is provided on the transmitting side to compare the data returned through the device and to send data when both data match or do not match, to transfer data normally between the receiving devices 1 and 4, and to detect an abnormality.

[0005]

[Work]

 Logic data and its access control signal are sent from the data transmitter 1 through the bidirectional transfer data bus 2 and the signal line 3, respectively, and sent at the timing of the access control signal (at the H level of the access control signal). Is received by the data receiving device 4, and is read and held internally. The data read inside this is immediately returned as it is to the data transmission side through the bidirectional transfer data bus 2, and is returned at the timing of the access control signal (at the L level of the access control signal) and the data transmission device 1. The comparison / detection device 5 compares the data held in 1), and if the two data do not match, it is detected that there is a data transfer error between both devices 1 and 4.

[0006]

【Example】

 FIG. 1 is an explanatory view of the configuration of one embodiment of the device of the present invention, and FIG. 2 is an explanatory view of its operation. In FIG. 1, 1 is a data transmitter for transmitting logic parallel data and its access control signal, 2 is a bidirectional transfer data bus for transferring parallel data, 3 is a signal line for transferring access control signal, and 4 is parallel data. And the access control signal thereof are received and the parallel data sent from the transmitter 1 is read and held inside at the timing according to the access control signal, and the parallel data read inside is directly transmitted through the bidirectional transfer data bus 2 to the transmitting side. It is a data receiving device for returning to. 5 inputs the returned parallel data and the parallel data held in the data transmission device 1 and compares them, and if the parallel data of both do not match, it is detected that there is an error in data transfer between both devices 1 and 4. It is a comparator / detector that detects which bit line is abnormal by knowing which bit does not match.

In the above configuration, the logic parallel data and its access control signal are transmitted from the data transmitter 1 through the bidirectional transfer data bus 2 and the signal line 3, respectively, and at the timing of the access control signal (at the H level of the access control signal). ) The transmitted parallel data is received by the data receiving device 4, read and held internally. The parallel data read inside is immediately returned as it is to the data transmission side through the bidirectional transfer data bus 2, and is returned at the timing of the access control signal (at the L level of the access control signal) and the data transmission device. The parallel data held in 1 is compared by the comparison / detection device 5, and if both data do not match, it is detected that there is a data transfer error between both devices 1 and 4, and which one of the parallel data is detected. It is possible to detect which bit line has an abnormality by knowing that the bits do not match.

According to the present embodiment described above, the parallel data sent from the data transmitter 1 and the parallel data returned from the data receiver 4 through the bidirectional transfer data bus 2 are compared by the comparator / detector 5. By comparing, it is possible to know the data transfer error between both devices 1 and 4 due to the mismatch of the parallel data of both, and also to know which bit does not match, so to know the error bit line. You can

[0009]

[Effect of the device]

 As described above, according to the present invention, the data transfer device 1 sends the logic data and its access control signal through the data bus and the signal line 3, respectively, and the data receiving device 4 receives and reads and holds them. In the above, the data bus is set as the bidirectional transfer data bus 2, and the data sent from the data transmitter 1 and the data returned from the data receiver 4 through the data bus 2 are compared, and both data match and no match. Since the comparison / detector 5 for detecting data transfer normality / abnormality between the transmission / reception devices 1 and 4 is provided on the transmission side, the data sent from the data transmission device 1 and the data reception device 4 from By comparing with the returned data, it is possible to detect with high accuracy whether the data transfer between the two devices 1 and 4 is normal or abnormal by matching or not matching the data. It is possible to improve the reliability of the stem overall operation.

[Brief description of drawings]

FIG. 1 is a structural explanatory view of an embodiment of the device of the present invention.

FIG. 2 is an explanatory diagram of the operation.

FIG. 3 is a configuration explanatory view showing an example of conventional data transfer.

FIG. 4 is an explanatory diagram of the operation.

[Explanation of symbols]

 1 data transmitter 2 bidirectional transfer data bus 3 signal line 4 data receiver 5 comparator / detector

Claims (1)

[Scope of utility model registration request] 1. A data transfer in which logic data and its access control signal are sent from a data transmitter (1) through a data bus and a signal line (3), respectively, and these are received and read by a data receiver (4). In the above, the data bus is a bidirectional transfer data bus (2), and the data transmitted from the data transmission device (1) is compared with the data returned from the data reception device (4) through the data bus (2). A logic data transfer abnormality detecting device in which a transmitting / receiving device (1, 4) is provided with a comparator / detector (5) for detecting an abnormality in data transfer between the receiving devices (1, 4) when the two data match or mismatch.