JPH0568861B2 - - Google Patents
Info
- Publication number
- JPH0568861B2 JPH0568861B2 JP59174645A JP17464584A JPH0568861B2 JP H0568861 B2 JPH0568861 B2 JP H0568861B2 JP 59174645 A JP59174645 A JP 59174645A JP 17464584 A JP17464584 A JP 17464584A JP H0568861 B2 JPH0568861 B2 JP H0568861B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate electrode
- silicon
- film
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔技術分野〕 本発明はMIS型半導体装置の構造に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to the structure of a MIS type semiconductor device.
従来、MNOS型と称されるシリコン酸化膜及
びシリコン窒化膜とからなる複合膜を絶縁膜とす
るMIS型半導体装置において、シリコン窒化膜と
多結晶シリコンよりなるゲート電極とは、実質的
に同じ形状をしている。第１図に従来のMNOS
半導体装置の断面図を示す。１はシリコン基体、
２はシリコン酸化膜、３はシリコン窒化膜、４は
多結晶シリコンよりなるゲート電極である。
Conventionally, in MIS type semiconductor devices whose insulating film is a composite film of silicon oxide film and silicon nitride film called MNOS type, gate electrodes made of silicon nitride film and polycrystalline silicon have substantially the same shape. doing. Figure 1 shows the conventional MNOS
A cross-sectional view of a semiconductor device is shown. 1 is a silicon substrate;
2 is a silicon oxide film, 3 is a silicon nitride film, and 4 is a gate electrode made of polycrystalline silicon.
ところでゲート電極４と交差してこれと電気的
に絶縁された配線層８を設けるとき、一般的にゲ
ート電極４の表面を酸化して絶縁性被膜で覆うこ
とが行なわれている。しかし従来例に示す構造で
は、ゲート電極４とシリコン窒化膜３の形状が実
質的に同じであるため、ゲート電極４を酸化した
際にゲート電極４の表面に形成されるシリコン酸
化膜５とシリコン基体１の表面上に形成されるシ
リコン酸化膜６との間、すなわちシリコン窒化膜
３の側面部７に間隙ができる。このため配線層８
とゲート電極４間の絶縁耐圧が低下するという欠
点がある。これはシリコン窒化膜３の難酸化性に
よつて起きる現象である。 By the way, when providing a wiring layer 8 that intersects with and is electrically insulated from the gate electrode 4, the surface of the gate electrode 4 is generally oxidized and covered with an insulating film. However, in the structure shown in the conventional example, since the shapes of the gate electrode 4 and the silicon nitride film 3 are substantially the same, the silicon oxide film 5 formed on the surface of the gate electrode 4 and the silicon A gap is formed between the silicon oxide film 6 formed on the surface of the base 1, that is, the side surface portion 7 of the silicon nitride film 3. Therefore, the wiring layer 8
There is a drawback that the dielectric strength between the gate electrode 4 and the gate electrode 4 decreases. This is a phenomenon caused by the oxidation resistance of the silicon nitride film 3.
本発明は上記の点に鑑み提案されたものであ
り、ゲート・配線間耐圧のすぐれたMIS型半導体
装置の提供を目的とする。
The present invention has been proposed in view of the above points, and an object of the present invention is to provide an MIS type semiconductor device with excellent gate-to-wiring breakdown voltage.
本発明は、半導体基体の一主表面上に形成され
た該半導体基体の酸化物を主成分とする第１の絶
縁膜と、該第１の絶縁膜を覆い難酸化性物質より
なる第２絶縁膜と、前記第１及び第２の絶縁膜か
らなる複合膜をゲート絶縁膜とし、多結晶半導体
を主成分とする前記ゲート絶縁膜を覆うゲート電
極とを有するMIS型半導体装置において、
前記第２の絶縁膜の形状が前記ゲート電極の形
状と相似形で、かつ前記ゲート電極の形状より小
さいことを特徴とする。
The present invention provides a first insulating film mainly composed of an oxide of the semiconductor substrate formed on one main surface of the semiconductor substrate, and a second insulating film covering the first insulating film and made of an oxidizable material. A MIS type semiconductor device having a gate insulating film that is a composite film composed of the first and second insulating films, and a gate electrode that covers the gate insulating film mainly composed of a polycrystalline semiconductor. The shape of the insulating film is similar to the shape of the gate electrode and smaller than the shape of the gate electrode.
以下図面を参照して本発明の実施例を説明す
る。第２図は本発明の実施例に係るMIS型半導体
装置の構造を形成するための製造プロセスを示す
図であり、１１はシリコン基体、１２はシリコン
酸化膜、１３はシリコン窒化膜、１４は多結晶シ
リコンによるゲート電極、１５はシリコンゲート
電極１４の酸化によるシリコン酸化膜、１６は基
板１１の酸化によるシリコン酸化膜、１８は配線
層である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a manufacturing process for forming the structure of a MIS type semiconductor device according to an embodiment of the present invention, in which 11 is a silicon substrate, 12 is a silicon oxide film, 13 is a silicon nitride film, and 14 is a multilayer film. A gate electrode made of crystalline silicon, 15 a silicon oxide film formed by oxidizing the silicon gate electrode 14, 16 a silicon oxide film formed by oxidizing the substrate 11, and 18 a wiring layer.
次に実施例の製造プロセスを説明する。まずシ
リコン基体１１の表面に約100Åの厚さのシリコ
ン酸化膜１２を形成し、次いで気相成長法で約
200Åの厚さのシリコン窒化膜１３を形成し、こ
の後多結晶シリコンよりなるゲート電極１４を形
成する（第２図−ａ）。次いでゲート電極１４を
マスクとしてシリコン窒化膜１３をエツチング処
理して整形する。上記のエツチング処理の際、エ
ツチング時間を適当に制御することにより、シリ
コン窒化膜１３はゲート電極１４の端部より例え
ば0.2mm後退した形状とすることができる（第２
図−ｂ）。次いで酸化性雰囲気内で熱処理するこ
とにより、ゲート電極１４の表面にシリコン酸化
膜１５が形成されるとともに、シリコン基体１１
の表面にシリコン酸化膜１６が成長する。この熱
処理により、シリコン窒化膜１３の側面部１７
は、下部から成長するシリコン酸化膜１６と上部
から下方向へ成長するシリコン酸化膜１５により
充填される。このため間隙は埋まり（第２図−
ｃ）、配線層１８とゲート電極１４間の耐圧は向
上する。 Next, the manufacturing process of the example will be explained. First, a silicon oxide film 12 with a thickness of approximately 100 Å is formed on the surface of a silicon substrate 11, and then approximately 100 Å thick is formed by vapor phase growth.
A silicon nitride film 13 with a thickness of 200 Å is formed, and then a gate electrode 14 made of polycrystalline silicon is formed (FIG. 2-a). Next, using the gate electrode 14 as a mask, the silicon nitride film 13 is etched and shaped. By appropriately controlling the etching time during the above etching process, the silicon nitride film 13 can be shaped to be recessed by, for example, 0.2 mm from the end of the gate electrode 14 (the second
Figure-b). Next, by heat treatment in an oxidizing atmosphere, a silicon oxide film 15 is formed on the surface of the gate electrode 14, and the silicon substrate 11 is
A silicon oxide film 16 grows on the surface. By this heat treatment, the side surface 17 of the silicon nitride film 13 is
is filled with a silicon oxide film 16 growing from the bottom and a silicon oxide film 15 growing downward from the top. Therefore, the gap is filled (Fig. 2-
c) The breakdown voltage between the wiring layer 18 and the gate electrode 14 is improved.
なお実施例ではMIS型キヤパシタの構造を示し
たが、ゲート電極１４の側面に隣接してシリコン
基体１１内にソース、ドレイン拡散層を有する
MIS型トランジスタに対しても本発明を適用でき
る事はいうまでもない。 Note that although the structure of the MIS type capacitor is shown in the embodiment, source and drain diffusion layers are provided in the silicon substrate 11 adjacent to the side surfaces of the gate electrode 14.
It goes without saying that the present invention can also be applied to MIS type transistors.
以上説明したように本発明によれば、難酸化性
のシリコン窒化膜の側部が酸化膜で覆われるの
で、配線層とゲート電極間の耐圧が良好で半導体
装置の信頼性が向上する。
As described above, according to the present invention, the sides of the silicon nitride film, which is difficult to oxidize, are covered with an oxide film, so that the withstand voltage between the wiring layer and the gate electrode is good, and the reliability of the semiconductor device is improved.
第１図は従来例に係る半導体装置の概略断面
図、第２図は本発明の実施例に係る半導体装置の
構造を形成するために製造プロセスを示す概略断
面図である。
１，１１……半導体基体、２，１２……シリコ
ン酸化膜、３，１３……シリコン窒化膜、４，１
４……多結晶シリコンによるゲート電極、５，１
５……ゲート電極の表面に形成されるシリコン酸
化膜、６，１６……シリコン基体表面に形成され
るシリコン酸化膜、７，１７……シリコン窒化膜
の側面部、８，１８……配線層。
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor device, and FIG. 2 is a schematic cross-sectional view showing a manufacturing process for forming the structure of a semiconductor device according to an embodiment of the present invention. 1, 11... Semiconductor substrate, 2, 12... Silicon oxide film, 3, 13... Silicon nitride film, 4, 1
4...Gate electrode made of polycrystalline silicon, 5,1
5... Silicon oxide film formed on the surface of the gate electrode, 6, 16... Silicon oxide film formed on the surface of the silicon substrate, 7, 17... Side part of silicon nitride film, 8, 18... Wiring layer .
Claims (1)
た該半導体基体の酸化物を主成分とする第１の絶
縁膜および該第１の絶縁膜を覆いシリコン窒化膜
よりなる第２の絶縁膜からなる複合絶縁膜と、こ
の複合絶縁膜を誘電膜としてその上に形成され多
結晶半導体を主成分とするキヤパシタ電極と、該
キヤパシタ電極を酸化して得られた絶縁膜で電気
的に絶縁された状態で該キヤパシタ電極上に延在
して形成された配線層とを有し、前記第２の絶縁
膜の形状が前記キヤパシタ電極の形状より小さい
ことを特徴とするMIS型半導体装置。1. A first insulating film mainly composed of an oxide of the semiconductor substrate formed on one main surface of a semiconductor substrate of one conductivity type, and a second insulating film made of a silicon nitride film covering the first insulating film. A capacitor electrode formed on the composite insulating film as a dielectric film and mainly composed of a polycrystalline semiconductor, and an insulating film obtained by oxidizing the capacitor electrode are electrically insulated. and a wiring layer formed extending over the capacitor electrode in a state where the second insulating film has a shape smaller than the shape of the capacitor electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17464584A JPS6151976A (en) | 1984-08-22 | 1984-08-22 | Mis type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17464584A JPS6151976A (en) | 1984-08-22 | 1984-08-22 | Mis type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6151976A JPS6151976A (en) | 1986-03-14 |
| JPH0568861B2 true JPH0568861B2 (en) | 1993-09-29 |
Family
ID=15982212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17464584A Granted JPS6151976A (en) | 1984-08-22 | 1984-08-22 | Mis type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6151976A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2569365B2 (en) * | 1989-04-03 | 1997-01-08 | 山口日本電気株式会社 | Method for manufacturing semiconductor integrated circuit device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55157264A (en) * | 1979-05-25 | 1980-12-06 | Fujitsu Ltd | Manufacturing method for semiconductor device |
-
1984
- 1984-08-22 JP JP17464584A patent/JPS6151976A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55157264A (en) * | 1979-05-25 | 1980-12-06 | Fujitsu Ltd | Manufacturing method for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6151976A (en) | 1986-03-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |