JPH056857A - Formation method of multilayer resist layer - Google Patents

Abstract

PURPOSE:To easily obtain an asymmetric resist pattern by a method wherein a first latent image formed in a first resist layer and second latent image formed in a second resist layer are exposed to light in an offset relationship, they are developed at a time and a resist pattern by a multilayer resist layer is formed. CONSTITUTION:A first resist layer 2 is formed on a semiconductor substrate 1; a first latent image 2b is formed in the first resist layer 2. Then, a second resist layer 3 is formed on the first resist layer 2; a second latent image 3b is formed in the second resist layer 3. The second latent image 3b constitutes an offset relationship with the first latent image 2b. Then, a developing treatment is executed in order to remove both of the latent images; a multilayer resist layer provided with desired patterns 2a, 3a is formed on the semiconductor substrate 1. Thereby, the cross-sectional shape of a resist pattern can be set freely by setting the formation condition of the individual latent images. As a result, an asymmetric resist pattern can be obtained easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-layered resist layer used in the process of manufacturing a semiconductor device, and more particularly to a method for forming a pattern having an offset relationship with each other among a plurality of resist layers. Is.

[0002]

2. Description of the Related Art In a conventional method for manufacturing a semiconductor device,
A method of forming a T-shaped gate electrode on a semiconductor substrate using a lift-off technique is known (Japanese Patent Publication No. 62-1).
(See Japanese Patent No. 6534). In this technique, a first electron beam resist film and a second electron beam resist film having a higher sensitivity to an electron beam are provided, and both the resist films are subjected to an electron beam exposure process and a development process so that they are aligned with each other. There are large and small openings. In order to install a Schottky junction gate electrode at an offset position on a recessed surface of a semiconductor substrate using this technique, it is necessary to perform the above-mentioned exposure and development processing after performing recess processing on the surface of the semiconductor substrate. As a result, the recessed surface is in contact with the resist, resist developer, resist stripper, cleaning water, atmosphere, etc. for a long period of time, resulting in unnecessary etching, oxidation, increase of surface defects, influence of impurities, etc. Is prone to deterioration.

As another conventional technique, a first resist film is provided on a semiconductor substrate and exposed, and then a second resist film is formed.
After the second resist film is exposed,
A technique for developing both resist films at once has been introduced (see Japanese Patent Publication No. 62-20689). This technique aims to improve the edge roughness of the formed pattern, and does not suggest a technique relating to offset exposure.

In general, regardless of whether the resist layer is a single layer or a multilayer, when exposure and development are performed once, a finished opening pattern can only have a bilaterally symmetrical sectional shape. In order to obtain an asymmetric pattern, there is a method of exposing the resist layer from an oblique direction in the case of a single resist layer, or a method of performing the process after forming the resist pattern from the oblique direction in the case of vapor deposition, for example. However, there are major restrictions on the finished shape and the direction in which the shape can be obtained. In the case of a multi-layer resist layer, it is necessary to carry out the same method as in the case of a single-layer resist layer. In addition, 1
When the exposure and development of the first layer are performed and then the exposure and development of the second layer are performed thereon, an asymmetric cross-sectional shape of the resist pattern is obtained by the alignment. However, the process is complicated, and depending on the surface accuracy (unevenness) of the first resist layer, coating unevenness or the like occurs in the second resist layer, resulting in poor pattern accuracy. Furthermore, it is not possible to form a resist layer having an overhang.

[0005]

The present invention has been made in consideration of the above problems of various conventional techniques. For example, in the manufacturing process of an FET having a T-shaped gate electrode at an offset position on a recessed surface. It is an object of the present invention to provide a method of forming a resist layer that can be used, and more generally, can easily form various resist patterns having asymmetric cross-sectional shapes.

[0006]

A method of forming a multi-layered resist layer according to the present invention comprises applying a first resist layer on a semiconductor substrate, exposing the first resist layer, and then exposing the first resist layer to the first resist layer. Forming the first latent image, and applying a second resist layer on the first resist layer to form a second resist layer having a second offset relationship with the first latent image. Exposing the second resist layer to form a latent image, and then the first latent image portion of the first resist layer and the second latent image portion of the second resist layer. And a developing step for removing the above-mentioned substances at once.

In the method for forming a multi-layered resist layer of the present invention, a third resist layer having a higher exposure sensitivity than that of the second resist layer is further coated on the second resist layer, and then the second resist layer is formed. A second latent image and a third latent image having an offset relationship with the first latent image are formed on the resist layer and the third resist layer, and the first, second, and third latent image portions are formed. It is characterized in that it is provided with a developing step of removing at once.

[0008]

In the present invention, the first latent image provided on the first resist layer and the second latent image provided on the second resist layer are exposed in an offset relationship, and these are developed at a time and multilayered. Since the resist pattern of the resist layer is formed, the cross-sectional shape of the resist pattern can be freely set by setting the conditions for forming each latent image, so that an asymmetric resist pattern can be easily obtained. Therefore, by using this resist pattern, the semiconductor substrate can be recessed and the gate electrode can be installed at an offset position on the recessed surface, and the processed portion is exposed to the development processing after the recessing. It is possible to manufacture an FET having better characteristics than an element.

[0009]

The method for forming a multi-layered resist layer of the present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a schematic configuration diagram of an FET manufactured by using the method of the present invention. 2, FIG. 3, and FIG. 4 are process explanatory diagrams of the first embodiment of the method of the present invention, and FIG. 5, FIG. 6 and FIG. 7 are process explanatory diagrams of the second embodiment of the method of the present invention. 8 and 9 are block diagrams of FETs of different types manufactured by using the method of the present invention.

The first embodiment shows a method of forming two resist layers on a semiconductor substrate. That is, the first resist layer 2 having the pattern 2a and the second resist layer 3 having the pattern 3a are provided on the semiconductor substrate 1 (FIG. 4). In order to form such a multi-layered resist layer, first, a semiconductor substrate 1 having a thickness of 30 is formed.
A first resist layer 2 having a thickness of about 00Å is formed, and a first latent image 2b is formed on the first resist layer 2 (FIG. 2). Next, a second resist layer 3 having a thickness of about 3000Å is formed on the first resist layer 2, and a second latent image 3b is formed on the second resist layer 3. The second latent image 3b has an offset relationship with the first latent image 2b (FIG. 3). Next, a development process is performed to remove both latent images, and a multilayer resist layer having desired patterns 2a and 3a is formed on the semiconductor substrate 1 (FIG. 4).

The semiconductor substrate 1 is a compound semiconductor (GaAs)
The source electrode S and the drain electrode D are ohmic-connected to the substrate body H of the substrate body H. The substrate body H is composed of a base 1a made of semi-insulating GaAs, a buffer layer 1b formed on the base 1a, and n. Operating layer 1 including layer 1c and n ⁺ layer 1d
e. Each drawing shows a part of a wafer provided with a large number of such combinations.

As the first resist layer 2, a low-sensitivity EB (electron beam) resist (OEBR-1000 manufactured by Tokyo Ohka Kogyo Co., Ltd.) was spin-coated (resist viscosity 75 cp, 3000 rpm).
Second) and then apply a pre-bake (200 ° C, 20 minutes)
Is formed. Then, an electron beam 4 is applied to the resist layer 2 so as to form a first latent image 2b having an exposure width W ₁ corresponding to the recess length, and the resist layer 2 is exposed.

The second resist layer 3 is also formed by spin-coating a low-sensitivity EB resist (OEBR-1000 manufactured by Tokyo Ohka Co., Ltd.) (same as above), and then applying a pre-bake (17).
It is formed at 0 ° C. for 20 minutes). Then, the resist layer 3 has a second offset value that is offset from the first latent image 2b and has an exposure width W ₂ smaller than the exposure width W ₁ .
The electron beam 5 is applied so as to form the latent image 3b, and the resist layer 3 is exposed. Note that X is the exposure width W ₁ and the exposure width W
Indicates the offset amount of ₂ .

For the development processing, the first latent image 2b and the second latent image 3 are formed by using a developing solution composed of a mixed solution of MIBK (methyl isobutyl ketone) and IPA (isopropyl alcohol).
b is removed, and a pattern 2a is formed on the first resist layer 2 and a pattern 3a is formed on the second resist layer 3. still,
The composition ratio of the mixed solution is determined by the exposure conditions, as is well known.

Since the pattern 2a of the first resist layer 2 has a width W ₁ corresponding to the recess length, the semiconductor substrate 1 exposed by this pattern can be recessed using this pattern. it can. After this recessing process, it is not necessary to perform processing for forming a resist layer on the processed surface, so that deterioration of the processed surface can be prevented. Also,
Since the pattern 3a of the second resist layer 3 is formed in an offset relationship with the pattern 2a, this pattern 3a
It is possible to form a gate electrode at an offset position on the recessed surface of the semiconductor substrate after the recess processing by utilizing.

Next, a second embodiment will be described with reference to the process charts of FIGS. 5, 6 and 7. The second embodiment shows a method of forming three resist layers on a semiconductor substrate. That is, the pattern 20a is formed on the semiconductor substrate 10.
A first resist layer 20 having a pattern, a second resist layer 30 having a pattern 30a, and a third resist layer 40 having a pattern 40a (FIG. 7).

In order to form such a multi-layered resist layer, first, a first resist layer 20 having a thickness of about 3000 Å is formed on the semiconductor substrate 10, and a first latent layer is formed on the first resist layer 20. The image 20b is formed (FIG. 5). Next, a second resist layer 30 having a thickness of about 3000Å is formed on the first resist layer 20, and a third resist layer having a thickness of about 5000Å is further formed on the second resist layer 20. Four
0, and the second latent image 3 is formed on the second resist layer 30.
0b is formed, and a third latent image 40b is formed on the third resist layer 40. Since the exposure sensitivity of the resist forming the third resist layer is higher than the exposure sensitivity of the resist forming the second resist layer, the width of the latent image formed by the application of the electron beam. Is larger in the third latent image than in the second latent image. The second latent image 30b and the third latent image 40b are offset from the first latent image 20b (FIG. 6). Next, a development process is performed to remove all the latent images at one time, and a multilayer resist layer having desired patterns 20a, 30a, 40a is formed on the semiconductor substrate 10 (FIG. 7).

The semiconductor substrate 10 is a compound semiconductor (GaA).
The source electrode S and the drain electrode D are ohmic-connected to the substrate body H of s), and the substrate body H is made of semi-insulating GaAs.
The base 10a is made of, the buffer layer 10b formed on the base 10a, and the operation layer 10e including the n layer 10c and the n ⁺ layer 10d. It should be noted that each of the drawings shows only a part of the wafer provided with a large number of such combinations.

The first resist layer 20 is a low-sensitivity EB (electron beam) resist (OEBR-1000 manufactured by Tokyo Ohka).
Was spin-coated (resist viscosity 75 cp, 3000 revolutions / second) and applied, and then pre-baked (200 ° C., 20
Min) is formed. Then, this resist layer 20
To the resist layer 2 by applying an electron beam EB so as to form a first latent image 20b having an exposure width W ₁ corresponding to the recess length.
0 is exposed.

The second resist layer 30 is also formed by spin-coating a low-sensitivity EB resist (OEBR-1000 manufactured by Tokyo Ohka Co., Ltd.) (same as above), and then applying a pre-bake (17).
It is formed at 0 ° C. for 20 minutes). In addition, a high-sensitivity EB resist (Toray E
BR-9) is applied by spin coating (resist viscosity is slightly high, 3000 revolutions / second), and then prebaked (200 ° C., 20 minutes). After that, the resist layer 30 and the resist layer 40 respectively have a second latent image having an offset relationship with respect to the first latent image 20b and having an exposure width W ₂ and an exposure width W ₃ smaller than the exposure width W _1. The electron beam EB is applied so as to form the image 30b and the third latent image 40b, and the resist layer 30 and the resist layer 40 are exposed at the same time. Incidentally, X represents the offset amount between the exposure width W ₁ , the exposure width W ₂ and the exposure width W ₃ .

For the development processing, a first latent image 20b, a second latent image 30b and a third latent image are formed by using a developing solution composed of a mixed solution of MIBK (methyl isobutyl ketone) and IPA (isopropyl alcohol). 40b is removed, the pattern 20a is formed on the first resist layer 20, and the second resist layer 30 is formed.
Then, a pattern 30a and a pattern 40a are formed on the third resist layer 40, respectively. The composition ratio of the mixed solution is determined by the exposure conditions, as is well known.

FIG. 1 shows a schematic structure of a MESFET formed by using the multi-layered resist layer manufactured by the second embodiment. First resist layer 2 of semiconductor substrate 10 having a multilayer resist layer having the pattern of FIG.
The recess processing is performed on the portion not covered by 0. This recess processing is performed so that the processed surface exceeds the n ⁺ layer of the operating layer 10e to expose the n layer 10c. For this recess processing, for example, chemical etching in which the etchant is phosphoric acid and hydrogen peroxide is used.
Further, the gate electrode G is formed in a T-shape at a portion near the source electrode S on the recessed surface after performing the recess processing. This can be formed by vapor-depositing the electrode metal including the recessed portion on the multilayer resist layer of FIG. 7 and then lifting off the resist layer. Here, the pattern 30a of the second resist layer 30
Sectional width W ₂ of chosen so as to define the gate length of the gate electrode G to reduce the junction capacitance of the MESFET, the width W ₃ of the third resist layer 40a is the gate electrode G to reduce the series resistance of the MESFET It is selected to increase the area.

FIG. 8 shows a configuration diagram of the second FET. The semiconductor substrate 10 has a mesa portion 10f,
An n-type operating layer 10g and an n ⁺ -type operating layer 10h are provided in the mesa portion. Recess processing is n-type operating layer 10g
Of the n-type operating layer 10g
Formed to control the thickness of the. A T-shaped gate electrode G is formed on a portion of the recessed surface 10i near the source electrode S.

FIG. 9 shows a third FET (FE of HEMT structure).
It is a block diagram of (T). The semiconductor substrate 10 is provided with a mesa portion 10j, and this mesa portion has ap ⁻ -type GaA.
s semiconductor layer 10k and n-type AlGaAs semiconductor layer 1
0l and an n ⁺ type GaAs semiconductor layer 10m. The recess processing is performed so that the surface of the n-type AlGaAs semiconductor layer 101 is exposed and the thickness of the n-type AlGaAs semiconductor layer 101 is controlled. A T-shaped gate electrode G is formed on a portion of the recessed surface 10n near the source electrode S.

[0025]

According to the present invention, the first latent image provided on the first resist layer and the second latent image provided on the second resist layer are exposed in an offset relationship, and these are developed at a time. Since the resist pattern of the multi-layered resist layer is formed by this method, the cross-sectional shape of the resist pattern can be freely set by setting the conditions for forming each latent image, so that an asymmetric resist pattern can be easily obtained. Therefore, by using this resist pattern, the semiconductor substrate can be recessed and the gate electrode can be installed at an offset position on the recessed surface, and the processed portion is exposed to the development processing after the recessing. This can contribute to the manufacture of FETs with better characteristics than devices.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first type FET manufactured by using the method of the present invention.

FIG. 2 is a process explanatory view of the first embodiment of the method of the present invention.

FIG. 3 is a process explanatory view of the first embodiment of the method of the present invention.

FIG. 4 is a process explanatory view of the first embodiment of the method of the present invention.

FIG. 5 is a process explanatory view of the second embodiment of the method of the present invention.

FIG. 6 is a process explanatory view of the second embodiment of the method of the present invention.

FIG. 7 is a process explanatory view of the second embodiment of the method of the present invention.

FIG. 8 is a configuration diagram of a second type FET manufactured by using the method of the present invention.

FIG. 9 is a configuration diagram of a third type FET manufactured by using the method of the present invention.

Claims (3)

[Claims] 1. A step of applying a first resist layer on a semiconductor substrate, exposing the first resist layer to form a first latent image on the first resist layer, and the first resist. Exposing a second resist layer on the layer so as to form a second latent image on the second resist layer in an offset relationship with the first latent image. And a developing step of removing the first latent image portion of the first resist layer and the second latent image portion of the second resist layer at a time. Forming method. 2. The second latent image is overlapped with the first latent image and has a width narrower than that of the first latent image, and the first resist layer is formed after the developing step. The method for forming a multilayer resist layer according to claim 1, wherein the second resist layer is configured to hang over. 3. A step of applying a first resist layer on a semiconductor substrate, exposing the first resist layer to form a first latent image on the first resist layer, and the first resist. A second resist layer and a third resist layer having a higher exposure sensitivity than the second resist layer are superposed on the layer, and the first resist is applied to the second resist layer and the third resist layer. A step of simultaneously exposing the second resist layer and the third resist layer so as to form a second latent image and a third latent image having an offset relationship with respect to the latent image, and then the first latent image. The first latent image portion of the resist layer and the second latent image portion of the second resist layer.
A developing step of removing the latent image portion and the third latent image of the third resist layer at one time.