JPH0568137B2 - - Google Patents

Info

Publication number
JPH0568137B2
JPH0568137B2 JP58247194A JP24719483A JPH0568137B2 JP H0568137 B2 JPH0568137 B2 JP H0568137B2 JP 58247194 A JP58247194 A JP 58247194A JP 24719483 A JP24719483 A JP 24719483A JP H0568137 B2 JPH0568137 B2 JP H0568137B2
Authority
JP
Japan
Prior art keywords
phase
output
circuit
clock
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58247194A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60141043A (ja
Inventor
Takeo Kusama
Masato Hirai
Takeshi Shimanuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58247194A priority Critical patent/JPS60141043A/ja
Publication of JPS60141043A publication Critical patent/JPS60141043A/ja
Publication of JPH0568137B2 publication Critical patent/JPH0568137B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58247194A 1983-12-28 1983-12-28 タイミング信号再生方式 Granted JPS60141043A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58247194A JPS60141043A (ja) 1983-12-28 1983-12-28 タイミング信号再生方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58247194A JPS60141043A (ja) 1983-12-28 1983-12-28 タイミング信号再生方式

Publications (2)

Publication Number Publication Date
JPS60141043A JPS60141043A (ja) 1985-07-26
JPH0568137B2 true JPH0568137B2 (enrdf_load_stackoverflow) 1993-09-28

Family

ID=17159841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58247194A Granted JPS60141043A (ja) 1983-12-28 1983-12-28 タイミング信号再生方式

Country Status (1)

Country Link
JP (1) JPS60141043A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62101152A (ja) * 1985-10-29 1987-05-11 Hitachi Denshi Ltd タイミング信号再生方式

Also Published As

Publication number Publication date
JPS60141043A (ja) 1985-07-26

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