JPH0568064A - Demodulator - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency of a radio line by implementing correlation detection and means phase estimate to a fixed code data string comprising burst signals thereby eliminating the need for a carrier recovery code. CONSTITUTION:A signal inputted to a reception signal input terminal 1 and signals from an oscillator 4 are detected by phase detectors 2-1, 2-2, from which 2-series of base band signals are obtained and they are inputted to a modulation phase estimate device 8 through low pass filters 5-1, 5-2 and A/D converters 6-1, 6-2. The output of the estimate device 8 is divided into two, the one is inputted to a clock regeneration circuit 10 and the other is inputted to a synchronization detection circuit 11 via a delay device 9. Then a mean phase of a fixed code data string of a reception burst signal is estimated to recover the fixed code data string and it is compared with a fixed data code string reserved in advance at a receiver side. Then a mean phase corrected based on the result of comparison is subtracted from a modulation phase estimate signal to identify data and the mean phase is corrected by using a recovered phase obtained from a phase corresponding to the identification output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation device for efficiently demodulating a received signal in a communication system for transmitting digital information in bursts.

[0002]

2. Description of the Related Art In a communication system for transmitting digital information in bursts, a carrier recovery code for synchronous detection is generally added to the head of a burst signal. This code is a waste signal that does not contribute to information transmission, and is preferably as short as possible.

However, when error correction with a high coding gain is applied to effectively use the signal power of the satellite repeater as in the mobile satellite communication system, the received C / N input to the demodulator is It goes low and requires a long preamble. In particular, in a random access line of mobile satellite communication, which has a short signal length and is transmitted intermittently, there is a drawback that the proportion of the preamble in one burst signal is large and the transmission efficiency is significantly reduced.

[0004]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks and performs correlation detection and average phase estimation of a fixed code data sequence forming a burst signal, thereby eliminating the need for carrier recovery code and improving the transmission efficiency of a wireless line. The purpose is to improve.

[0005]

The feature of the present invention for achieving the above object is that demodulation by synchronous detection of a communication system for transmitting a burst signal composed of a fixed code data sequence and an information data sequence by digital phase modulation. In the device,
Means for estimating an average phase value from a modulation phase estimation signal, which is a relative modulation phase value of a received signal wave, of a fixed code data string of a received burst signal, and reproducing the fixed code data string based on the average phase value. Then, the fixed code data sequence prepared in advance on the receiving side is compared with the reproduced fixed code data sequence, and the means for correcting the average phase value based on the comparison result and the corrected average phase value Means for performing data discrimination by subtracting from the modulation phase estimation signal of data, and means for correcting the average phase value with a reproduction phase value obtained by subtracting a phase value corresponding to the discrimination output from the modulation phase estimation signal In a demodulator having.

[0006]

EXAMPLE A two-phase PSK is shown here for simplicity of explanation.
Target. As is well known, the modulation phase of a two-phase PSK wave is expressed by the following equation. φ (+) = πD (t) (D (t) is modulation data of 1 or 0)

FIG. 2 shows an example of the frame structure of a burst signal. The burst signal is composed of a fixed code data string and an information data string as shown in FIG. In the following description, the number of data in the fixed code data sequence is m, the data value is W _j (j = 1 to m), and the phase value is p _j.
(J = 1 to m). The number of information data is n.

FIG. 1 is a block diagram of a demodulation device according to the present invention. 1 is a reception signal input terminal, 2-1 and 2-2
Is a phase detector, 3 is a π / 2 phase shifter, 4 oscillators, 5-1 and
5-2 is a low-pass filter, 6-1 and 6-2 are analog / digital (A / D) converters, 7 is a timing clock (frequency of several times the clock frequency) input terminal, 8 is a modulation phase estimator, 9 is a delay device, 10 is a clock recovery circuit, 1
Reference numeral 1 is a synchronous detection circuit, 12 is an output terminal (reproduction data output terminal), and the present invention relates to this circuit 11.

In FIG. 1, the signal input to the terminal 1 is detected by the respective signals of the oscillator 4 by the phase detectors 2-1 and 2-2 to obtain two series of baseband signals. The signals of these two series are supplied to the low-pass filters 5-1 and 5-2 and the A / D converter 6-.
1, 6-2, and is input to the modulation phase estimator 8.
The output of the estimator 8 is branched into two, one of which is input to the clock reproduction circuit 10 to reproduce the clock signal. The other is input to the synchronous detection circuit 11 via the delay device 9.

Now, the modulation phase estimation signal input to the synchronous detection circuit 11 is expressed by the following equation. When a received signal exists: α (t) = φ (t) + θ + n (t) φ (t); modulation phase θ; initial phase (arbitrary value of [0,2π]) n (t); due to noise When there is no received signal: α (t) = n (t)

[0011] It should be noted that the phase signal α (t at time t _{k + 1
Let k + 1} ) be α _{k + 1} to simplify the following description.

The operation of the synchronous detection circuit of FIG. 1 will be described below. The synchronous detection circuit relates to (1) operation related to correlation detection of a fixed code data sequence and estimation and correction of an average phase from the fixed data sequence, and (2) reproduction of information data using the average phase estimated from the fixed data sequence. It is divided into motions.

(A) First, the operation (1) will be described. (A) Receive the α _k phase signal from the modulation phase estimator of FIG. (B) Each phase value p ₁ of the fixed code is subtracted from the m modulation phase estimation signals of (α _k , α _k-1 , ..., α _{k-n + 1} ).
(Subscript minus indicates past time) That is, the calculation of q _j = α _{k-j + 1} −p _j (j = 1 to m) is performed. (C) The averaged phase signal β is obtained by averaging q _j (j = 1 to m) of the subtraction results over m. That is, β =
Perform (q ₁ + ... + q _n ) / m. (D) The above β is subtracted from each of the m phase signals of (α _K , α _K-1 , ..., α _{K-n + 1} ). "1" of the data from the subtraction result, "0" is determined, comparing this with the reproduction data value, and a fixed code data values W _j which is previously easily. As a result of this comparison, if the number of mismatches is smaller than a certain number, it is determined as "detected", and if it is larger than a certain number, it is determined as "not detected". (Correlation detection) (e) When the above detection result is “non-detection”, the process returns to (a) and the operations of (a), (b), (c), and (d) are repeated. (The subscript of α is changed from k to k + 1) When the above detection result is "detection", the operation proceeds to the next (f). (F) For the mismatched data with the fixed code data value W _j (j = 1 to m), the polarity of q _j of the corresponding number is inverted, and the average phase is again obtained from the following equation. β = (q ₁ + ·· + q _n ) / m (g) The corrected phase signal q _j is averaged over m to obtain a corrected average phase β.

As described above, the detection of the fixed code data sequence of the received signal and the average phase value thereof can be obtained.

(B) Next, the operation of (2) will be described.
The phase value of the last data of the fixed code data string from the modulation phase estimator is α _a, and the z-th (z
The phase value of = 1 to n) is α _{a + z} . In addition, the time transition of the average phase value in the information data string is β _z-1 . Here, β ₀ when z = 1 is equal to β. (A) From the modulation phase estimator of FIG. 1, α _{a + z} (z = 1 ...
Information data) phase signal. (B) The average phase value β _z-1 is subtracted from the phase signal α _{a + z} . Let the result be γ _z . (C) Based on the phase value of γ _z , “1” of the data,
Judgment of "0" is performed. (D) Based on this determination result, the following calculation is performed on α _{a + z} . In the case of “1”, η _z = α _{a + z} −π In the case of “0”, η _z = α _{a + z} (e) The phase range of η _z is determined based on the average phase value, Based on this result, the weighting factors w ₁ and w _z are added to correct the average phase. That is, the following equation is obtained. When η _z −β _z-1 <ξ, β _z = (1-w ₁ ) β _z-1 + w ₁ η _z η _z −β _z-1 > ξ, β _z = (1-w _z ) β _{z -1} + w _z η _z (f) It is determined whether z is n, and when z <n, the operation from (a) is repeated. (Increase the value of the subscript z of α by 1) When z = n, this operation ends.

As explained above, (a), (a),
The information data can be reproduced by the operation of (C), (D),
By the operation of (e), the influence of the phase having a large deviation from the average phase due to noise can be reduced.

FIG. 3 shows an embodiment of the present invention. In this embodiment, in order to simplify the description, a case where the number of fixed code data is 5 will be described.

In FIG. 3, 1 is an input terminal, 2 is a shift register, 3 is a memory value of phase information, 4-1 to 4-5.
Is a subtracter, 5-1 to 5-5 is a delay device, and 6-1 to 6-
5 is a subtracter, 7-1 to 7-5 are discriminators, and 8-1 to 8
-5 is a comparator, 9 is a fixed code data memory value, 10 is a fixed code data detector, 11-1 to 11-5 are adders, 12 is a fixed code data averaging circuit, 13 is a gate, and 14 is Delay device, 15 is an integrator for information data,
16 is a switch, 17 is a delay device, 18 is a subtractor, 19 is a discriminator, 20 is a delay device, 21 is a modulation phase generator, 22 is a subtractor, 23 is a comparator, 24 is a weighting factor generator, 2
Reference numeral 5 is a multiplier, 26 is a switch, and 27 is an output terminal.
In the initial state in which the circuit of FIG. 3 operates (state before fixed code data is detected), the switches 16 and 2 are
6 is in an off state, and the gate 13 is in an off state.

First, the operation for fixed code data will be described.

The phase signal from the modulation phase estimator shown in FIG. 1 is input to the terminal 1 and is branched into two. One is input to the shift register 2 and the other is input to the switch 16. The phase signal to the shift register 2 is subtracted from each value of the memory circuit 3 which holds the phase value of the fixed code data by each subtractor of 4-1 to 4-5, and 11-1 to 11-5. The data is input to the averaging circuit 12 via each adder and the average of five data is calculated. Since the gate 13 is in the OFF state when the fixed code data detector 10 does not detect the fixed code data, the adders 11-1 to 11-5 from the gates are in the OFF state.
The added value to is 0. The output of this averaging circuit 12 is
The phase value of each stage of the shift register 2 is delayed by the delay unit 5-1.
Signal delayed by 5 to 5 and 6-1 to 6 of each subtractor
Subtract at -5. For each of the subtracted values, "1" and "0" of the data are judged by the discriminators 7-1 to 7-5. The outputs of the discriminator are compared with the respective values of the fixed code data in the memory circuit 9 by the comparators 8-1 to 8-5, and are input to the fixed code data detector 10 and the gate 13. The fixed code data detector 10 counts the number of mismatches between the outputs of the comparators 8-1 to 8-5, judges that the count value is larger than a certain number, and judges that it is “non-detection”, and inputs it. The phase signals from the terminal 1 are sequentially input, and the operation is repeated until the detector 10 determines that they are detected. Further, when the count value of the number of mismatches is smaller than a specific number, it is determined as “detection”, the gate 13 is turned on, the switch 16 is turned on, and the switch 26 is turned on via the delay device 14. When the gate 13 is turned on, the output values of the comparators 8-1 to 8-5 are added to the adders of 11-1 to 11-5 to invert the polarity of the signal corresponding to the mismatch. With the corrected signal, the circuit 12 again averages five pieces of data.

Next, the operation for information data will be described.

When the fixed code data detector determines "detection", the switch 16 is turned on and the modulated phase estimation signal of the information data passes through the switch 16 and is input to the delay unit 17. The phase signal passed through the delay unit 17 is branched into two, one of which is input to the subtractor 18 and the other of which is input to the delay unit 20. The subtractor 18 subtracts the output signal of the delay unit 17 from the integrator output signal that modifies the output of the averaging circuit 12 with the phase signal of the information data. The output of the subtractor 18 is the discriminator 19
The data "1" and "0" are discriminated by and the reproduced data is output to the output terminal 27. Further, the output of the discriminator 19 is input to the modulation phase generator 21, and the phase signal passing through the delay device 20 is subtracted by the subtractor 22 with the phase value corresponding to the reproduction data. The output of the subtractor 22 is branched into two, one of which is the comparator 2
The weighting coefficient generator 24 generates a weighting coefficient according to the comparison output value. The other signal of the subtractor 22 is multiplied by the output of the weighting coefficient generator 24 by the multiplier 25 and input to the integrator 15 via the switch 26. The integrator 15 integrates the output of the multiplier 25 to generate an average phase signal for the next information data. Reproduced data can be obtained by repeatedly performing the above-described operation for information data that is sequentially input.

[0023]

As described above, according to the present invention, it is possible to obtain the phase signal required to obtain the reproduction data from the fixed code data string, and the phase signal of the information data having a large phase error due to noise is weighted by the weighting coefficient. Since it is weighted by, the influence is small, and stable operation can be expected for a line with a low carrier power to noise power ratio.

[Brief description of drawings]

FIG. 1 shows a configuration of a demodulation device according to the present invention.

FIG. 2 shows a frame configuration example of a burst signal.

FIG. 3 shows a configuration of a synchronous detection circuit in FIG.

[Explanation of symbols]

 1 Input Terminal 2-1, 2-2 Phase Detector 3 π / 2 Phase Shifter 4 Oscillator 5-1 and 5-2 Low-pass Filter 6-1, 6-2 A / D Converter 7 Timing Clock Input Terminal 8 Modulation phase estimator 9 Delay device 10 Clock recovery circuit 11 Synchronous detection circuit

Claims (2)

[Claims] 1. A demodulator by synchronous detection of a communication system for transmitting a burst signal composed of a fixed code data string and an information data string by digital phase modulation, wherein a fixed code data string of a received burst signal is A means for estimating an average phase value from a modulation phase estimation signal which is a relative modulation phase value, and reproducing a fixed code data string with the average phase value as a reference, and a fixed code data string prepared in advance on the receiving side. And the reproduced fixed code data sequence are compared, and the means for correcting the average phase value based on the comparison result, and the corrected average phase value are subtracted from the modulation phase estimation signal of the information data to identify the data. And means for correcting the average phase value with a reproduction phase value obtained by subtracting the phase value corresponding to the discrimination output from the modulation phase estimation signal. Demodulation and wherein the. 2. A phase value obtained by a difference between a reproduction phase value and an average phase value is determined as a phase value within a specific range or a phase value outside the specific range, and a weight value is determined based on the result of the determination. The demodulator according to claim 1, wherein the reproduction phase value is multiplied by and the result and the average phase value are averaged to obtain a reproduction phase value.