JPH0567978A - Coder/decoder - Google Patents

Abstract

PURPOSE:To quicken the processing by selecting a degree prediction value register for reading and revising a degree prediction value when state of a reference symbol is a specific state and selecting a degree prediction memory in other cases. CONSTITUTION:When bits of a reference symbol pattern 102 are all not zero and a prediction value object symbol is inputted to a coder as an information source symbol 101, a reference symbol generator 1 outputs a processed signal and a detector 7 discriminates that all bits are not zero. A selector 9 receives the result and outputs an output signal read from a degree prediction value memory 2 to an area width table 4 and a prediction converter 3. When bits of the pattern 102 are all zero, the selector 9 selects an output of the degree prediction value register 8 in place of the memory 2 as the degree and prediction value signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an encoding / decoding device,
In particular, it relates to a coding / decoding device for image information and the like.

[0002]

2. Description of the Related Art In coding a Markov information source, a target symbol to be coded is predicted from a reference symbol which has already been coded with respect to an output symbol sequence of the information source, and the prediction error signal is used as a reference symbol pattern. Thus, each prediction error signal is classified into several groups according to the predictive predictive value, and coding is performed using a code suitable for each. Here, the generation of this prediction error signal is called prediction conversion, the classification into groups is called integration, and the group identifier is called order. Further, the prediction error signal to be encoded will be referred to as a prediction error symbol.

This predictive conversion and order selection method is to cope with local changes in the statistical properties of the information source.
A technique for performing adaptive processing is disclosed in Japanese Patent Application No. 1-127134. Regarding the encoding method of the prediction error symbol, the subtraction type arithmetic encoding method is described in IBM Research and Development Information 19
Vol. 32, No. 6, November 1988 (IBM Journal
l of Research and Development, V
ol. 32, No. 6, Nov. 1988) "Overview of the Basic Principles of Binary Arithmetic Encoder for Q-coder" (An
overview of the basic pri
ncle of the Q-Coder adaptive-b
It is disclosed in, for example, Japanese Laid-Open Patent Publication No. 2-202267. These are symbol sequences on the number line from 0.0 to 1.
This is a kind of number line display encoding method that maps up to 0 and encodes the coordinates as a code word, and is performed only by addition and subtraction when dividing a number line according to a generated symbol.

The process of predictive conversion, integration and coding according to the conventional technique will be described below with reference to FIG. For simplicity, the information source is a binary image signal and the reference symbol is shown in FIG.
12 pixels, and the integrated number is 16.

In FIG. 25, 1 is a reference symbol generator for selecting and outputting a reference symbol from a sequence of information source symbols 101, and 2 is a reference symbol pattern 102 which is the output thereof, and outputs the order 103 and predicted value 104 of the target symbol. Order / predicted value memory, 3 is a prediction converter that creates a prediction error symbol 105 based on the predicted value 104, and 4 is the order 10
An area width table for outputting the area width 106 of the arithmetic code based on 3, 5 is an arithmetic encoder, and 6 is an order / predicted value control circuit for controlling reading and updating of the order / predicted value memory 2. Here, since the number of reference symbols is set to 12, 2 ¹² kinds of order / predicted value tables (contents of the memory 2) are required as shown in FIG. As for the numerical value, since the integration is made into 16 groups, this can be identified. Here, the higher the predictive predictive value, the higher the order.

Next, the operation will be described with reference to FIG.
The symbol 101 (image signal) generated from the information source is stored in the reference symbol generator 1 and its sequence is stored.
The signal of 12 pixels shown in 6 is selected and output as the reference symbol pattern 102. Based on this, the order / predicted value memory 2 outputs the predicted value 104 and the order 103 of the target symbol from the table contents shown in FIG.
The information is converted and output as the area width 106 in the area table 4 shown in FIG.

On the other hand, the generated symbol 101 is the prediction converter 3
Then, an exclusive OR is calculated with the prediction value 104 to create a prediction error symbol 105. Since this prediction error symbol is a binary image signal to be encoded, it is 0 when the prediction matches.
(MPS: MoreProblem Symbol
l), 1 (LPS: Less Prob if there is no match)
Able Symbol).

In the arithmetic encoder 5, the prediction error symbol 105 is mapped on a number line based on the region width 106 signal, and coding is executed. That is, the i-th symbol in the prediction error symbol sequence is a _i , and the LP at the i-th time point is
When the mapping range (allocation area) of S is S, the mapping range (effective area) Ai of the symbol sequence at the i-th time point and its lower bound coordinate Ci are the MPS area of the effective area when the symbol a _i is MPS. In the lower side, Ai = Ai−1−S Ci = Ci−1 When the symbol a _i is LPS, Ai = S Ci = Ci−1 + (Ai−1−S).

When the effective area Ai becomes 1/2 or less, it is multiplied by a power of 2 in order to improve the calculation accuracy. At this time, overflow of coordinates Ci (portion above decimal point)
Minutes are output as a code bit sequence. Hereinafter, this exponentiation process is called normalization. Ai update value = Ai * 2 ^m (1/2 <Ai update value ≦ 1) Ci update value = Ci * 2 ^m

In the arithmetic code, it is known that high efficiency coding extremely close to the information source entropy can be performed by setting S to the appearance probability (= prediction error probability) of LPS. Therefore, arithmetic coding can be performed by the above processing by selecting an S value suitable for the predictive predictive value corresponding to the order. FIG. 28 is an example of a correspondence table between the degree and the area width S. The values in the table are the values in the above formula multiplied by 2 ¹⁶ .

Next, the adaptive processing of prediction and integration will be described. The order / predicted value control circuit 6 counts the number of consecutive MPSs and LPSs from the output symbol sequence of the predictive converter 3, and, for example, at the time of detecting k MPSs and at the time of detecting 1 LPS, performs the following procedure. The contents of the order / predicted value table memory 2 are rewritten. The values of k and l are preset in the order / predicted value control circuit 6 according to each order.

When one LPS is detected, the order / predicted value table memory 2 subtracts 1 from the order value corresponding to the reference symbol pattern at that time. This is an operation of adapting the order / predicted value to the information source currently being coded by lowering the order indicating the prediction accuracy because the prediction in the reference symbol state is wrong. Is. When the order reaches the lowest order and the order cannot be further reduced, the predicted value is inverted. By this operation, the predicted value with extremely bad hit rate is rewritten.

When k MPSs are detected In the order / prediction value table memory 2, the order value corresponding to the reference symbol pattern at that time is incremented by one. This is because the prediction in the reference symbol state is correct, so by increasing the order indicating the accuracy of the prediction, the order / predicted value is adapted to the information source currently being encoded. It is an action. If the order has already reached the highest order, no addition is performed. When the prediction hits extremely well by this operation, the S value becomes smaller by increasing the order, and the code amount output from the arithmetic encoder 5 can be suppressed.

By the above operation, the order / predicted value control circuit 6
Can rewrite the order / predicted value table according to the property of the information source, and realize the arithmetic coding with high coding efficiency.

[0015]

However, in this conventional apparatus, the order / prediction value memory 2 is a general-purpose RAM because of its capacity (2 ¹² × 5 bits in the above embodiment).
I have no choice but to use. On the other hand, as is apparent from the above description, in the arithmetic coding based on the Markov model, the reference symbol pattern is created for each symbol, the order / predicted value memory 2 is searched, and the area of the number line is calculated. A4 size original document is 8 pixels / mm horizontally and 7.7 l vertically
In the case of encoding with a resolution of ine / mm, it is about 1.3 seconds, which is significantly higher in processing speed than an encoding / decoding device based on another encoding method such as MMR encoding.

The present invention has been made in order to solve the above problems, and a code capable of significantly increasing the processing speed by making it possible to access the order / prediction value memory for a specific reference symbol pattern at high speed. The purpose is to obtain an encryption / decryption device.

Another invention is made in order to solve the above-mentioned problems, and the search of the order / predicted value table for the next symbol and the area calculation of the number line for the symbol are performed in parallel. By doing so, it is an object to obtain an encoding / decoding device capable of significantly increasing the processing speed.

Further, another invention has been made to solve the above-mentioned problems, and when a specific reference symbol pattern is continuous, the number line area calculation is performed as a batch process. It is an object of the present invention to obtain an encoding / decoding device capable of various high-speed processing.

[0019]

The encoding / decoding apparatus according to the first aspect of the present invention determines that an object to be coded is predicted from the states of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source. When the prediction error signal is encoded and the prediction error signal is encoded, the predicted value of the encoding target symbol and the order that is the identifier of the group classified by the predictive matching rate are calculated from the state of the reference symbol. A rewritable memory for storing, a detector for detecting that the state of the reference symbol is one or more specific states, and one or more for storing predicted values and orders in the specific states. A register, a selector for selecting the memory and the register output based on the detector output, an arithmetic encoder for encoding a prediction error signal based on the prediction value / order information output from the selector, Coded symbols are those having a degree and predicted value controller for rewriting in the predicted value and degree to the reference symbol state in accordance with the inspection and the result whether they match the prediction.

In the encoding / decoding device according to the second aspect of the present invention, the decoding target symbol to be decoded is predicted from the states of a plurality of reference symbols at predetermined positions of the output symbol sequence of the information source. When performing a prediction and decoding a coded bit sequence obtained by coding the prediction error signal, the degree that is the identifier of the group classified by the prediction value and the prediction matching rate of the decoding target symbol from the state of the reference symbol, and , A detector for detecting that the state of the reference symbol is one or more specific states, and a predictive value and order for the specific state 1
To a plurality of registers and based on the detector output,
A selector for selecting the memory and the register output, an arithmetic decoder for decoding a code bit sequence based on the order output from the selector, and checking whether or not the decoding target symbols are predictively matched, An order / predicted value control circuit for rewriting the predicted value and the order in the reference symbol state according to the result is provided.

The encoding / decoding device according to the third aspect of the invention predicts the symbol to be encoded by predicting the symbol to be encoded from the states of a plurality of reference symbols at predetermined positions in the output symbol sequence of the information source. When encoding the error signal, a rewritable memory that stores the predicted value of the encoding target symbol in each state of the reference symbol and the order that is the identifier of the group classified by the predictive coincidence rate, and from this memory The predicted value and order signal of the read target symbol to be encoded, or, for the immediately preceding target symbol to be encoded,
Prediction value and order of the memory in the reference symbol state are checked in accordance with the result of checking whether or not the order / prediction value register that stores the prediction value and order after the rewriting process matches the prediction target symbol. The order of rewriting
A predictive value control circuit, a detector that detects whether or not the reference symbol state for the symbol to be encoded and the reference symbol state for the immediately preceding symbol match, and updates the contents of the order / predicted value register according to the detection result. An arithmetic encoder for encoding a prediction error signal based on the predicted value / order information output from the order / predicted value register.

In the encoding / decoding device according to the fourth aspect of the present invention, the decoding target symbol to be decoded is predicted from the states of a plurality of reference symbols at predetermined positions of the output symbol sequence of the information source. When performing a prediction and decoding a code bit sequence obtained by coding the prediction error signal, the prediction value of the decoding target symbol from the state of the reference symbol and the order that is the identifier of the group classified by the prediction matching rate are A rewritable memory to be stored, and an order / prediction value control circuit for checking whether or not the decoding target symbols are predictively matched and rewriting the prediction value and the order of the memory in the reference symbol state according to the result , A register for storing the predicted value and order from this memory, or the updated predicted value and order for the immediately preceding decoding target symbol, and the decoding target symbol It detects whether or not the reference symbol state for the corresponding symbol and the reference symbol state for the immediately preceding symbol match and detects the detector according to the detection result, and a set of predicted values and orders of the memory outputs for a plurality of states. A selector for selectively outputting and an arithmetic decoder for decoding a code bit sequence based on the selected prediction value / order information are provided.

The encoding / decoding device according to the fifth aspect of the present invention predicts the symbol to be encoded by predicting the symbol to be encoded from the states of a plurality of reference symbols at predetermined positions of the output symbol sequence of the information source. When encoding the error signal, a rewritable memory that stores the predicted value of the encoding target symbol from the state of the reference symbol and the order that is the identifier of the group classified by the predictive matching rate, and a plurality of consecutive rewritable memories. A detector that detects that all the reference symbol states for the encoding target symbol are in a specific state and that all the encoding target symbols predictively match, and the code based on the prediction value stored in the memory. The prediction converter for calculating the prediction error of the symbol to be coded and the prediction symbol of the symbol to be coded are checked, and the memo in the reference symbol state is checked according to the result. And a predictive value control circuit that rewrites the predictive value and the order, and an arithmetic encoder that encodes the prediction error signal calculated by the predictive converter based on the order information stored in the memory. It is a thing.

The encoding / decoding apparatus according to the sixth aspect of the present invention predicts the encoding target symbol sequence from the states of a plurality of reference symbols at predetermined positions of the output symbol sequence of the information source, When a coded bit sequence obtained by coding a prediction error signal is decoded, the rewritable value is stored which stores the predicted value of the decoding target symbol and the order which is the identifier of the group classified by the predicted matching rate from the state of the reference symbol. A memory and a detector for detecting that all the states of the reference symbols for the plurality of decoding target symbols are in a specific state when it is assumed that a plurality of consecutive decoding target symbols are predictively matched; An arithmetic decoder that decodes a code bit sequence based on order information stored in a memory to create a prediction error signal, and a prediction error signal and a prediction signal created by the arithmetic decoder Based on the prediction inverse converter that restores the decoding target symbol based on the above, it is checked whether the restored decoding target symbol matches the prediction, and the prediction value and the order in the reference symbol state are determined according to the result. It is provided with a rewriting order / predicted value control circuit.

[0025]

According to the first aspect of the invention, when the reference symbol is in a specific state, the register is selected for reading and updating the order / predicted value, and in other states, the memory is selected. The coding speed is improved by using it.

According to the second invention, when the state of the reference symbol is in a specific state, the register is selected for reading and updating the order / predicted value, and in other states, the memory is selected. The decoding speed is improved by using it.

According to the third aspect of the present invention, the prediction value and the order signal used in the encoding process depend on whether or not the reference symbol state for the symbol to be encoded and the reference symbol for the immediately preceding symbol match. The encoding speed is improved by selecting and using the predicted value and the order or the output signal from the order / predicted value memory after the rewriting process for the symbol to be coded.

According to the fourth aspect of the present invention, the prediction value and the order signal used in the decoding process depend on whether or not the reference symbol state for the symbol to be decoded and the reference symbol for the immediately preceding symbol match. The decoding speed is improved by selecting and using the predicted value and the order or the output signal from the order / predicted value memory after the rewriting process for the symbol to be decoded.

According to the fifth aspect of the invention, when the state of the reference symbol for a plurality of consecutive symbols to be coded is in a specific state, the arithmetic encoder performs arithmetic operation on the plurality of symbols. The encoding speed is improved by performing the operations collectively.

According to the sixth aspect of the invention, when the state of the reference symbol with respect to a plurality of consecutive symbols to be decoded is in a specific state, the arithmetic encoder performs arithmetic operation on the plurality of symbols. Decoding speed improves by carrying out collectively.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first invention will be described below with reference to illustrated embodiments. FIG. 1 shows an encoding apparatus according to an embodiment of the present invention. In FIG. 1, the difference from the conventional encoding apparatus of FIG. 25 is that reference symbol patterns 102 to 12 of FIG.
A detector 7 for detecting whether all the pixels are 0 (white pixels),
A register 8 for storing an order and a predicted value when all 12 pixels are 0, and a memory 2 depending on whether all 12 pixels are 0 or not.
And that the selector 9 for switching the output of the register 8 and the update signal for writing to these is added.

FIG. 2 is a block diagram showing the internal configuration of the arithmetic encoder 5. In the figure, 5a is an A register for storing the effective area Ai on the number line, and 5b is an MPS area width 11
7 is a subtracter for calculating 7; 5c is a C register for storing the lower bound coordinate 118; 5d is a C register value for LPS 11
The adder 5e for calculating 9 temporarily stores the carry output 120, which is an overflow (shift-out) signal of the C register, carries out a carry when updating the C register 5c, and the stored sign bit contents are continuous. When the number of eight "1" s is reached, a process of inserting "0" from the bottom of the least significant bit to suppress the influence of the carry process after that to the insertion "0" or less (hereinafter referred to as bit stuffing process). A code register 5f for performing the above is a timing control circuit for controlling the movement of the arithmetic encoder 5.

Next, the operation of this embodiment will be described.
3 and 4 are timing charts showing an operation example of this embodiment. In order to facilitate the description, first, the case where the reference symbol patterns 102 shown in FIG. 3 are not all “0” and the case where all of them are “0” will be separately described.

First, when all the reference symbol patterns 102 are not "0", when the symbol to be predicted is input as the information source symbol 101 to the present coding apparatus, it has already been processed in the reference symbol generator 1. The signal of the reference pixel of 12 pixels shown in FIG.
In, it is determined that they are not all "0". The selector 9 receives this and outputs the output signal in the reference symbol pattern read from the order / prediction value memory 2 to the region width table 4 and the prediction converter 3. Here, in this embodiment, the reading process of the order / predicted value memory 2 is 10M.
Two HZ system clock cycles are set to 200 nsec.

The order signal 112 is converted by the area width table 4 into the area width signal 106 shown in FIG.
Reference numeral 13 is a prediction converter 3 which performs an exclusive OR operation on the information source symbol 101 to generate a prediction error symbol 105. After that, the calculation of the effective area Ai and the lower limit coordinate Ci and the update of the order / predicted value are performed as follows. (1) When normalization and order / prediction value updating is not performed (# 1 in FIG. 3) The calculation of the above area and coordinates is executed in one cycle of the system clock. (2) If there is normalization and there is no update of order / prediction value (# 2 in Fig. 3), the area / coordinate calculation processing other than normalization is performed by the system clock 1
In cycles, normalization is performed in m clocks. (3) When there is no normalization and there is an update of the order / predicted value (# 3 in FIG. 3) After the area and coordinates are calculated in one cycle of the system clock, the contents of the order / predicted value memory 2 are updated. The memory is updated in two system clock cycles. (4) When there is normalization and update of order / predicted value (Fig. 3
# 4) System clock 1 for area / coordinate calculation processing excluding normalization
After the cycle, the normalization is performed with m clocks, and the order / predicted value memory 2 is updated in parallel. At this time, the processing of the next symbol is performed after both the normalization and the update of the memory 2 are completed.

Here, the control of the area calculation and the coordinate calculation including the determination of LPS and MPS is performed by the prediction error symbol 105.
Further, based on the MSB signal of the A register output 116, the timing control circuit 5f of the arithmetic encoder 5 performs the update control of the order / predicted value memory 2 by the order / predicted value control circuit 6.

In the sign register 5e, the carry process is performed in parallel with the above-mentioned (excluding normalization) area / coordinate calculation. At the time of normalization, the carry from the 8th bit is output as code 107 along with the shift of the internal register. At this time, when all the bits of the 8-bit internal register are "1", the bit stuff signal 122 is sent to the timing control circuit 5f, the normalized clock 121 is temporarily stopped, and the system clock 1 cycle is used to perform the internal operation. 1-bit shift of the register (LSB shift-in signal is set to "0") is performed.

All reference symbol patterns 102 are "0".
In the case of, the selector 9 selects the output of the order / predicted value register 8 as the order and predicted value signal instead of the output of the order / predicted value memory 2. Since only the delay (10 nsec or less) in the selector 9 needs to be taken into consideration in this process, a special cycle for reading the order / predicted value becomes unnecessary. Also, the update of the order / predicted value is possible in one system clock cycle. Therefore, the processing when the reference symbol patterns 102 are all "0" is as shown in FIG.

In the above, the case where all the reference symbol patterns 102 are "0" or other cases have been separately described, but in actual image signal coding, these occur in a mixed manner. Therefore, the operation timing is a combination of the cases of FIGS. 3 and 4.

As is apparent from the above description, in the encoding processing time T in this embodiment, the number of symbols other than "0" for all reference symbol patterns is Na, the number of symbols for all "0" is Nb, and the code is When the number of bits is Nc, T = 200 * Na + 100 * (Na + Nb) + 100 * Nc + 100 * α (nsec). Here, α is the number of clocks required to be added (required for updating when there is no normalization process) when the updating process is not completed at the end of the normalization process when updating the order / predicted value.

Therefore, the standard resolution is horizontal 8 pixels / m.
Assuming that the ratio of all reference symbol patterns to be “0” is 2/3 and the compression rate is 30 for an A4 size document of m, vertical 7.7 lines / mm, Na = 1728 * 2376 * (1/3) Nb = 1728 * 2736 * (2/3) Nc = 1728 * 2736 * (1/30), and the encoding processing time T becomes about 0.7 seconds. Here, since the update of the order / predicted value is about 1/50 to 1/200 of all symbols, the influence of α is ignored.

On the other hand, in the conventional encoding apparatus, if Na = 1728 * 2376 Nb = 0 Nc = 1728 * 2736 * (1/30) in the above equation, the encoding processing time T is about 1.25 seconds. Therefore, it can be seen that the present invention can realize a significant improvement in the encoding processing speed.

Next, FIG. 5 shows a block configuration of a decoding device according to an embodiment of the second invention. In the figure, 10
Is an arithmetic decoder that reproduces the prediction error symbol 105 from the code bit sequence 107 based on the region width signal 106, and 11 performs the exclusive OR operation of the prediction error symbol 105 and the prediction value 113 to obtain the information source symbol 101. It is a predictive inverse converter for reproduction, and the other part is the same circuit as the embodiment of FIG.

FIG. 6 is a block diagram showing the internal structure of the arithmetic decoder 10. 10a is an effective area Ai on the number line.
A is a register that stores the MPS area width 117, 10c is a register that stores the lower bound coordinates, 10d is a subtractor that calculates the C register value 119 in the case of LPS, and 10e is the sign bit sequence 107 Is stored temporarily, and the most significant signal of the internal 9-bit register is sent to the C register in accordance with the normalized shift clock 122, and the contents of the lower 8 bits of the stored sign bit become eight consecutive "1" s. In this case, a code register for performing stuff bit removal processing for deleting the bit stuff signal inserted in the encoder by inputting 1 bit from the code bit sequence 107 and performing addition at the lowest position of the internal 9-bit register. 10 f is a timing control circuit for controlling the movement of the arithmetic decoder 10.

Next, the operation of this embodiment will be described. In the decoding of the arithmetic code, if Ci is the relative coordinate that is the contents of the C register and S is the area width of the LPS at the time of the i-th prediction error symbol a _i , Ci−1 <(Ai−1−S ) Then a _i is MP
If S Ai = Ai−1−S Ci = Ci−1 Ci−1 ≧ (Ai−1−S), then a _i is LPS Ai = S Ci = Ci−1 (Ai−1−S).

If the effective area Ai becomes 1/2 or less, the normalization process is performed to increase the calculation accuracy to 2
To the power of. At this time, the carry input signal 123 is input from the code register 10e from the least significant bit of Ci. Ai update value = Ai * 2 ^m (1/2 Ai update value ≦
1) Ci update value = Ci * 2 ^m

7 and 8 are timing charts showing an operation example of this embodiment. FIG. 7 shows a case where the reference symbol patterns 102 are not all "0", and FIG. 8 shows a case where they are all "0". The operations of creating the reference symbol pattern 102, creating and updating the order / predicted value are the same as those in the embodiment of FIG.

Regarding the reproduction of the prediction error symbol a _i and the calculation of the effective area Ai and the relative coordinate Ci, first, in the timing control circuit 10f, as described above, Ci-1 and (Ai
-1-S) is performed to determine the symbol a _i (MPS or LPS), and based on this, Ai and Ci are calculated and set in the A register 10a and the C register 10c. This series of processing is performed in one cycle of the system clock.

As a result of this calculation, when the effective area Ai becomes less than 1/2, the above normalization processing is performed in m clocks. At this time, the contents of the lower 8 bits of the sign bit stored in the sign register 10e are consecutive "1" s.
In this case, the normalized clock 121 is temporarily stopped, 1 bit is input from the code bit sequence 107, and addition is performed at the lowest position of the internal 9-bit register.

Therefore, the decoding processing time T becomes T = 200 * Na + 100 * (Na + Nb) + 100 * Nc + 100 * α (nsec) as in the case of encoding, and this embodiment also has a large time compared with the conventional decoding device. Improvement can be realized.

Further, in the above-described embodiment, the special register is provided only for the state of all "0" as the reference symbol pattern to speed up the processing. However, for example, the state of all the reference symbol patterns including "1" is included. Alternatively, a plurality of registers may be provided.

The third aspect of the present invention will be described below with reference to the illustrated embodiments. FIG. 9 shows an encoding apparatus according to an embodiment of the present invention. In FIG. 9, the difference from the conventional encoding apparatus shown in FIG. 25 is that the reference symbol pattern from the reference symbol pattern 102 to the immediately preceding encoding target symbol is changed. And the detector 7 for detecting whether or not the reference symbol pattern for the encoding target symbol matches, the order 103 and the predicted value output 104 from the order / predicted value memory 2, or the order / predicted value control circuit 6. The point is that the order / prediction value register 8b for temporarily storing the update signal 108 is provided, and this output is used as the input to the region width table 4 and the prediction converter 3.

FIG. 10 is a block diagram showing the internal structure of the arithmetic encoder 5. In the figure, 5a is an A register for storing the effective area Ai on the number line, 5b is a subtracter for calculating the MPS area width 117, 5c is a C register for storing the lower bound coordinate 115, and 5d is a C register for the LPS. An adder for calculating the value 116, 5e is a carry output 117 which is an overflow (shift out) signal of the C register.
Is temporarily stored to carry a carry when updating the C register 5c, and if the stored code bit contents are eight consecutive "1" s, "0" is inserted from the bottom of the least significant bit. Then, a code register 5f for performing processing (hereinafter referred to as bit stuffing processing) for suppressing the influence of the carry processing thereafter to this insertion "0" or less is a timing control circuit for controlling the operation of the arithmetic encoder 5. is there.

Next, the operation of this embodiment will be described.
FIG. 11 is a timing chart showing an operation example of this embodiment.
First, when the encoding target symbol is input to the present encoding device as the information source symbol 101, the reference symbol generator 1
26, the signal of the reference pixel of 12 pixels shown in FIG. 26 that has already been processed is output 102, and the order and prediction value in the reference symbol pattern are read from the order / prediction value memory 2 and stored in the order / prediction value register 8. It Here, in the present embodiment, the process of creating the reference symbol pattern and storing it in the register 8 is 100 nsec for one cycle of the system clock of 10 MHZ.

The order signal 111 is converted by the area width table 4 into the area width signal 106 shown in FIG.
Reference numeral 12 is a prediction converter 3 which performs an exclusive OR operation on the information source symbol 101 to generate a prediction error symbol 105. After that, the calculation of the effective area Ai and the lower limit coordinate Ci and the update of the order / predicted value are performed as follows. (1) When normalization and order / prediction values are not updated (# 1 in FIG. 19) The calculation of the above area and coordinates is executed in one cycle of the system clock. (2) When there is normalization and there is no update of the order / predicted value (# 2 in FIG. 19) The area / coordinate calculation processing other than normalization is performed by the system clock 1
In cycles, normalization is performed in m clocks.

(3) Order / prediction value update without normalization (# 3 in FIG. 19) After the area and coordinates are calculated in one cycle of the system clock, the contents of the order / prediction value memory 2 are changed. Update. The memory is updated in one cycle of the system clock. (4) When there is normalization and updating of order / predicted value (Fig. 19)
# 4) System clock 1 for area / coordinate calculation processing excluding normalization
After the cycle, the normalization is performed with m clocks, and the order / predicted value memory 2 is updated in parallel. At this time, the next symbol coordinate calculation process is performed by normalization and memory 2.
It will be done after updating both.

Here, the control of the area calculation and the coordinate calculation including the determination of LPS and MPS is performed by the prediction error symbol 105.
And the timing control circuit 5f of the arithmetic encoder 5 based on the MSB signal of the A register output 113, and the update control of the order / predicted value memory 2 is performed by the order / predicted value control circuit 6.

In the sign register 5e, the carry process is performed in parallel with the above-mentioned (excluding normalization) area / coordinate calculation. At the time of normalization, the carry from the 8th bit is output as code 107 along with the shift of the internal register. At this time, when all the bits of the 8-bit internal register are "1", the bit stuff signal 119 is sent to the timing control circuit 5f, the normalized clock 118 is temporarily stopped, and the system clock 1 cycle is used to perform the internal operation. 1-bit shift of the register (LSB shift-in signal is set to "0") is performed.

Since the order / prediction value may be updated in the reading process from the order / predicted value memory 2 and the calculation of the effective area Ai / lower bound coordinate Ci, conventionally, the serial / serial process is performed. It had been. In the present embodiment, this is performed in parallel with the calculation of the effective area Ai / lower bound coordinate Ci for the target symbol to be encoded and the reading process from the order / predicted value memory 2 for the next symbol to be encoded as follows. To process.

That is, when the order / prediction value register 8 outputs the order signal and the predicted value signal of the target symbol to be encoded, the order / predicted value memory 2 outputs the order and the predicted value for the next target symbol to be encoded. It is read using one cycle of the system clock. After that, the processing is performed as follows. (1) When normalization and order / prediction values are not updated (# 1 in FIG. 19) After the above area and coordinates are calculated, the area / coordinate calculation of the next encoding target symbol is performed. (2) Normalization is performed and order / prediction value is not updated (# 2 in FIG. 19) After normalization is completed, the process proceeds to the area / coordinate calculation of the next encoding target symbol. (3) When there is no normalization and the order / predicted value is updated (# 3 in FIG. 19) The contents of the order / predicted value memory 2 are updated by referring to the reference pattern (reference symbol) for the symbol output from the detector 7. The pattern 102 delayed by one symbol) and the update signal 108 from the order / prediction control circuit 6 are used. At this time, if the reference symbol pattern 102 (signal for the next encoding target symbol) and the reference pattern for the encoding target symbol match, the detection signal 11
Based on 0, the contents of the order / predicted value register are updated. These content updates are processed in one cycle of the system clock, and then the area / coordinate calculation of the next encoding target symbol is performed. (4) When there is normalization and updating of order / predicted value (Fig. 19)
# 4) The contents of the order / predicted value are updated in the same manner as (3). If the normalization process is not completed after updating the content, wait for it and
The process moves to the area / coordinate calculation of the next encoding target symbol.

As is apparent from the above description, the encoding processing time T in this embodiment is T = 100 + 100 * Na + 100 * Nc + 100 * α (nsec), where Na is the total number of symbols and Nc is the number of code bits. Becomes Here, α is the number of clocks required to update the order and the predicted value in the case of (3) above. Therefore, A with a standard resolution of 8 pixels / mm horizontally and 7.7 lines / mm vertically
Assuming a compression ratio of 30 for a 4-size original, Na = 1728 * 2376 Nc = 1728 * 2736 * (1/30), and the encoding processing time T is about 0.4 seconds. Here, the update of the order / prediction value is about 1/50 to 1/200 of all symbols, and the case of (3) above is limited to the case where the prediction result is MPS and normalization does not occur. Ignored the effect of.

On the other hand, similarly in the conventional encoding device, T = (100 + 100) * Na + 100 * Nc + 100 * α (nsec). Therefore, if the calculation is performed under the same conditions as described above, the encoding processing time T becomes about 0.8 seconds, and it is understood that the present invention can realize a significant improvement in the encoding processing speed.

Next, FIG. 12 shows a block configuration of an encoding apparatus which is another embodiment of the present invention. In the figure, 9 is an update order / prediction value register, and 10 is an order / prediction value memory 2
Order / predicted value register 8 for storing the read signal from
And an output of the update order / predicted value register 9 are selected.

In this embodiment, only the read signal from the order / predicted value memory 2 is stored in the order / predicted value register 8, and the updated order / predicted value register 9 is subjected to the adaptive processing of the order and the predicted value (updated). If an update is performed, a signal of the selector 10 used in the area calculation is stored), and the detection signal 110 causes the reference pattern of the target symbol to be encoded immediately before. When the same as the reference pattern of the symbol, the output from the update order / prediction value register 9 is used, and when it is different, the area width calculation and prediction conversion are performed using the output from the order / prediction value register 8. The other processing is the same as that of the embodiment of FIG. However, the detection signal 110 from the detector 7
Is delayed by one symbol as compared with the case of the embodiment of FIG.

Next, FIG. 13 shows a block configuration of a decoding apparatus which is an embodiment of the fourth invention. In the figure, 11
Is an arithmetic decoder that reproduces the prediction error symbol 105 from the code bit sequence 107 based on the region width signal 106, and 12 performs an exclusive OR operation of the prediction error symbol 105 and the prediction value 112 to obtain the information source symbol 101. It is a predictive inverse converter for reproduction. Further, 2 is A among the reference pixels in FIG.
In the order / prediction value memory which inputs the reference symbol pattern of 11 pixels except for A and outputs the order and prediction value signals (two kinds of 103a, 104a and 103b, 104b, respectively) for two kinds of states in which A is 1 and 0 Yes, 8 is a register which receives this output and also stores two kinds of orders and predicted values. Further, 13 is a selector for selecting one of two kinds of orders and prediction values according to the information source symbol 101 immediately before reproduced by the prediction inverse converter 12, and updating from the order / prediction value control circuit 6. For receiving the signal 108 and updating the contents of the order / prediction value memory 2 and the contents of the order / prediction value register 8 in which the reference pixel A in FIG. 26 is either 1 or 0 in response to the reproduced information source symbol. First selection update signal 108a and second selection update signal 108b
Has the function of creating. The other part has the same circuit as that of the embodiment of FIG.

FIG. 14 is a block diagram showing the internal structure of the arithmetic decoder 11. 11a is an effective area A on the number line.
A register for storing i, 11b is MPS area width 114
, 11c is a register for storing the lower bound coordinate, 11d is a subtractor for calculating the C register value 116 in the case of LPS, 11e is a temporary storage of the sign bit sequence 107, and corresponds to the normalized shift clock 118. The highest-order signal of the internal 9-bit register is sent to the C register, and when the contents of the lower 8 bits of the stored code bit become eight consecutive "1" s, the code bit sequence 107 to 1
A code register for performing stuff bit removal processing for deleting the bit stuff signal inserted in the encoder by inputting bits and performing addition at the lowest position of the internal 9-bit register, 11f is the arithmetic decoder 11 It is a timing control circuit that controls movement.

Next, the operation of this embodiment will be described. In the decoding of the arithmetic code, if the relative coordinates that are the contents of the C register are Ci and the area width of the LPS at the time of the i-th prediction error symbol a _i is S, then Ci-1 <(Ai-1 − S ), A _i is MPS Ai = Ai-1-S Ci = Ci-1 Ci-1 ≧ (Ai-1-S) If _ai is LPS Ai = S Ci = Ci-1 (Ai-1-S) ).

If the effective area Ai becomes 1/2 or less, the normalization process is performed to increase the calculation accuracy by 2
To the power of. At this time, the carry input signal 117 is input from the encoding register 11e from the least significant bit of Ci. Ai update value = Ai * 2 ^m (1/2 Ai update value ≦
1) Ci update value = Ci * 2 ^m

FIG. 15 is a timing chart showing an operation example of this embodiment. First, for the decoding target symbol, based on the reference symbol pattern of 11 pixels excluding A among the reference pixels in FIG. Store in 8. These processes are performed during the time of one cycle of the system clock. After that, the information source symbol A which is reproduced immediately before is A.
One of these two types of order and prediction value is selected according to the value of, and the information symbol is reproduced and the order and prediction value are updated.

Regarding the reproduction of the prediction error symbol a _i and the calculation of the effective area Ai and the relative coordinates Ci, first, in the timing control circuit 11f, as described above, Ci-1 and (Ai
-1-S) is compared to determine the symbol a _i (MPS or LPS), and based on this, Ai and Ci are calculated and set in the A register 11a and the C register 11c. This series of processing is performed in one cycle of the system clock.
As a result of this calculation, when the effective area Ai becomes less than 1/2, the above normalization processing is performed in m clocks. Here, when the contents of the lower 8 bits of the sign bit stored in the sign register 11e become eight consecutive "1" s, the normalized clock 118 is temporarily stopped and one bit is input from the sign bit sequence 107. And the addition is performed at the lowest position of the internal 9-bit register.

When it is necessary to update the order / predicted value, an update signal is issued from the order / predicted value control circuit 6, and the selector 13
At the selected update signal (108a, 108a,
108b) is generated and the contents of the order / predicted value memory 2 are updated. At this time, if the reference pattern 102 of the order / predicted value memory 2 read immediately before coincides with the update reference symbol pattern, the contents of the order / predicted value register 8 are updated at the same time. This updating process is performed after setting the A register and the C register, and is executed in one system clock period.

Therefore, the decoding processing time T becomes T = 100 + 100 * Na + 100 * Nc + 100 * α (nsec) as in the case of the next encoding, and in this embodiment as well, a great improvement can be realized as compared with the decoding device according to the prior art.

FIG. 16 shows a block configuration of a decoding apparatus which is another embodiment. In this embodiment, as in FIG. 13, a register 9 for updating is provided separately from the register 8a for storing the read signal of the memory 2, and a selector 10 is added. However, like the embodiment of FIG. 12, in this embodiment, the detector 7 is different from that of the embodiment of FIG.
The detection signal output 110 of 1 is delayed by one symbol.

In the above embodiment, the order and the predicted value are updated by L
The method of counting and controlling the number of PS and MPS was used.
A method of controlling updating may be used only at the timing when the normalization is performed like the IBM research and development information.

The fifth invention will be described below with reference to the illustrated embodiments. FIG. 17 shows an encoding apparatus according to an embodiment of the present invention. In FIG. 17, the difference from the conventional encoding apparatus of FIG. 25 is that the eight symbols to be encoded immediately before the reference symbol pattern 102 are included. 26, the detector 7 for detecting whether all 12 reference pixels are “0” (white pixels) and the coded symbols are also “0”, and when all 12 reference pixels are “0” A register 8 for storing the order and the predicted value, and an a11 “0” state order signal 110 indicating that the output is the highest order 16 when the detector 7 output and all 12 reference pixels from the register 8 are “0”. Similarly, a11 “0” state prediction signal 11 indicating that the prediction value is “0”
That is, the first AND circuit 9 for calculating the logical product of 1 is added.

FIG. 18 is a block diagram showing the internal structure of the arithmetic encoder 5. In the figure, 5a is an A register for storing the effective area Ai on the number line, 5b is a subtractor for calculating the MPS area width 114, 5c is a C register for storing the lower bound coordinate 115, and 5d is a C register for the LPS. An adder for calculating the value 116, 5e is a carry output 117 which is an overflow (shift out) signal of the C register.
Is temporarily stored to carry a carry when updating the C register 5c, and if the stored code bit contents are eight consecutive "1" s, "0" is inserted from the bottom of the least significant bit. Then, a code register 5f for performing processing (hereinafter referred to as bit stuffing processing) for suppressing the influence of the carry processing thereafter to this insertion "0" or less is a timing control circuit for controlling the operation of the arithmetic encoder 5. is there.

Further, 5 g has an A register output of 0 _× 100.
The area detector 5h for detecting that it exceeds 0 + 0 _X 0008 is a second AND circuit 5h for calculating the logical product of this output and the switching signal 112 which is the output of the first AND circuit 9. When the output of the AND circuit 2 is 1, it is a switcher that multiplies the area width signal 106 by 8. Of these, 5
The circuits from a to 5f are used in the conventional arithmetic encoder, and the difference between this embodiment and the conventional device is 5g to 5i.
Is the time when was added.

Next, the operation of this embodiment will be described.
19 and 20 are timing charts showing an operation example of this embodiment. For ease of explanation, when all the reference symbol patterns 102 for continuous 8 coded symbols are not “0” (hereinafter, simply referred to as a11 “0” state), the reference symbol pattern 102 for continuous 8 coded symbols. Will be explained separately by dividing into cases where all are "0".

First, in the case of the a11 "0" state, when the prediction target symbol is input to the present coding apparatus as the information source symbol 101, the reference pixel generator 1 has already processed 12 pixels of 12 pixels shown in FIG. The signal of the reference pixel is output 102, and it is determined in the detector 7 that the reference symbol patterns for the continuous 8 coded symbols are not all “0”. Therefore, the detection signal 109 is "0".
Is output. At the same time, the order / prediction value memory 2 outputs the order signal 103 in the reference symbol pattern.
Also, the output signal of the predicted value signal 104 is read. Here, in this embodiment, the reading process of the memory 2 is 10 MHz.
The system clock is set to 100 nsec.

The order signal 103 is converted by the area width table 4 into the area width signal 106 shown in FIG.
Reference numeral 04 is a prediction converter 3 which performs an exclusive OR operation on the information source symbol 101 to generate a prediction error symbol 105. After that, the calculation of the effective area Ai and the lower limit coordinate Ci and the update of the order / predicted value are performed as follows. (1) When normalization and order / prediction values are not updated (# 1 in FIG. 19) The calculation of the above area and coordinates is executed in one cycle of the system clock. (2) When there is normalization and there is no update of the order / predicted value (# 2 in FIG. 19) The area / coordinate calculation processing other than normalization is performed by the system clock 1
In cycles, normalization is performed in m clocks. (3) When there is no normalization and there is an update of the order / predicted value (# 3 in FIG. 19) After the area and coordinates are calculated in one cycle of the system clock, the contents of the order / predicted value memory 2 are updated. The memory is updated in two system clock cycles. (4) When there is normalization and updating of order / predicted value (Fig. 19)
# 4) System clock 1 for area / coordinate calculation processing excluding normalization
After the cycle, the normalization is performed with m clocks, and the order / predicted value memory 2 is updated in parallel. At this time, the processing of the next symbol is performed after both the normalization and the update of the memory 2 are completed.

When the order / predicted value is updated in the a11 "0" state, the contents of the order / predicted value register 8 for the a11 "0" state are updated at the same time as the order / predicted value memory 2. ..

The control of the area calculation and the coordinate calculation including the determination of LPS and MPS is performed by the prediction error symbols 105 and A.
Based on the MSB signal of the register output 113, the timing control circuit 5f of the arithmetic encoder 5 performs the update control of the order / predicted value memory 2 in the order / predicted value control circuit 6.

In the sign register 5e, the carry process is performed in parallel with the above-mentioned (excluding normalization) area / coordinate calculation. At the time of normalization, the carry code 107 from the 8th bit is output together with the shift of the internal register. At this time, when all the bits of the 8-bit internal register are "1", the bit stuff signal 119 is sent to the timing control circuit 5f, the normalized clock 118 is temporarily stopped, and the system clock 1 cycle is used to perform the internal operation. 1-bit shift of the register (LSB shift-in signal is set to "0") is performed.

When all the reference symbol patterns 102 for 8 consecutive encoded symbols are "0", the first and second
The AND circuit determines whether or not to collectively process the arithmetic operations. That is, the output 121 of the second AND circuit 5h is
The corresponding 8 encoded symbols are all "0" (detection signal 10
9 is “1”), and a11 “0” state order is 16 (a
When the 11 "0" state order signal 110 is "1") and the predicted value of the same state is "0" (a11 "0" state predicted value "1"), it becomes "1". When this is "0", the processing is performed at the timing shown in FIG.

In the case of batch processing, the area width signal 106 is multiplied by 8 by the switch 5i, and "0 _X 0008" is subtracted by the subtractor 5b.
Is used as the subtraction input 123 for arithmetic operation. A just before
Since the register output 113 exceeds 0 _X 0008 and becomes 0 _X 1000 or more even if the verification process is performed, the normalization process does not occur. Further, since the order and the predicted value are not updated, the next coded symbol, that is, the 9th pixel is continuously coded. This area arithmetic processing can be performed in one cycle of the system clock. The operation of this process is shown in FIG.

In the above description, the case where all of the continuous 8 reference symbol patterns 102 are "0" or other cases have been separately described, but in actual image signal encoding, these occur in a mixed manner. Therefore, the operation timing is as shown in FIG.
1 and each case of FIG. 12 are combined.

As is clear from the above description, the coding processing time T in the present embodiment is such that when the batch processing is possible, that is, all the reference symbol patterns for 8 consecutive coding target pixels are "0", and all the corresponding 8 coded symbols "0", and a11 "0" order is 16 states, and the predicted value of the state is "0", and the effective area width is 0 _X 100
Assuming that the number of encoding target symbols in the case of exceeding 0 + 0 _X 0008 is Na, the number of other encoding target symbols is Nb code, and the number of code bits is Nc, T = 100 (Na / 8 + Nb) + 100 * (Na / 8 + Nb) + 100 * Nc + 100 * α (nsec). Here, α is the required number of clocks when updating the order / predicted value in (3) above.

Therefore, the standard resolution is horizontal 8 pixels / m.
Assuming that the ratio of the pixels that can be collectively processed is 2/3 and the compression rate is 30 for an A4 size document of m, vertical 7.7 lines / mm, Na = 1728 * 2376 (2/3) Nb = 1728 * 2376 * (1/3) Nc = 1728 * 2736 * (1/30), and the encoding processing time T is about 0.35 seconds. Here, since the update of the order / predicted value is about 1/50 to 1/200 of all symbols, the influence of α is ignored.

On the other hand, in the conventional encoding apparatus, if Na = 0 Nb = 1728 * 2376 Nc = 1728 * 2736 * (1/30) in the above equation, the encoding processing time T is about 0.83 seconds. Therefore, it can be seen that the present invention can realize a significant improvement in the encoding processing speed.

Next, FIG. 21 shows a block configuration of a decoding apparatus according to an embodiment of the sixth invention. In the figure, 10 is an arithmetic decoder that reproduces a prediction error symbol 105 from a code bit sequence 107 based on a region width signal 106, and 11 is an information obtained by performing an exclusive OR operation of the prediction error symbol 105 and a prediction value 104. It is a predictive inverse transformer that reproduces the source symbol 101. Reference numeral 12 denotes a batch processing identification signal 121 from the arithmetic decoder 10 and, in the case of normal processing, a prediction inverse converter 11
In the case of batch processing, the output is an information symbol switch (selector) which outputs eight consecutive "0" signals as the information source symbol 101, and the other parts are the same circuits as in the embodiment of FIG.

FIG. 22 is a block diagram showing the internal structure of the arithmetic decoder 11. 10a is an effective area A on the number line.
A register for storing i, 10b is MPS area width 117
Is a register for storing the lower bound coordinates, 10d is a subtracter for calculating the C register value 119 in the case of LPS, 10e is a temporary storage of the sign bit sequence 107, The highest bit signal of the internal 9-bit register is sent to the C register, and when the contents of the lower 8 bits of the stored code bit become eight consecutive "1" s, the code bit sequence 107 to 1
A code register for performing stuff bit removal processing for deleting the bit stuff signal inserted in the encoder by inputting bits and performing addition at the lowest position of the internal 9-bit register, 10f is the arithmetic decoder 10. It is a timing control circuit that controls movement. Furthermore, 10g
Is a region detector which detects that the output of the A register exceeds 0 _X 1000 + 0 _X 0008, and 10h is a second AND which calculates a logical product of this output and the switching signal 112 which is the output of the first AND circuit 9. AND circuit, 10i is the second
When the AND circuit output of 1 is 1, it is a switcher that multiplies the area width signal 106 by 8.

Next, the operation of this embodiment will be described. In the decoding of the arithmetic code, if the relative coordinates that are the contents of the C register are Ci and the area width of the LPS at the time of the i-th prediction error symbol a _i is S, then Ci-1 <(Ai-1 − S ), A _i is MPS Ai = Ai-1-S Ci = Ci-1 Ci-1 ≧ (Ai-1-S) If _ai is LPS Ai = S Ci = Ci-1 (Ai-1-S) ).

Here, when the effective area Ai becomes 1/2 or less, the normalization process is performed to increase the calculation accuracy to 2
To the power of. At this time, the carry input signal 117 is input from the code register 10e from the least significant bit of Ci. Ai update value = Ai * 2 ^m (1/2 Ai update value ≦
1) Ci update value = Ci * 2 ^m

23 and 24 are timing charts showing an operation example of this embodiment. 23 shows a case where normal processing is performed as in FIG. 19, and FIG. 24 shows a case where batch processing is performed. The operations of creating the reference symbol pattern 102, creating and updating the order / predicted value are the same as those in the embodiment of FIG.

Next, in the case of normal processing, regarding the reproduction of the prediction error symbol a _i and the calculation of the effective area A _i and the relative coordinate Ci, first, in the timing control circuit 10f, as described above, Ci-1 and (Ai- 1-S) is performed to determine the symbol a _i (MPS or LPS), based on which Ai and Ci are calculated and the A registers 10a and C
It is set in the register 10c. This series of processing is performed in one cycle of the system clock. As a result of this calculation, when the effective area Ai becomes less than 1/2, the above normalization processing is performed in m clocks. At this time, when the contents of the lower 8 bits of the sign bit stored in the sign register 10e become eight consecutive "1" s, the normalized clock 118
Is temporarily stopped, 1 bit is input from the sign bit sequence 107, and addition is performed at the lowest position of the internal 9-bit register.

In the case of collective processing, that is, except for the pixels for which the restoration of the information source symbols has not been completed, the reference symbol patterns for all 8 consecutive encoding target pixels are "0" (the detection signal 109 is "1"). , And the order of the a11 “0” state is 16 (a11 “0” state order signal 110 is “1”), and the predicted value of the same state is “0” (a11 “0”).
The state prediction value signal 111 is “1”), and the effective area width 11
When 3 exceeds 0 _X 1000 + 0 _X 0008 (the area detector output 120 is "1"), "0 _X 0008" is used as the area width subtraction signal 122 by the switch 10i as in the case of FIG. Then, an arithmetic operation is performed on 8 consecutive symbols. This processing is performed in one cycle of the system clock as in FIG. As the information source symbol 101 restored at this time, 8 consecutive "0" s are output from the information source symbol switching unit 12 regardless of the output of the prediction inverse transformer 11.

Therefore, the decoding processing time T becomes T = 100 (Na / 8 + Nb) + 100 * (Na / 8 + Nb) + 100 * Nc + 100 * α (nsec) as in the case of encoding. It is possible to realize a significant improvement compared to the digitalization device.

Further, in the above embodiment, a special register is provided only in the state of all "0" as the reference symbol pattern to speed up the process. However, for example, the state of all the reference symbol patterns including "1" is included. Alternatively, a plurality of registers may be provided. Further, in the present embodiment, the batch processing is performed only when the order is the highest 16;
In the case of the fifth order, the effective area width 13 is 0 _X 1000 + 0 _X 10
The same batch processing may be performed by using 00 as the criterion of the area detector 5g.

Further, in the above embodiment, the order and the predicted value in a specific symbol pattern state are read from the order / predicted value memory 2. However, as in the first invention, a circuit for switching the order and the predicted value is provided. When all the reference symbol patterns are “0”, the order / prediction value memory 2 may not be read or updated.

Further, in the above embodiment, the method of adapting the order and the prediction value based on the number of MPS or LPS occurrences is shown. However, as described in the above IBM R & D information, the symbol at the time of normalization occurs. The same effect as described above can be obtained even if the method is applied to the method according to MPS or LPS.

[0101]

As described above, according to the first and second aspects of the invention, the memory for storing the predicted value and the order of the target symbol according to the reference symbol pattern and the reference symbol pattern are in a specific state. A detector for detecting the above, a register for storing the predicted value and the order in this specific state, and a selector for selecting the memory and the register based on the output of this detector, and corresponding to a specific reference symbol pattern. Regarding the order / predicted value table, a register with a high access speed is used without using a memory, so that an encoding / decoding device capable of significantly improving the encoding or decoding speed can be realized. ..

As described above, according to the third and fourth aspects of the present invention, the rewriting process for the prediction value and order signal of the target symbol to be coded read from the memory, or the immediately preceding target symbol to be coded is performed. A degree / prediction value register that stores the subsequent predicted value and the degree, and a detector that detects whether or not the reference symbol state for the symbol to be coded and the reference symbol state for the immediately preceding symbol match are provided. Since the order / prediction table search for a symbol and the area calculation of the number line for the symbol are performed in parallel, it is possible to realize an encoding / decoding device that can significantly improve encoding or decoding. it can.

As described above, according to the fifth and sixth aspects of the present invention, it is detected that the particular reference symbol pattern is continuous with the memory for storing the predicted value and order of the target symbol corresponding to the reference symbol pattern. Since a detector is provided to perform arithmetic operations on a plurality of symbols in a batch when a specific reference symbol pattern is continuous, encoding / decoding speed that can be greatly improved. A decoding device can be realized.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an encoding apparatus according to an embodiment of the first present invention.

FIG. 2 is a block configuration diagram showing an internal configuration of an arithmetic encoder in this embodiment.

FIG. 3 is a timing diagram showing an operation example according to the present embodiment.

FIG. 4 is a timing diagram showing an operation example according to the present embodiment.

FIG. 5 is a block configuration diagram of a decoding device showing an embodiment of the second invention.

FIG. 6 is a block configuration diagram showing an internal configuration of an arithmetic decoder in the present embodiment.

FIG. 7 is a timing diagram showing an operation example according to the present embodiment.

FIG. 8 is a timing diagram showing an operation example according to the present embodiment.

FIG. 9 is a block configuration diagram of an encoding apparatus according to an embodiment of the third invention.

10 is a block diagram showing an internal configuration of an arithmetic encoder in the embodiment of FIG.

FIG. 11 is a timing diagram showing an operation example according to the embodiment of FIG.

FIG. 12 is a block diagram of an encoding device according to another embodiment of the present invention.

FIG. 13 is a block diagram of a decoding device showing an embodiment of the fourth invention.

14 is a block diagram showing an internal configuration of an arithmetic decoder in the embodiment of FIG.

15 is a timing diagram showing an operation example according to the embodiment of FIG.

FIG. 16 is a block diagram of a decoding device according to another embodiment of the present invention.

FIG. 17 is a block configuration diagram of an encoding device according to an embodiment of the fifth invention.

18 is a block diagram showing an internal configuration of an arithmetic encoder in the embodiment of FIG.

19 is a timing diagram showing an operation example according to the embodiment of FIG.

20 is a timing diagram showing an operation example according to the embodiment of FIG.

FIG. 21 is a block diagram of a decoding device showing an embodiment of the sixth invention.

22 is a block diagram showing the internal structure of the arithmetic decoder in the embodiment of FIG. 21. FIG.

23 is a timing diagram showing an operation example according to the embodiment of FIG. 21. FIG.

FIG. 24 is a timing diagram showing another operation example according to the embodiment of FIG. 21.

FIG. 25 is a block diagram of a conventional encoding device.

FIG. 26 is a diagram showing positions of reference symbols used for encoding.

FIG. 27 is a diagram showing the contents of an order / predicted value table.

FIG. 28 is a diagram showing the contents of an area width table.

[Explanation of symbols]

 2nd order / predicted value memory 3 Prediction converter 5 Arithmetic encoder 6 Order / predicted value control circuit 7 Detector 8 Order / predicted value register 9, 12 Selector 10 Arithmetic decoder 11 Predictive inverse converter

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Tomohiro Kimura 5-1-1, Ofuna, Kamakura-shi, Kanagawa Mitsubishi Electric Corporation Communication Systems Laboratory (72) Fumitaka Ono 5-1-1, Ofuna, Kamakura, Kanagawa No. Mitsubishi Electric Corporation Communication Systems Laboratory

Claims (6)

[Claims] 1. When predicting a coding target symbol to be a coding prediction target from the states of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source and coding the prediction error signal In addition, a rewritable memory for storing the predicted value of the encoding target symbol from the state of the reference symbol and the order which is the identifier of the group classified by the predictive coincidence rate, and the identification of the state of the reference symbol of 1 or more A detector for detecting the state of the above, one or a plurality of registers for storing the predicted value and the order in the specific state, and a selection for selecting the memory and the register output based on the detector output. And the arithmetic encoder that encodes the prediction error signal based on the prediction value and order information output from the selector, and whether or not the above-mentioned symbols to be encoded are predictively matched and the result is checked. An encoding / decoding device comprising an order / prediction value control circuit for rewriting a prediction value and order in the reference symbol state according to the result. 2. A code obtained by predicting a decoding target symbol to be a decoding prediction target from the states of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source and coding the prediction error signal. When decoding a bit sequence, a rewritable memory that stores the predicted value of the decoding target symbol from the state of the reference symbol and the order that is the identifier of the group classified by the predictive matching rate, and the state of the reference symbol Based on the output of the detector, and a detector for detecting that one or a plurality of specific states are stored, one or a plurality of registers for storing predicted values and orders in the specific state. And a register that selects the register output, an arithmetic decoder that decodes the code bit sequence based on the order output from the selector, and whether or not the above decoding target symbols were predicted and matched. An encoding / decoding device comprising an order / prediction value control circuit for inspecting and rewriting a prediction value and order in the reference symbol state according to the result. 3. When a prediction target symbol is predicted from the states of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source and the prediction error signal is coded, each of the reference symbols is A rewritable memory that stores the predicted value of the encoding target symbol in the state and the order that is the identifier of the group classified by the predictive matching rate, the predicted value of the encoding target symbol read from the memory, and The order signal or the order / prediction value register that stores the predicted value and the order after the rewriting process with respect to the immediately preceding encoding target symbol and the encoding target symbol are inspected for prediction, and depending on the result. Order / prediction value control circuit for rewriting the prediction value and the order of the memory in the reference symbol state, and a reference symbol state for the symbol to be encoded. State and the reference symbol state for the immediately preceding symbol are detected, and the detector that updates the contents of the order / predicted value register according to the detection result and the predicted value output from the order / predicted value register・
An encoding / decoding device, comprising: an arithmetic encoder for encoding a prediction error signal based on order information. 4. A code obtained by predicting a decoding target symbol to be a decoding prediction target from the states of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source and coding the prediction error signal. When decoding a bit sequence, a rewritable memory that stores a predicted value of a decoding target symbol from a state of a reference symbol and an order that is an identifier of a group classified by a prediction matching rate, and the decoding target symbol And a prediction value control circuit for rewriting the prediction value and order of the memory in the reference symbol state according to the result, and the prediction value and order from this memory, or immediately before Register that stores the updated predicted value and degree for the decoding target symbol of, and the reference symbol state and the immediately preceding symbol for the decoding target symbol. A detector that detects whether or not the corresponding reference symbol states match, and a detector that follows the detection result; a selector that selectively outputs one set of predicted values and orders of memory outputs for a plurality of states; An encoding / decoding device comprising: an arithmetic decoder that decodes a coded bit sequence based on the predicted value / order information thus obtained. 5. A state of a reference symbol when a target symbol to be coded is predicted from the states of a plurality of reference symbols at predetermined positions in an output symbol sequence of an information source and the prediction error signal is coded. From the rewritable memory that stores the predicted value of the encoding target symbol and the order that is the identifier of the group classified by the predictive matching rate, and the state of the reference symbol with respect to a plurality of consecutive encoding target symbols is all specified. A detector that detects a number of symbols that are in a state and in which all the encoding target symbols are predictively matched, and a prediction converter that calculates a prediction error of the encoding target symbol based on the prediction value stored in the memory. , The order / predicted value for rewriting the predictive value and the order of the memory in the reference symbol state according to the result of checking whether or not the symbols to be encoded match prediction An encoding / decoding device comprising a control circuit and an arithmetic encoder for encoding a prediction error signal calculated by a prediction converter based on order information stored in the memory. 6. A code bit sequence obtained by predicting an encoding target symbol sequence from the states of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source and encoding the prediction error signal In this case, a rewritable memory that stores the predicted value of the decoding target symbol from the state of the reference symbol and the order that is the identifier of the group classified by the predictive matching rate, and a plurality of consecutive decoding target symbols are When it is assumed that the prediction matches, the state of the reference symbols for the plurality of decoding target symbols is all a specific state, and a code bit sequence based on the order information stored in the memory. An arithmetic decoder that decodes a prediction error signal to generate a prediction error signal, and a prediction that restores the decoding target symbol based on the prediction error signal and the prediction signal created by the arithmetic decoder An inverse transformer and an order / prediction value control circuit for checking whether or not the restored decoding target symbol matches prediction and rewriting the prediction value and order in the reference symbol state according to the result An encoding / decoding device characterized by: