JP3119025B2 - Encoding device and decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding / decoding device,
In particular, the present invention relates to an apparatus for encoding and decoding image information and the like.

[0002]

2. Description of the Related Art In coding a Markov information source, a symbol to be coded is predicted by a reference symbol which is a coded symbol for an output symbol sequence of the information source, and the prediction error signal is referred to as a reference symbol pattern. , Each prediction error signal is classified into several groups according to the predictive accuracy, and coding is performed using codes suitable for the respective groups. Here, the creation of the prediction error signal will be described below.
Predictive transformation and classification into groups are called integration, and group identifiers are called orders. Also, a prediction error signal to be encoded is referred to as a prediction error symbol.

[0003] The prediction conversion and order selection method include the following:
Japanese Patent Application Laid-Open No. 2-305225 discloses a technique for performing an adaptive process in order to cope with a local change in the statistical property of an information source. Regarding the encoding method of the prediction error symbol, the subtraction type arithmetic encoding method uses the IBM R & D information 198
November 2008, Volume 32, Issue 6 (IBM Journal)
of Research and Developmentmen
t, Vol. 32, no. 6, Nov., 1988) "Appearance of the basic principle of a binary arithmetic encoder for Q-coder".
(An overview of the basic
principal of the Q-Coder
adaptive-binary arith-me
Tic coder) and Japanese Patent Publication No. 2-58811. These are a type of number line display encoding method that maps a symbol sequence between 0.0 and 1.0 on a number line and encodes the coordinates as a code word. Is divided only by addition and subtraction.

[0004] Hereinafter, the process of prediction conversion, integration and encoding according to the prior art will be described with reference to the drawings. FIG. 14 is a block diagram of a conventional encoding device, and FIG. 15 is an internal configuration diagram of an arithmetic encoder therein. For simplicity, the information source is a binary image signal, and the reference symbol is 12 in FIG.
The number of pixels and the number of integration are 16.

In FIG. 14, reference numeral 1 denotes a reference symbol creator for selecting and outputting a reference symbol from a sequence of information source symbols 101, and 2 outputs an order 103 and a predicted value 104 of a target symbol from a reference symbol pattern 102 which is the output. The order / predicted value memory 3 is a prediction converter that creates the prediction error symbol 105 based on the predicted value 112 selected and stored in the order / predicted value register 8 described later.
An area width table for outputting the area width 106 of the arithmetic code based on the degree 111 selected and stored in the predicted value register 8;
5 is an arithmetic encoder, 6 is an order / predicted value control circuit that controls reading and updating of the order / predicted value memory, and 7 is a reference symbol pattern from the reference symbol pattern 102 to the immediately preceding symbol to be encoded and a symbol to be encoded. A detector 8 for detecting whether or not the reference symbol patterns match each other. Reference numeral 8 denotes an order 103 and a predicted value output 104 from the order / predicted value memory 2 or an order / predicted value control circuit 6.
Is an order / predicted value register for temporarily storing the update signal 108 from the CPU. Here, since the number of reference symbols is set to 12, the order / predicted value table (contents of the order / predicted value memory) requires 2 ¹² types as shown in FIG. The next numerical value is to be identified because the integration is made into 16 groups. Here, it is assumed that the higher the predictive accuracy is, the higher the order is.

FIG. 15 is a block diagram showing the internal configuration of the arithmetic encoder 5. In the figure, 5a is an A register for storing the effective area Ai on the number line, 5b is a subtractor for calculating the MPS area width 114, 5c is an LPS area width and M
A selector for selecting the area width of the PS and inputting it to the A register 5a; 5d, a C register for storing the lower bound value coordinates 116;
5e is an adder for calculating the C register value 117 in the case of LPS, 5f temporarily stores a carry output 118 which is an overflow (shift-out) signal of the C register, carries out a carry process when updating the C register 5d, and finally performs A code register 5g for creating a proper code sequence is a timing control circuit for controlling the operation of the arithmetic encoder 5.

Next, the operation will be described with reference to FIG.
The sequence of the symbol 101 (image signal) generated from the information source is stored in the reference symbol creator 1 and FIG.
6 are selected and output as the reference symbol pattern 102. The order / predicted value memory 2 outputs the predicted value 104 and the order 103 of the target symbol from the table contents shown in FIG.
3 information is the area width 106 in the area width table 4 shown in FIG.
Is converted and output. On the other hand, the generated symbol 101 is exclusive-ORed with the predicted value 112 by the predictive converter 3 to generate the predicted error symbol 105. Since the encoding target of this prediction error symbol is a binary image signal, 0 (MPS: More Probable Sy
mbol), 1 in case of mismatch (LPS: Less P)
(robable Symbol).

In the arithmetic encoder 5, the prediction error symbol 105 is mapped on a number line based on the area width 106 signal, and coding is executed. That is, the i-th symbol in the prediction error symbol sequence is a _i , and the LP at the i-th time is
Assuming that the mapping range (assigned area) of S is S, and the MPS area is below the effective area, the mapping range (effective area) Ai of the symbol series at the i-th time point and its lower-bound value coordinate Ci
Is Ai = Ai-1−S Ci = Ci−1 when the symbol a _i is MPS, and Ai = S Ci = Ci−1 + (Ai−1−S) when the symbol a _i is LPS.

If the effective area Ai becomes less than 1/2, the power is multiplied by 2 to increase the arithmetic precision. At this time, the overflow of the coordinate Ci (part beyond the decimal point)
The minute is output as a code bit sequence. Hereinafter, this exponentiation process is referred to as normalization. Ai update value = Ai * ^2m (1/2 <
Ai update value ≦ 1) Ci update value = Ci * 2 ^m

In arithmetic codes, it is known that by setting S as the appearance probability of LPS (= prediction error probability), highly efficient coding very close to the information source entropy can be performed. Therefore, arithmetic coding can be performed by the above processing by selecting an S value suitable for the predictive accuracy corresponding to the order. FIG. 18 is an example of a correspondence table between the order and the area width S. The value in the table, are shows information about those 2 ¹⁶ times the numerical value in the above formula. In this example, the area calculation on the number line is performed with 16-bit precision, and the A register and the C register each have a structure of 16 bits to the decimal.

Next, adaptive processing of prediction and integration will be described. As the adaptive processing method, a method of counting and controlling the number of consecutive MPSs and LPSs from an output symbol sequence, and a method in which the symbol when the above-mentioned normalization occurs is MPS or L
There is a method of controlling by PS. Here, the latter method will be described as an example. There degree and predicted value controller 6 with MPS output symbols of the prediction converter 3 during normalization L
It is determined whether it is PS.

In the case of LPS, the order / predicted value memory 2 subtracts 1 from the value of the order corresponding to the reference symbol pattern at that time. For example, if the order of the encoding target symbol X with respect to the reference symbol patterns A to L is 4 and the prediction value is 1 as shown in FIG. 17A, the order is 3 as shown in FIG. To This is because the prediction in the reference symbol state is deviated, and by lowering the order indicating the accuracy of the prediction, the information source that is the current encoding target is
This is the operation of adapting the order / predicted value. When the order reaches the lowest order and cannot be reduced any more, the predicted value is inverted. With this operation, a predicted value having an extremely poor hit rate is rewritten.

In the case of MPS, the order / predicted value memory 2 adds 1 to the value of the order corresponding to the reference symbol pattern at that time. For example, when the order of the encoding target symbol X with respect to the reference symbol patterns A to L is 4 as shown in FIG. 17A, the order is set to 5 as shown in FIG. 17C. This is because the prediction in the reference symbol state is correct, and the order / prediction value is adapted to the information source which is the current encoding target by increasing the order indicating the prediction accuracy. Operation. If the order has already reached the highest order, no addition is performed. When the prediction is very good due to this operation, the S value is reduced by increasing the order, and the code amount output from the arithmetic encoder 5 can be suppressed.

By the operation of the above adaptive processing, the order / predicted value control circuit 6 rewrites the order / predicted value table according to the nature of the information source, and can realize arithmetic coding with high coding efficiency.

Here, the processing operation of the encoding apparatus for each symbol will be described in detail with reference to FIG. In FIG. 19, C
, 1, C2, C3,... Indicate one cycle of the system clock. Also, in the figure, # 1, # 2, # 3... Indicate target symbols to be encoded. However, FIG.
# 1, # 2, and # 3 in the parentheses do not mean the target symbol itself, but indicate that various patterns and outputs described on the left side of the figure correspond to the target symbol. For example, in the target symbol pattern 102, #
.. Indicate the output of the reference symbol pattern corresponding to the target symbol # 1, and similarly, # 2 indicates the output of the reference symbol pattern corresponding to the target symbol # 2. ing.

As shown in FIG. 19, the system clock C
1, an information source symbol 101 is input, and a reference symbol pattern 102 is output from the reference symbol creator 1. At the same time, the order 103 and the predicted value 104 are output from the order / predicted value memory 2 at the system clock C1. Further, at the system clock C2, the order / predicted value register 8 outputs the order signal 1 of the encoding target symbol.
11 and the predicted value signal 112 are output, and the degree / predicted value memory 2 stores the order 1 for the next symbol to be encoded.
03 and the predicted value 104 are read using one cycle of the system clock. In the system clock C3,
The output for the symbol encoding is performed by the arithmetic encoder 5, and in parallel with the output of the codes from the A register and the C register, the order signal 111 and the prediction signal of the next symbol to be encoded are output. 112 is the order / predicted value register 8
And the order 103 and the predicted value 104 for the next encoding target symbol are read out from the order / predicted value memory 2. Thus, the encoding device is configured to perform the processing in a pipeline manner.

Next, a description will be given of a case where normalization and an update of the order / predicted value are not performed when the target symbol is coded, and a case where there is the update. (1) Case where normalization and degree / prediction value update are not performed. For example, as in the case of # 1, # 3, # 4, and # 6 in FIG. Move to the area / coordinate calculation of. (2) Case where normalization and degree / predicted value update are performed For example, as in the case of # 2 and # 5 in FIG. Perform the conversion.

The contents of the order / predicted value memory 2 are updated by the reference pattern 109 (the reference symbol pattern 102 delayed by one symbol) for the symbol output from the detector 7 and the order / predicted value control circuit 6. Is performed based on the update signal 108 of FIG. At this time, if the reference symbol pattern 102 (the signal for the next encoding target symbol) matches the reference pattern 109 for the encoding target symbol, the contents of the order / predicted value register are also updated. These contents are updated in one cycle of the system clock.

The normalization is carried out in one system clock cycle per bit by left shifting in parallel with this updating operation. A specific example in the case where the normalization and the update of the degree / predicted value are performed will be described. In the system clock C3, a region / coordinate calculation is performed on the encoding target symbol # 2. When the effective area is reduced to ２ or less as a result of the calculation, normalization processing is performed. Similarly, the above-described adaptive processing is performed. That is, in order to perform the normalization processing, the A register and the C register are shifted by one bit in the system clock C4, and the sign is output. In the adaptive processing, as shown in FIGS. 17B and 17C, the order corresponding to the reference symbol pattern referred to by the encoding target symbol # 2 is changed. Alternatively, the predicted value is changed. The order and prediction value referred to by the encoding target symbol # 2 in the degree / prediction value memory 2 thus updated are shown as # 2 'in FIG.

After completion of these two operations, the operation proceeds to the calculation of the area and coordinates of the next symbol to be encoded. In the system clock C5, the calculation of the next symbol to be encoded is performed, but the next symbol to be encoded # 3
Are used as the encoding target symbol #
If the reference symbol pattern of the encoding target symbol # 3 does not match the reference symbol pattern of the encoding target symbol # 3, the order and the prediction value obtained from the reference symbol pattern of the encoding target symbol # 3 are used. On the other hand, when the reference symbol pattern of the encoding target symbol # 2 matches the reference symbol pattern of the encoding target symbol # 3, the order and the prediction value updated by the above-described adaptive processing (in FIG.
Predicted value memory output # 2 ′) is used.

In the case of the symbol to be encoded # 5, as a result of the operation of the system clock C7, a two-bit shift is performed for normalization processing. Therefore, the two-bit shift normalization is performed in the system clocks C8 and C9. Processing is performed. Also, regarding the order and prediction value of the encoding target symbol # 6 to be encoded next, when the reference symbol patterns of the encoding target symbol # 5 and the encoding target symbol # 6 do not match, the system clock C7 remains unchanged. Are used in the system clock C10. If the reference symbol patterns of the encoding target symbol # 5 and the encoding target symbol # 6 match, the order and the prediction value of the encoding target symbol # 5 are used. The order processing
Since the contents of the predicted value memory 2 have been updated, the updated order and predicted value (indicated by # 5 ′ of the order / predicted value memory output in the figure) are used in the system clock C10. The normalization process is performed as described above, and one additional cycle of the system clock is used every time a 1-bit code is output. The number of this additional system clock will be equal to the number of sign bits.

As is clear from the above description, the encoding processing time T of this encoding apparatus is as follows: when the total number of symbols is Na and the number of code bits is Nc, the system clock is 10 MHz.
In the case of Z, T = 100 + 100 * Na + 100 * Nc (nse
c) The first item 100 in the above equation indicates the time of the system clock C1 in FIG. In addition, 1 of the second item
Since 00 × Na takes 100 nsec per symbol, it indicates the time for processing all symbols. Also, the third
The item 100 × Nc indicates the additional time required for the normalization process in FIG. 19, that is, the process of outputting the sign bit. For example, in FIG. 19, three shifts of the system clocks C4, C8, and C9 are performed, so three code bits are output. In this example, 100 × 3
= 300 nsec. Therefore, assuming that the compression rate is 30 as an A4 size original having a standard resolution of 8 pixels / mm in horizontal direction and 7.7 lines / mm in vertical direction, Na = 1728 * 2376 Nc = 1728 * 2376 * (1/30) The encoding processing time T is about 0.4 seconds.

[0023]

As described above, in the conventional apparatus, reference symbol patterns are created for all symbols, the order / predicted value table is searched, and the area of the number line is calculated. As a result, the order / predicted value table is updated and normalized, and the encoding / decoding process is slowed down due to the nature of the image signal. In particular, in an organized dither image or a pseudo halftone image binarized by an error diffusion method, an A4 size original is horizontally 8 pixels / pixel.
mm, the encoding time is about 0.7 to 1 second when encoding at a resolution of 7.7 lines / mm, which is about twice as long as a normal character image.

The present invention has been made to solve the above problems, and has as its object to provide an encoding / decoding device capable of greatly increasing the processing speed.

[0025]

The encoding apparatus according to the first aspect of the present invention estimates the symbol appearance probability from the output symbol sequence of the information source, performs effective area division according to the estimation, and divides this symbol sequence. In arithmetic coding, a first register for storing an effective area on a number line, a first arithmetic unit for calculating an area width of the MPS, and a second register for storing a boundary value of the effective area on the number line A second calculating means for calculating a boundary value between the area corresponding to the LPS and the MPS area, and a first selecting means for selecting a new effective area width depending on whether the generated symbol is the MPS or the LPS. Second selection means for selecting a boundary value of a new effective area; bit position detection means for receiving the output of the first selection means and detecting the position of the most significant "1" or "0"; The first according to the output A first sheet cover for outputting a first register input value shifts the-option means outputs, likewise the overflowed data from the second selecting means receives the output second register input value and the second register Output second
And sheet lid, those having a code generating means for generating a code output by receiving the data output overflowed from the second register from the second sheet cover.

The encoding apparatus according to the second invention has an F
It has code generation means having an IFO memory.

The decoding apparatus according to the third aspect of the present invention estimates the symbol appearance probability from the output symbol sequence of the information source, performs effective area division in accordance with the estimation, and arithmetically codes the symbol sequence. A first register for storing an effective area on a number line when decoding a sequence;
First calculating means for calculating an area width of a symbol (dominant symbol: MPS) which is assumed to occur at a high frequency, a second register for storing a boundary value of an effective area on a number line, and a second register A region of a symbol (recessive symbol: LPS) which is assumed to have a low occurrence frequency from the output and the MPS
By subtracting the boundary value from the area, the symbol is MPS or LP
S, and the symbol is MP
First to select a new effective area width depending on whether it is S or LPS
Selecting means, a second selecting means for also selecting a new effective area boundary value, and a bit position detection for detecting the position of the most significant "1" or "0" in response to the output of the first selecting means. means and includes a first sheet cover to be output as the first register input value by shifting the first selection means output in accordance with the detection means output, likewise the second selection means output and the code reading means outputs the later a second sheet cover for outputting a second register input value undergoing receives the entered code data sequence, a second sheet cover the code sequence number of necessary bits as a lower bit signal of the second register And a code reading means for outputting the data to the device.

The decoding apparatus according to the fourth aspect of the present invention
A code reading means having an IFO memory is provided.

The encoding apparatus according to the fifth aspect of the present invention predicts a symbol to be encoded from states of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source, and generates a prediction error signal. when encoding, and write simultaneously operable memory read stores a degree which is an identifier of the group are classified predicted value of the coding target symbol in each state of the reference symbol and the predictive coincidence rate,
An order / predicted value control circuit for checking whether or not the encoding target symbol matches the prediction and rewriting the predicted value and the order in the reference symbol state according to the result; and the encoding target read out from the memory. An order / predicted value register for storing the predicted value and the order signal of the symbol or the predicted value and the order after the rewriting process for the immediately preceding encoding target symbol; a reference symbol state for the encoding target symbol and a reference for the immediately preceding symbol; A detector for detecting whether or not the symbol state matches, and an arithmetic encoder for encoding a prediction error signal based on the predicted value / order information output from the degree / predicted value register. Things.

The decoding apparatus according to the sixth aspect of the present invention predicts a symbol to be decoded from states of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source, and outputs a prediction error signal. Simultaneous writing and reading that stores the predicted value of the decoding target symbol and the order that is the identifier of the group classified based on the prediction matching rate from the state of the reference symbol when decoding the encoded code bit sequence
Such a memory, and the order and prediction value control circuit for rewriting the predicted value and degree of the reference symbol state in response to the decoded symbol to inspect whether the match prediction result, decoded preceding A selector for selecting and outputting a set of predicted values and orders from memory outputs for a plurality of states according to a reproduced signal value of a symbol; and a predicted value and orders from the memory, or a selector for the immediately preceding symbol to be decoded. A register for storing the updated predicted value and degree, a detector for detecting whether a reference symbol state for the symbol to be decoded matches the reference symbol state for the immediately preceding symbol, and a detector for detecting whether the selected predicted value An arithmetic decoder for decoding the code bit sequence based on the degree information.

[0031]

[Action] coding apparatus according to the first invention, by the speed of the normalization operation by using the first and second sheet cover, and improves the encoding rate.

The encoding apparatus according to the second aspect of the present invention reduces the interruption of the encoding operation related to the code output by buffering the code output by using the FIFO for the code generation means to reduce the encoding speed. It is to improve.

The decoding apparatus according to the third invention, by the speed of the normalization operation by using the first and second sheet cover, is intended to improve the decoding speed.

The decoding apparatus according to the fourth aspect of the present invention reduces the interruption of the decoding operation related to the code input by buffering the code input by using the FIFO for the code reading means to reduce the decoding speed. It is to improve.

The encoding device according to the fifth aspect of the present invention improves the encoding speed by configuring the memory for storing the order / predicted value with a plurality of ports and performing the reading and writing operations simultaneously. .

The decoding device according to the sixth aspect of the present invention improves the decoding speed by configuring the memory for storing the order / predicted value with a plurality of ports and performing the reading and writing operations simultaneously. .

[0037]

[Embodiment 1] Hereinafter, the present invention will be described based on illustrated embodiments. The encoding device block configuration of the present embodiment includes:
14 is the same as the conventional device of FIG.
The order / predicted value memory 2 has a high speed, a write operation can be performed in the first half cycle of the system clock, and a read operation can be performed in the second half cycle, and the internal configuration of the arithmetic encoder 5 is different. That is the point.

FIG. 1 is a block diagram showing the internal configuration of the arithmetic encoder 5 in the present embodiment. The difference from the arithmetic encoder of the conventional encoder shown in FIG.
A bit position detector 5h for receiving the output of the area width selector 5c to detect the position of the most significant 1 and a selector 5c for the number of bits corresponding to the output normalized bit number signal 120.
The first barrel shifter 5i that shifts the output to the left and inputs 121 to the A register 5a, and the C register 5d output 116
And a selector 5j for switching the C register value 117 in the case of LPS and an output 122 of the selector 5j is shifted leftward by the number of bits corresponding to the normalized bit number signal 120, and an overflow 124 is output to the code register 5f. The addition of the second barrel shifter 5k for inputting the lower bit 123 to the C register 5d;
Instead of the conventional 1-bit carry output as f input,
Overflow signal 12 from second barrel shifter 5k
4 and that the normalized bit number signal 120 from the bit position detector 5h is input.

FIG. 2 is a diagram showing the internal structure of the code register 5f. 5f1 is a barrel shifter for shifting the overflow signal by a predetermined number of bits, 5f2 receives the normalized bit number signal 120, and shift-adds the overflow signal. A digit control circuit for controlling the number of bits 126, 5f3 is an adder for adding and adding an overflow signal to the lower part of the preceding bit sequence, and 5f4 is a byte pack register for packing the overflow signal sequence into bytes, 5f5.
Is the carry 130 from the byte pack register 5f4.
The overflow detector 5f6 detects "0x" in hexadecimal notation from the output 129 of the byte pack register 5f4.
ff pattern detection / counter for detecting and counting ff ″, 5
f7 is the output 129 from the byte pack register 5f4
Is temporarily stored, and the overflow detector 5f5
5f8 is a ff data generator that outputs "0xff" in hexadecimal notation.
Is a 00 data generator that also outputs “0x00”, 5
f10 is the buffer register 5f7 and the ff data generator 5
f8,00 This is a selector for selecting data from the data generator 5f9 to create a code data sequence.

Next, the operation of this embodiment will be described with reference to FIG. 3 is that the order / predicted value memory 2 has a high speed, so that reading from the order / predicted value memory is possible in the latter half of the system clock. For example, when reading the encoding target symbol # 1 from the order / predicted value memory 2, the reading is performed using the latter half of the system clock C1. Similarly, when reading the encoding target symbol # 2, the symbol is read using the latter half of the system clock C2. If the calculation results in a normalization process and an order / predicted value changing process, the order / predicted value memory can be updated using the first half of the system clock. For example, as a result of performing the arithmetic processing of the encoding target symbol # 2 at the system clock C3, the 1-bit shift normalization processing occurs, and the order / prediction value is updated, the first half of the system clock C4 is updated. The order / predicted value memory 2 can be used to perform an update process. Similarly, when the normalization process of the 2-bit shift and the update process of the degree / predicted value occur in the system clock C6 as a result of the arithmetic process of the encoding target symbol # 5, the system clock C7
Can be updated in the order / predicted value memory 2 in the first half of the process. Now, assuming that the degree signal 111 and the predicted value signal 112 of the encoding target symbol are output from the degree / predicted value register 8, the degree / predicted value signal 112 is output in parallel with the processing for the symbol encoding described below. In the predicted value memory 2, the order and predicted value for the next symbol to be encoded are read using the second half cycle of the system clock. (1) When there is no update of the normalization and the order / predicted value For example, as in the case of # 1, # 3, # 4, and # 6 in FIG.
After the calculation of the area and the coordinates, the process proceeds to the area / coordinate calculation of the next encoding target symbol. (2) When the normalization and the update of the order / predicted value are performed For example, as in the case of # 2 and # 5 in FIG. Let's move on to the symbol processing.

Since the barrel shifter can perform the shift processing of a plurality of bits in one clock, even in the case of the normalization processing in which the shift processing of a plurality of bits is performed, the normalization processing can be completed in one clock. The operation of this normalization processing will be described later. The update of the contents of the order / predicted value memory 2 is performed by the order / predicted value control circuit 6 and the detector 7 in the first half of the cycle of the system clock of the cycle in which the next symbol area and coordinate calculation are performed.

Next, a specific operation will be described with reference to FIG. If it is determined in the system clock C3 that the normalization process and the order / prediction value update process (adaptive process) are performed as a result of the calculation process of the encoding target symbol # 2, the first half of the system clock C4 is performed. Is used to update the order / predicted value memory. In the system clock C4, when determining the order and prediction value of the encoding target symbol # 3, there may be cases where the reference symbol patterns of the encoding target symbol # 2 and the encoding target symbol # 3 match or not. If the reference symbol patterns of the encoding target symbol # 2 and the encoding target symbol # 3 do not match, the order of the encoding target symbol # 3 read from the order / predicted value memory 2 at the time of the system clock C3 and The prediction value is output as the order and prediction value of the encoding target symbol # 3 at the system clock C4. On the other hand, when the reference symbol pattern of the encoding target symbol # 2 matches the reference symbol pattern of the encoding target symbol # 3, the normalization processing and the order / prediction value update processing occur after the encoding processing of the encoding target symbol # 2. Therefore, the updated order and predicted value must be used. The process of updating the order and the predicted value is performed in the first half of the system clock C4. Therefore, as the order and predicted value from the order / predicted value register 8, the order and predicted value updated in the first half of the system clock C4 are used as the order and predicted value of the encoding target symbol. The degree / predicted value register 8 is updated in parallel with the updating of the degree / predicted value memory 2 in the first half of the system clock C4, thereby encoding the degree / predicted value register 8 in the first half of the system clock C4. The order and prediction value of the target symbol # 2 can be updated at the same time. System clock C4
In, by using the updated order and predicted value of the order / predicted value register 8 as the order and predicted value of the encoding target symbol # 3, the newly updated order and predicted value can be used correctly.

In the symbol to be encoded # 5,
Even when 2-bit normalization processing and degree / prediction value change processing occur, the same normalization processing and degree / prediction value update processing as in the above-described encoding target symbol # 2 are performed. Further, when determining the order and prediction value for the encoding target symbol # 6, as described above, the encoding target symbol # 6
If the reference symbol patterns of # 2 and # 3 match or do not match, the updated new order and predicted value are used if they match, and if they do not match, the order read for encoding target symbol # 6 And the predicted value are used as they are.

As described above, in this embodiment, the order / predicted value memory 2 is faster than in the prior art, so that writing and reading can be performed using the first and second halves of the system clock. A big feature is what you can do. Also, a great feature is that even when there are a plurality of bits of processing using a barrel shifter in the shift processing at the time of normalization, it can be performed with one clock. As described above, in the conventional apparatus, the system clock is required for performing the shift processing. On the other hand, in this embodiment, even when the number of shift bits is plural, it is possible to complete the processing in one clock, and the normalization is performed. There is no need to delay other pipelined processing for processing. In addition, since the normalization process and the order / predicted value updating process are performed in the latter part of the arithmetic encoder of the pipelined apparatus, it is determined whether or not the order and the predicted value are updated. The order / predicted value memory 2 can be accessed at a high speed in order to reflect the new order and predicted value obtained on the encoding target symbol to be encoded next.

Next, the operation of the arithmetic encoder 5 will be described with reference to FIG. Arithmetic encoder 5 receives region width 106 and prediction error symbol 105 and outputs code 107. The prediction error symbol 105 is one of LPS (1) / MPS (0), and in the case of LPS, the selector 5c
3 is connected. And the selector 5j selects S6 and S4. On the other hand, when the prediction error symbol 105 is the MPS, the selector 5c connects S2 and S3. The selector 5j connects S5 and S6. When the selector 5c connects S1 and S3, the area width 106 is input and output to the first barrel shifter 5i. On the other hand, when S2 and S3 are connected, the remaining MPS area width 114 obtained by subtracting the area width 106 from the area width in the A register 5a is used as the first barrel shifter 5
Output to i.

The bit position detector 5h monitors the output 115 from the selector and detects the most significant bit position of the output 115. For example, when bit “1” is detected in the second digit, 1 is output as a normalized bit number signal. When bit 1 is detected in the third digit, 2 is output as a normalized bit number signal. When the normalized bit number signal indicates 1, the shift number is 1, and when the normalized bit number signal is 2, the shift number is 2. The normalized bit number signal 120 is input to the first barrel shifter 5i and the second barrel shifter 5k, and shifts the signals output from the selectors 5c and 5j. Thus, the normalization process is completed in one clock. If S4 and S6 are connected in the selector 5j, the MPS area width 114 is added to the value in the C register 5d to calculate a new LPSC register value, and this is calculated as the second LPSC register value.
To the barrel shifter 5k. On the other hand, if the selector 5j is S5
When S6 and S6 are connected, the C register output 116 output from the C register 5d is selected and output to the second barrel shifter 5k.

Next, the operation of the code register 5f will be described with reference to FIG. The sign register 5f receives the overflow signal 124 from the second barrel shifter 5k and outputs a sign 107. In outputting the code 107 from the overflow signal 124, the normalized bit signal 120 is input, and the encoding stop signal 125 is output to adjust the encoding timing. As previously mentioned,
When 2 bits of the overflow signal 124 are input, the normalized bit number signal 120 inputs 2 as the number of bits to be shifted. The digit control circuit 5f2 shifts the barrel shifter 5f1 based on the value of the normalized bit number signal 120 and takes in the overflow signal 124. If the barrel shifter 5f1 cannot shift by the number of bits based on the normalized bit number signal 120, the digit control circuit 5f2 outputs an encoding stop signal 125. The encoding stop signal 125 is input to the timing control circuit 5g shown in FIG. The timing control circuit 5g outputs the encoding stop signal 1
When 25 is input, the encoding operation of the arithmetic encoder 5 is temporarily stopped. The digit control circuit that has output the encoding stop signal 125 performs the remaining shift operation of the barrel shifter 5f1 while the arithmetic encoder 5 has stopped the next operation, so that the next overflow signal 124 in the code register 5f is output.
The operation of the sign register 5f is continued until it becomes possible to input.

The operation of the sign register 5f during normalization is as follows. (A) Overflow signal 124 from C register 5d
Is added to the position immediately below the already processed overflow signal. However, when the overflow signal is larger than the number of normalized bits (only one bit at maximum), the most significant bit is added to the least significant bit of the immediately preceding overflow signal. (B) When the overflow signal cannot be added to the byte pack register at once, the output from the byte pack register shown in (c) below is performed, and the same addition operation is performed until the least significant bit is stored in the byte pack register. repeat. (C) When data is stored in the byte pack register 5f4 up to the byte boundary, the ff pattern detection / counter 5f
6, the following processing is performed. (C-1) When the data of the byte pack register 5f4 exceeds “0xff”: 1 is added to the content of the buffer register 5f7 which has been already stored (detected by the overflow detector), and is added via the selector 5f10. After the code output, "0
"0x00" is sign-output by the 00 data generator 5f9 by the number of count values of "xff". Thereafter, the lower 8 bits of the byte pack register 5f4 are read and output to the buffer register 5f7. When the data of the register 5f4 is "0xff", the count value of "0xff" is incremented by 1. (c-3) When the data of the byte pack register 5f4 is less than "0xff" Contents of the buffer register 5f7 already stored. Is output as a code through the selector 5f10, and then "0xff" is code-output by the ff data generator 5f8 by the number of counts of "0xff" .Then, the byte pack register 5f4 is read out and stored in the buffer register 5f7. By these processes, so-called pure output is output.
Is performed.

As is clear from the above description, the encoding processing time T of this encoding apparatus is such that when the total number of symbols is Na and the number of code bits is Nc, the system clock is 10 MHz.
In the case of Z, T = 100 + 100 * Na + α (nse
c) Here, α represents the overflow signal 124 of a plurality of bits sent from the C register 5d.
At the time f, the next overflow signal is generated while the data is packed into 8 bits and output, so that the calculation of the area of the next coded symbol is awaited. This occurs when the overflow signal 124 exceeds 8 bits. Therefore, a standard resolution of 8 pixels / mm (horizontal) and 7.7 lines / mm (vertical) for an A4 size original with a compression ratio of 30
Assuming that, the encoding processing time T is about 0.4 seconds, and also about 0.4 seconds for an extremely complicated image such as an error diffusion image even if the compression ratio is 1.5. Here, α is α = 100 * Nc * (1/16).

On the other hand, in the conventional apparatus of FIG. 14, when the compression ratio is 1.5, it takes about 0.7 seconds.

Embodiment 2 FIG. Next, FIG. 4 shows a block configuration of an arithmetic encoder of an encoding apparatus according to another embodiment of the present invention. The difference between this embodiment and the embodiment of FIG. 1 is that a FIFO for storing the overflow signal 124 and the normalized bit number signal 120 is added to the first stage of the code register 5f.

According to the arithmetic coding, since the coding according to the nature of the information source is performed, the compression ratio exceeds 1 except for the transitional part, and the processing of the code register 5f requires a time lag. Since the processing of 8 bits can be performed in one clock, the stop of the area calculation is not required by the FIFO of about 16 stages (that is, α = 0), and the ultra-high speed / constant speed required for the digital copying machine or the like is required. An encoder can be realized.

Embodiment 3 FIG. Next, FIG. 5 shows a block configuration of an encoding apparatus according to another embodiment of the present invention. In the drawing, the difference from the block diagram in the above-described embodiment is that
The predicted value memory 2 has a two-port configuration, and the reference symbol pattern 102 and the update reference symbol pattern signal 109 are monitored in place of the detector 7, and the update signal 1
If both patterns match when 08 occurs, a two-port control unit 9 and an access prohibition circuit 10 for stopping access to the order / predicted value memory for the next symbol are added.

FIG. 6 shows an example of the encoding operation in this embodiment.
Here, the arithmetic encoder shown in FIG. 1 is used. The same processing as described above can be performed by a two-port memory having half the access speed.

Next, this specific example will be described with reference to FIG. As a result of the arithmetic processing of the encoding target symbol # 2 at the system clock C3, the normalization processing and the order / prediction value update processing (adaptive processing) are performed. System clock C
In No. 4, the order and the prediction value used for the encoding target symbol # 2 are updated in order to update the degree and the prediction value.
The write operation to the order / predicted value memory 2 is performed in parallel with the reading of the order / predicted value memory for the encoding target symbol # 4 at the system clock C4.
However, if the reference symbol pattern of the encoding target symbol # 2 and the encoding target symbol # 4 are the same, the order
Since writing to and reading from the predicted value memory 2 compete with each other, even when the order / predicted value memory 2 is a two-port memory, one of the accesses must be prohibited. The two-port control unit 9 instructs the access prohibition circuit 10 to prohibit access when the reference symbol pattern of the encoding target symbol # 2 and the encoding target symbol # 4 are the same. The access prohibition circuit 10 prohibits reading of the order / predicted value memory for the encoding target symbol # 4. Even when the reading of the order and prediction value memory for the encoding target symbol # 4 is prohibited, the order and prediction value are updated by the encoding target symbol # 2, so that the order and prediction value memory 2 and the order The encoding target symbol # 2 of the prediction value register 8 (that is, the encoding target symbol #
The reference symbol pattern of 4) can be used as an updated new value.

When the reference symbol patterns of the symbol to be encoded # 2 and the symbol to be encoded # 4 do not match at the system clock C4, the writing process to the degree / predicted value memory and the reading process are performed at different addresses. Therefore, reading and writing are performed simultaneously in parallel.
In the system clock C5, the encoding target symbol #
The order and predicted value set in the order / predicted value register 8 are used in the system clock C4 as the order and predicted value of 4. That is, when the encoding target symbol # 2 and the encoding target symbol # 4 do not match, the order and prediction value read from the order / prediction value memory 2 are used as the order and prediction value of the encoding target symbol # 4. Used. On the other hand, when the reference symbol pattern of the encoding target symbol # 2 matches the reference symbol pattern of the encoding target symbol # 4, the access is prohibited by the access prohibition circuit 10, so that reading from the order and prediction value memories is not performed, and the order The new order and predicted value updated by the predicted value control circuit 6 are used as the order and predicted value of the encoding target symbol # 4.

When the normalization processing and the update processing to the degree / predicted value occur in the encoding target symbol # 5, the encoding target symbol # 7 is also processed by the above-described processing.
Is determined and the predicted value is determined.

Embodiment 4 FIG. Next, FIG. 7 shows a block configuration of a decoding apparatus according to another embodiment of the present invention. In the figure, reference numeral 11 denotes an area width signal
Arithmetic decoder that reproduces the prediction error symbol 105 based on
Reference numeral 12 denotes a prediction inverse transformer that performs an exclusive OR operation of the prediction error symbol 105 and the prediction value 112 to reproduce the information source symbol 101. Reference numeral 2 denotes a reference symbol pattern of 11 pixels excluding A among the reference pixels shown in FIG. 16, and the order and prediction value signals (103a, 104a, 103b, and 104, respectively) for two states where A is 1 and 0
b) is an order / predicted value memory that outputs
Is a register that receives this output and stores two types of order and prediction values. A selector 13 selects one of two types of order and a predicted value in accordance with the immediately preceding information source symbol 101 reproduced by the predictive inverse converter 12, and updates from the order / predicted value control circuit 6. Upon receiving the signal 108, the reference pixel A shown in FIG. 16 stores an order / predicted value memory 2 of either 1 or 0 according to the reproduced information source symbol.
Selection update signal 108a and second selection update signal 1 for updating the contents of
08b is created.

FIG. 8 is a block diagram showing the internal configuration of the arithmetic decoder 11, wherein reference numeral 11a denotes an effective area Ai on a number line.
A, 11b is a subtractor for calculating the MPS area width 114, 11c is an LPS area width 106 and the MPS
A selector for selecting the area width 114, a bit position detector 11d for receiving the selector output 115 and detecting the position of the most significant 1 and a selector 11e for selecting the output 115 of the selector 11c by the number of bits corresponding to the output 120. A first barrel shifter that shifts to the left, 11f is a C register for storing lower bound value coordinates,
1g is a subtractor for calculating a C register value 117 in the case of LPS, and 11h is a subtractor for calculating the C register value 117 and C in the case of LPS.
A selector 11i for selecting a register output 116 is provided below a sign register 11j below this switch output 122.
The second barrel shifter 11j for adding the lower bit input 140 from the code data 1 sent from the
Code register for inputting 07 to the C register 11f via the second barrel shifter 11i by predetermined bits,
1k is a timing control circuit for controlling the operation of the arithmetic decoder 11.

FIG. 9 is a block diagram showing the internal structure of the code register 11j. 11j1 to 11j3 are buffer registers for temporarily storing code data, and 11j4 is the lower bit 1 input from the code register output to the C register.
The barrel shifter 11j5 is a digit control circuit for controlling the number of bits 126 to be shifted by the barrel shifter.

Next, the operation of this embodiment will be described. In arithmetic code decoding, Ci-1 <(Ai-1-S), where Ci is the relative coordinate, which is the content of the C register, and S is the area width of the LPS at the i-th prediction error symbol _ai. ) if a _i is MPS Ai = Ai-1 - S Ci = Ci-1 Ci-1 ≧ (Ai-1 - S) if a _i is LPS Ai = S Ci = Ci- 1 - (Ai-1 - S)

Here, when the effective area Ai is reduced to 以下 or less, the normalization processing is performed in order to increase the calculation accuracy.
To the power of. At this time, n-bit code data is input from the code register 11j at the least significant position of Ci. Ai update value = Ai * 2 ^m (1/2 <A
i update value ≦ 1) Ci update value = Ci * 2 ^m

FIG. 10 is a timing chart showing an operation example of this embodiment. First, in each system clock, the orders 103a, 103b, and 103 for two states where A is 1 and 0 based on the reference symbol pattern of 11 pixels excluding A among the reference pixels in FIG. The predicted values 104a and 104b are read from the memory 2 and stored in the register 8. These processes are performed on the system clock 1
Perform at the time of the cycle. Thereafter, one of the two types of order and the predicted value is selected based on the value of A, which is the information source symbol reproduced immediately before, and the reproduction of the information source symbol and the order
Update the predicted value.

The reproduction of the prediction error symbol a _i , the calculation of the effective area Ai and the relative coordinates Ci, and the update of the order / predicted value are performed by the following operations. (1) First, the timing control circuit 1 inside the arithmetic decoder 11
At 1k, according to the polarity of the LPSC register value signal 117, the symbol _ai is determined (MPS or LPS) by comparing Ci-1 and (Ai-1-S) as described above. (2) When Normalization and Degree / Update of Predicted Value are not Performed As in the case of decoding target symbols # 1, # 3, # 4, and # 6 in FIG. 10, Ai and Ci are calculated and the A register 11a is calculated.
And the C register 11f. A series of processes (1) and (2) are performed in one cycle of the system clock. (3) When Normalization and Degree / Predicted Value Update are Performed As shown in FIG. 10, decoding target symbols # 2, # 5, and #
In the case where the effective area Ai is less than の as a result of the calculation of Ai and Ci as in the case of 7, the bit position detector 11d
The normalization process corresponding to the number of bits indicated by is performed.
Here, the bit shift / normalization operation by the barrel shifters 11e and 11i is performed within the same clock cycle as the process (1), and the process proceeds to the next symbol. In this embodiment, it is also assumed that the order / predicted value memory 2 is capable of processing at a higher speed than the conventional one.

The order / predicted value memory is updated as shown by the system clocks C3, C6 and C8 in FIG.
This is performed by the predicted value control circuit 6 and the detector 7 in the first half cycle of the system clock. As described above, this decoding apparatus is characterized in that the normalization processing can be performed within one system clock by using the barrel shifter. Also, since the normalization operation can be performed within one clock cycle by using the barrel shifter, the update of the order / predicted value memory is performed at a high speed. In this example, an example is shown in which writing to the order / predicted value memory 2 is performed in the first half of the system clock, and reading from the order / predicted value memory 2 is performed in the second half of the system clock.

When the order / predicted value is updated, an update signal is output from the order / predicted value control circuit 6, and the selector 13 changes the reference pixel A to 1 to 0 based on the value of the information source symbol reproduced immediately before. Corresponding selection update signal (108a, 108b)
Is generated, and the contents of the order / predicted value memory 2 are updated. At this time, the order / predicted value memory 2 read immediately before
Is the reference symbol pattern 1 for updating.
If the value matches with 09, the contents of the degree / predicted value register 8 are updated at the same time.

The operation of the sign register 11j at the time of normalization is as follows.
It is as follows. (A) From the unprocessed code bit sequence already shown at the position from the top of the barrel shifter 11j4, the data is read out by the number of normalized bits and set to the lower order of the C register 11f via the barrel shifter 11i. (B) As a result of this reading, the third buffer register 11
When j3 has no unprocessed code bits, new code data is input and stored in the first buffer register 11j1, and the first and second buffer registers 11j2, 11j2,.
The contents of 11j3 are transferred to the second and third buffer registers 11j3 and 11j4, respectively. (C) Second and third buffer registers 11j2, 11j
If there are no more unprocessed code bits in 3, another one byte of code data will be input similarly.

Therefore, the decoding processing time T is T = 100 + 100 * Na + α (nse
c) In this embodiment, a great improvement can be realized as compared with the decoding device according to the prior art.

Embodiment 5 FIG. FIG. 11 shows a block configuration of a code register 11j of an arithmetic decoder according to another embodiment. This embodiment is different from the embodiment shown in FIG. 9 in that a word converter 11j6 for forming code data input in units of bytes for every two bytes into a word structure and a FIFO memory 11j7 for temporarily storing the same are added. That is, the first and second buffer registers have been deleted and the third buffer register 11j3 has a word configuration.

With this configuration, the next 16-bit data can be prepared when the code bits (maximum 16 bits) required for normalization are read from the buffer register 11j3, so that ultra-high speed / constant speed decoding can be performed. Vessel can be realized.

Embodiment 6 FIG. Next, FIG. 12 shows a block configuration of a decoding device according to another embodiment of the present invention. The difference from the embodiment of FIG. 7 is that the order / predicted value memory 2 has a two-port configuration, and that the reference symbol pattern 102 and the same signal 109 for updating are monitored instead of the detector 7, If the reference symbol patterns 102 match (except A in FIG. 16) when the update signal 108 is generated,
Two-port control unit 1 for canceling an access that matches a symbol pattern for updating among accesses corresponding to reference symbol patterns 102 accessed in parallel
Fourth, an access prohibition circuit 15 is added.

FIG. 13 shows an example of the decoding operation in this embodiment. Here, the arithmetic decoder shown in FIG. 8 was used. The same processing as described above can be performed by a two-port memory having an access time of 100 nsec.

In the above-described embodiment, the LPS and the MPS calculation method for arithmetic coding is a single method irrespective of the effective area width, but as described in JP-A-3-247123, the LPS and MPS
MPS and LP when the magnitude relation of the effective range of
The method of reversing the assignment of S, or the method of LPS when the width of the MPS region is less than 1/2, as in JP-A-2-202267.
A similar effect can be obtained by a method of distributing a part of the region to the MPS. The same applies to a method in which the MPS region is positioned at a higher position on the number line.

[0074]

As described above, according to the present invention, when arithmetic coding or decoding of an information source symbol, LPS
Alternatively , encoding is performed by shifting the new effective area width and area boundary value according to the MPS by a predetermined number of bits.
Or an encoding device that can greatly improve the decoding speed or
A decoding device can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an arithmetic encoder of an encoding apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a code register in the embodiment of FIG. 1;

FIG. 3 is a timing chart showing an operation example according to the embodiment.

FIG. 4 is a block diagram of a code register of an arithmetic encoder of an encoding apparatus according to another embodiment of the present invention.

FIG. 5 is a block diagram of an encoding apparatus showing another embodiment of the present invention.

FIG. 6 is a timing chart showing an operation example according to the embodiment of FIG. 5;

FIG. 7 is a block diagram of a decoding apparatus showing another embodiment of the present invention.

FIG. 8 is a block diagram showing the internal configuration of the arithmetic decoder in the embodiment of FIG. 7;

9 is a block diagram showing an internal configuration of a code register of the arithmetic decoder shown in FIG. 8;

FIG. 10 is a timing chart showing an operation example according to the embodiment of FIG. 7;

FIG. 11 is a block diagram of a code register of an arithmetic decoder showing another embodiment of the present invention.

FIG. 12 is a block diagram of an arithmetic decoder showing another embodiment of the present invention.

FIG. 13 is a timing chart showing an operation example according to the embodiment of FIG. 12;

FIG. 14 is a block diagram of a conventional encoding device.

FIG. 15 is a block diagram showing an internal configuration of an arithmetic encoder in the encoding device of FIG. 14;

FIG. 16 is a diagram illustrating positions of reference symbols used for encoding.

FIG. 17 is a diagram showing contents of an order / predicted value table.

FIG. 18 is a diagram showing contents of an area width table.

19 is a timing chart showing an operation example in the encoding device of FIG.

[Explanation of symbols]

 2 order / predicted value memory 5 arithmetic encoder 6 order / predicted value control circuit 7 detector 8 order / predicted value register 11 arithmetic decoder 13 selector 5a first register 5b first arithmetic unit 5d second register 5e Second calculation means 5c First selection means 5j Second selection means 5h Bit position detection means 5i First barrel shifter 5k Second barrel shifter 5f Code generation means 5f11 FIFO 11a First register 11b First calculation means 11f Second register 11g Second operation means 11c First selection means 11h Second selection means 11d Bit position detection means 11e First barrel shifter 11i Second barrel shifter 11j Code reading means 11j4 FIFO

Continuation of the front page (56) References JP-A-56-79333 (JP, A) JP-A-60-196014 (JP, A) JP-A-62-43222 (JP, A) JP-A-1-286526 (JP) JP-A-3-247123 (JP, A) JP-A-5-64007 (JP, A) JP-A-5-298063 (JP, A) JP-A-2-305225 (JP, A) 5-67978 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 7/40

Claims (6)

(57) [Claims] 1. An encoding apparatus for estimating a symbol appearance probability from an output symbol sequence of an information source, performing effective area division on the number line, and arithmetically encoding the symbol sequence, comprising: A first register for storing an effective area width of the first area, first calculating means for calculating an area width of a symbol (dominant symbol: MPS) which is assumed to have a high frequency of occurrence, and a boundary value of the effective area on a number line A second register for storing a boundary value between a region corresponding to a symbol whose occurrence frequency is assumed to be low (recessive symbol: LPS) and a region of MPS; First selecting means for selecting a new effective area width depending on whether the symbol is LPS, second selecting means for selecting a boundary value of a new effective area depending on whether the generated symbol is MPS or LPS, Bit position detecting means for detecting the position of the most significant "1" or "0" in response to the new effective area width from the selecting means, and from the first selecting means in response to the output from the bit position detecting means. shifting a first sheet cover to be output to the first register by shifting a new effective region width, the boundary value of a new effective region from the second selecting means in accordance with the output from the bit position detection means further comprising a second sheet lid outputs an overflow data, the code generating means for generating a code output by receiving overflowed data output from the second sheet cover and outputs in the second register An encoding device characterized by the above-mentioned. 2. The encoding apparatus according to claim 1, wherein said code generation means includes a FIFO memory. 3. A decoding method for estimating the symbol appearance probability from an output symbol sequence of an information source, dividing an effective area on a number line, and decoding a code bit sequence obtained by arithmetically encoding the symbol sequence. A first register for storing an effective area width on a number line; first calculating means for calculating an area width of a symbol (dominant symbol: MPS) which is assumed to have a high frequency of occurrence; A second register for storing a boundary value of an effective area of the symbol, and a boundary value between an area of a symbol (recessive symbol: LPS), which is assumed to have a low frequency of occurrence from the output of the second register, and an MPS area. A second calculating means for determining whether the symbol is MPS or LPS, a first selecting means for selecting a new effective area width depending on whether the symbol is MPS or LPS, A second selecting means for selecting a new effective area boundary value depending on whether it is MPS or LPS, and receiving the new effective area width from the first selecting means, and determining the position of the highest "1" or "0" A bit position detecting means for detecting, a code reading means for inputting a code data sequence and outputting a code data sequence of a required number of bits according to an output from the bit position detecting means, and an output from the bit position detecting means. depending first and first sheet lid order to shift the new effective area width from the selection means to the first register, the new from the second selecting means in accordance with the output from the bit position detecting means such boundary value of the effective region and to shift the output from the code reading means second output to the second register
Decoding apparatus characterized by comprising a sheet cover. 4. The decoding device according to claim 3, wherein said code reading means comprises a FIFO memory. 5. An encoding apparatus for predicting an encoding target symbol from a state of a plurality of reference symbols at a predetermined position of an output symbol sequence of an information source and encoding a prediction error signal, comprising: The read / write simultaneous operation that stores the predicted value of the above-mentioned encoding target symbol in each state and the order that is the identifier of the group classified by the prediction coincidence rate is possible .
And memory, and the order and prediction value control circuit for rewriting the predicted value and degree of the reference symbol state in accordance with coded symbols examines whether they match the prediction result, read from the memory An order / predicted value register for storing the predicted value and the order of the encoding target symbol or the predicted value and the order after the rewriting process for the immediately preceding encoding target symbol, and the reference symbol state and the immediately preceding A detector for detecting whether or not the reference symbol state for the symbol matches; and an arithmetic encoder for encoding a prediction error signal based on the predicted value / order output from the order / predicted value register. If the prediction value or order for the previous symbol is updated, the rewriting process of the prediction value / order for the previous symbol and the encoding target The prediction value and the order of the symbol are read in parallel, and the reference symbol state for the encoding target symbol and the reference symbol state for the immediately preceding encoding target symbol are one as the prediction value and the order used for encoding. We by whether rewriting the predicted value and degree of post-treatment, or the encoding apparatus characterized by selectively using degree and predicted value stored in the memory. 6. A decoding target symbol is predicted from states of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source, and a code bit sequence obtained by encoding the prediction error signal is decoded. The decoding device stores a predicted value of a decoding target symbol and an order which is an identifier of a group classified based on a prediction coincidence rate from a state of a reference symbol, and corresponds to a plurality of symbols that may be decoded. and memory that can be read write simultaneously to multiple outputs order and predicted value as a set, the decoded symbol is examined whether or not the match predicted prediction value and the order of the reference symbol state according to the result and degree and predicted value controller for rewriting, by the reproduction signal values of decoded symbols preceding a plurality of sets of prediction values output from the main <br/> memory One of the fine the next number
A set of predicted values and the selector for selecting and outputting the order, the prediction value and the order of the memory, or a register for storing the predicted value and the order of the updated for the immediate decoded symbols, for decoded symbol A detector for detecting whether the reference symbol state matches the reference symbol state for the immediately preceding symbol; and an arithmetic decoder for decoding a code bit sequence based on the selected predicted value / order. If there is an update of the predicted value or order for the immediately preceding symbol, the process of rewriting the predicted value or order for the immediately preceding symbol and the process of reading the predicted value or order for the symbol to be decoded are performed in parallel, and decoding is performed. The reference symbol state for the decoding target symbol and the reference symbol state for the immediately preceding symbol as the prediction value and order used for There by whether they match, the predicted value and degree after rewriting the decoded symbol of the immediately preceding or,
Decoding apparatus characterized by selectively using prediction values and orders stored in the memory.