JP2001230935A - Method and device for arithmetic encoding/decoding - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate the decoding speed of an encoded multilevel image using hardware having simple configuration. SOLUTION: For the arithmetic encoding/decoding method for arithmetically encoding/decoding multilevel image information composed of plural bit planes while referring to context information, the encoding/decoding order is determined, so that the context information corresponding to an encoding/decoding object pixel can be determined while preceding for at least two cycles of the encoding/decoding object pixel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an arithmetic code (Arithme
The present invention relates to an arithmetic coding method for coding image data using a tic code, and an arithmetic decoding device for decoding image data coded by the method, and particularly to an arithmetic coding method and arithmetic decoding for a multi-valued image. Related to the device.

[0002]

2. Description of the Related Art Arithmetic codes are represented by a corresponding section (binary decimal [0.0... 0, 0.1...) On a numerical line of [0, 1).
1]) is divided into unequal lengths in accordance with the occurrence probabilities of the respective symbols, the symbol sequence to be encoded is allocated to the corresponding subsections, and the section obtained by recursively repeating the division is The coordinates of the included points are represented as binary decimal numbers that can be distinguished from at least other sections, and are directly used as codes.

[0003] As a typical arithmetic code method, I
TU organization JBIG (Joint Bi-1ev)
el Image Experts Group), JBIG (QM-coder) method, IBM
There is Q-coder etc. proposed by the company.

[0004] Since the terms used in each method are different, the terms used in the JBIG method, which is a standard method, are used here, but the present invention is not limited to the arithmetic code of the JBIG method.

[0005] In arithmetic coding, multiplication processing is required in principle in the arithmetic operation unit. However, when the multiplication processing is performed, the hardware scale of the arithmetic operation unit becomes large or the processing time required for the multiplication processing becomes long. Therefore, a simplified method in which the arithmetic operation is replaced with an addition / subtraction operation has become mainstream.

In the arithmetic operation unit, there are an A register for holding an area width (orgent) corresponding to a coded symbol sequence, and a code register (C register) for holding a value from which a code is generated. , The loss probability of the symbol to be coded with respect to the coded prediction value is input as a probability estimation value LSZ, and based on information indicating whether the symbol matches the prediction value or not, the probability estimation value LSZ and the two registers An arithmetic operation (addition / subtraction) is performed from the value to update the values of the two registers.

[0007] The probability estimation value LSZ is obtained by converting the peripheral symbol information of the symbol to be encoded from an index (state) value possessed for each digitized context using a predetermined correspondence table. By updating the state value possessed for each context based on a predetermined condition, it is possible to learn a pattern unique to the coded symbol sequence,
Encoding efficiency can be increased.

In the JBIG method, the value of the A register is set to 10
If the value of the A register is less than 8000H as a result of the arithmetic operation (encoding or decoding), the normalization process is called and the value of the A register is 8000H.
Until the above, the left shift is performed, and at that time, the state value of the current context is updated.

When the value of the A register is shifted to the left,
At the same time, the value of the C register is also shifted left. At this time,
Data shifted out from the uppermost position of the C register becomes encoded data.

If the value of the symbol to be encoded is binary pixel data having a value of only 0 or 1, the configuration of the encoding block for performing the arithmetic encoding process is as shown in FIG.

<Encoding block> In FIG.
Is a terminal for inputting binary data PIX of the pixel to be encoded,
Reference numeral 102 denotes a binary data PIX signal; 103, context information including peripheral pixel data of an encoding target pixel;
Is the predicted value and index (state) for each context information
A predicted state memory that holds a value, 106 is a predicted value output from the predicted state memory 105, 107 is a state value output from the predicted state memory 105, and 109 is a conversion of the output state value 107 into a probability estimation value LSZ. Probability estimator, 1
11 is a probability estimation value LS output from the probability estimation unit 109
Z and 113 are exclusive NOR gates, 114 is a signal representing the match / mismatch between the binary data PIX and the predicted value 106, 115 is an arithmetic coding operation unit, and 117 is a code output from the arithmetic coding operation unit 115. Coded data (code data) 118, a signal for requesting an update of the predicted state memory 105, 119 a predicted state update unit for obtaining an updated predicted value and a state value from the current predicted value 106 and the state value 107, 120 is output from the prediction state update unit 119;
Updated predicted value / state value signal and predicted state memory 10
5 is a control signal for writing the signal.

Next, the operation of the arithmetic coding processing block shown in FIG. 1 will be described.

The binary data PIX of the pixel to be encoded is inputted from a terminal 101 and inputted to an exclusive NOR gate 113. On the other hand, the peripheral pixel data CXi (i = 1, 2,..., N) of the encoding target pixel 103 which is the context information
Is given to the prediction state memory 105.

The prediction state memory 105 uses the context information 103 consisting of peripheral pixel data as an address and a prediction value 106 for an encoding target pixel and an index (state).
The value 107 is output. Note that this state value 107 is determined based on the contents learned by encoding processing up to that time. The predicted value 106 is a binary value of 0 or 1, and the exclusive NOR
Input to the gate 113.

On the other hand, the state value 107 is sent to a probability estimating unit 109, where it is converted into a probability estimated value 111. The probability estimation value 111 represents the probability that the binary data PIX does not match the prediction value 106. Probability estimate 11 from state value 107
Conversion to 1 is performed using a ROM table or a decoder. The state value 107 is the predicted state update unit 1
19 is also input.

The exclusive NOR gate 113 checks the match / mismatch relationship between the binary data PIX and the predicted value 106, and sends 1 to the arithmetic coding operation unit 115 if they match and 0 if they do not match. .

The arithmetic coding operation unit 115 performs an arithmetic operation for an encoding process to be described later based on the coincidence / mismatch information 114 and the probability estimation value 111 input from the probability estimation unit 109. The data 117 is output.

When the above-described normalization processing is performed in the course of the arithmetic operation in arithmetic coding operation section 115, signal 118 is output.
Is output, and an update request is sent to the predicted state update unit 119.

The predicted state updating unit 119 obtains an updated state value and predicted value from the input state value 107, predicted value 106, and match / mismatch information 114, and sends updated data to the predicted state memory 105. The predicted state memory 105 that has received the update data updates the held content based on the update request. In order to obtain the updated state value from the input state value 106 in the predicted state updating unit 119, a ROM table, a decoder, or the like is used.

Next, FIG. 2 shows an example of the configuration of the arithmetic coding operation unit 115, and its operation will be described.

Referring to FIG. 1, reference numeral 201 denotes an A register for holding an area width (an agent); 203, a code register (C register) for holding a value from which a code is generated; A subtracter 207 for subtracting the probability estimation value 111;
Adder for adding the output of the subtractor 205 to the output value of
9 is a selector for selecting data to be input to the A register 201, 211 is a selector for selecting data to be input to the C register, 213 is a shift register for capturing code information shifted out from the C register, 215 is an output register, and 217 is an output register. A counter for counting the number of bits fetched into the shift register 213, a terminal 218 for inputting a shift clock, a mask circuit 219, a shift clock masked by the mask circuit 219, a shift clock 22
1 indicates that the output value of the A register 201 is 8000H (16
Hex) or more.

In the state after the initialization, the value of the A register 201 is 10000H, the value of the C register 203 is 0H, and the value of the counter 217 is 0.

A predetermined arithmetic operation is performed based on the input match / mismatch information 114 and the estimated probability value 111, thereby updating the values of the A register 201 and the C register 203 every time one pixel is encoded. And the A register 20
The data that is shifted out from the upper part of the C register 203 in the normalization process of 1 and output in N bits is the encoded data 117.

First, the input probability estimation value 111 is input to the subtractor 205 and the selector 209.

The subtractor 205 subtracts the probability estimation value 111 from the output value of the A register 201, and sends the result to the selector 209 and the adder 207.

The selector 209 is also provided with an estimated probability value 111. When the match / mismatch information 114 is 1, the subtraction result is selected, and when the match / mismatch information 114 is 0, the estimated probability value 111 is selected and output.

The adder 207 adds the subtraction result sent from the subtractor 205 to the output value of the C register 203, and sends the addition result to the selector 211. Selector 211
, The output value of the C register 203 is directly given. When the match / mismatch information 114 is 1, the output value of the C register 203 is selected, and when the match / mismatch information 114 is 0, the addition result is selected and output.

The outputs of the selectors 209 and 211 are taken into the A register 201 and the C register 203 in the next cycle, respectively.

If the value of the A register 201 is less than 8000H, the detector 221 detects it and performs a normalization process before performing the next arithmetic operation. In contrast, the A register 20
When the value of 1 is 8000H or more, the following arithmetic operation is performed.

One way of realizing the normalization processing is to use a register having a shift function for each of the A register 201 and the C register 203, apply a shift clock 220 to the register, and set the value of the A register 201 to 8000H. Until the A register and the C register are shifted to the left.

The shift clock 220 is supplied to the detector 22
The shift clock input from the terminal 218 is masked by the mask circuit 219 on the basis of the output of 1 to obtain the shift clock.

While the value of the A register 201 is less than 8000H, the input shift clock passes through the mask circuit 219 and is sent to the A register 201, the C register 203, the shift register 213, and the counter 217. Each time the shift clock is input, the A register 201, the C register 203, and the shift register 213 shift one bit to the left, and the counter 217 counts up by one.

The data input to the shift register 213 is the most significant bit of the C register 203. Therefore, each time the shift clock 220 is sent to each block, the upper bit data of the C register 203 is transferred to the shift register 21.
It will move to 3.

The number of bits transferred to the shift register 213 is counted by the counter 217 which counts up by the shift clock 220. When the count value reaches a predetermined value, the counter 217 sends the output register 215 to the output register 215. A data capture pulse 222 is sent.

The output register 215 collectively receives data of a predetermined number of bits sent from the shift register 213 at the timing when the pulse 222 is input, and holds the data until the next data input pulse 222 is input. .

The value of the A register 201 is 8000H
When the detector 221 detects that the difference is less than the predetermined value, a signal 118 requesting an update is output to the prediction state update unit 119 by a circuit (not shown).

The binary data PIX input to the terminal 101 is encoded by the arithmetic operation and the normalizing process as described above, and the encoded data
15 is output in predetermined bit units.

<Decoding Block> Next, the configuration of a decoding block corresponding to the coding block shown in FIG. 1 is shown in FIG. 3 and its operation will be described.

There are two major differences between the decoded block shown in FIG. 3 and the encoded block shown in FIG.

(1) An arithmetic decoding operation unit 301 is used in place of the arithmetic coding operation unit 115. (2) The coded data 306 is input, and the value of the pixel data of interest is obtained.
Since the other configurations are basically the same, the differences will be briefly described.

First, the operation of the arithmetic decoding unit 301 will be described. FIG. 4 shows the configuration of the arithmetic decoding operation unit 301.

In the figure, a subtractor 401 corresponds to an adder 207 in the arithmetic coding operation unit 115 of FIG. 2, an input buffer register 403 corresponds to an output register 215 of FIG. 2, and a shift register 405 corresponds to a shift register 213. It has been replaced.

The input probability estimation value 111 is subtracted from the subtractor 2
05 and the selector 209. The subtractor 205 subtracts the input probability estimation value 111 from the output value of the A register 201, and sends the subtraction result to the selector 209 and the subtractor 401.

In the arithmetic coding operation unit 115 shown in FIG. 1, the selector 209 operates based on the match / mismatch information 114. In the arithmetic decoding operation unit 301, the subtractor 401
Selector 209 depending on whether the result of the subtraction is positive or negative.
Is determined.

The subtractor 401 subtracts the output value of the subtractor 205 from the output value of the C register 203, sends the subtraction result to the selector 211, and outputs a signal 302 indicating whether the subtraction result is positive or negative. The signal 302 has a value of 0 when the subtraction result is positive and 1 when the subtraction result is negative.

Using the signal 302 as a control signal, the selector 209 selects the estimated probability value 111 when the subtraction result is positive, and selects and outputs the output of the subtractor 205 when the subtraction result is negative.

The selector 211 is also controlled by the same signal 302 as the selector 209. The selector 211 receives the output of the subtractor 401, that is, the subtraction result, and the output value of the C register 203. When the subtraction result is positive, the output of the subtractor 401 is selected, and when the subtraction result is negative, the output of the C register 203 is selected and output.

The outputs of the selectors 209 and 211 output the A register 201 and the C register 20 in the next cycle, respectively.
3 and performs a normalization process in the same manner as the arithmetic coding operation unit 115.

The arithmetic coding operation unit 115 outputs the encoded data 117 at the time of the normalization processing, but the arithmetic decoding operation unit 301 outputs the encoded data 30 by the normalization processing.
Take in 6.

The encoded data 306 is output from the arithmetic encoding unit 115 in FIG. 1 and is temporarily stored in a storage unit (not shown). Then, the data is read out at an appropriate timing and supplied to the arithmetic decoding operation unit 301 in the decoding block. Alternatively, the encoded data is directly transferred to a remote place, and the original 2
It is restored to value image data. The restored binary image data is sent to an image display device such as a monitor or a printer, and is converted into a visible image.

The encoded data 306 given to the arithmetic decoding operation unit 301 is taken into the shift register 405 via the input buffer register 403, and the most significant bit of the shift register 405 is changed to the C register 203 by normalization processing. Is shifted into the least significant bit of The control method of the normalization process is the same as that of the arithmetic coding operation unit 115, and thus the description thereof is omitted. At the timing when the normalization process is performed, a signal 315 requesting an update to the prediction state update unit 119 is output by a circuit (not shown).

By the arithmetic processing of the arithmetic decoding operation unit 301 described above, information indicating whether or not the pixel value of interest during decoding matches the predicted value (match / mismatch) is obtained as a signal 302, and the arithmetic decoding operation is performed. The output from the unit 301 is used in the decoding block of FIG. The signal 302 has a value of 1 when the pixel value of interest during decoding matches the predicted value, and has a value of 0 when not matching.

In the decoding block, similarly to the coding block, the prediction state memory 105 outputs the prediction value 106 for the pixel of interest being decoded, using the context information of the peripheral pixel data as an address.

The predicted value 106 is calculated by the arithmetic decoding
The exclusive NOR gate 305 performs a logical operation on the match / mismatch signal 302 output from 1. The result of this logical operation is the value of the decoded pixel of interest, and the decoded pixel value is obtained as signal 304.

The operation of the other blocks is the same as that of the coding block shown in FIG.

Next, Japanese Patent Application Laid-Open No.
FIG. 5 shows the configuration of an arithmetic decoding block having means for obtaining an updated probability estimate from a probability estimate described in -103257. In FIG. 5, reference numeral 501 denotes a predicted probability update unit that obtains the next (updated) probability estimate from the current probability estimate, and 503 denotes a probability estimated value memory that stores the predicted value and the probability estimated value. The elements have the same function as the elements with the same numbers in FIG.

When comparing the block diagram of FIG. 5 with the block diagram of FIG. 3, the probability estimation value memory 503 and the arithmetic decoding operation unit 301
It can be seen that there is no probability estimating unit 109 between the two.

Since the input / output signals of the arithmetic decoding operation unit 301 are exactly the same as those in the configuration shown in FIG. 3, the effect of eliminating the probability estimating unit 109 is affected by the prediction state memory 105 and the prediction state memory 105 which are the other components. Appears in the state update unit 119.

The probability estimation value 111 required for the arithmetic decoding operation unit 301 is stored in a newly provided prediction probability estimation value memory 503.
Read from Therefore, the probability estimation unit 109 becomes unnecessary.

To store the probability estimation value in the probability estimation value memory 503, the probability estimation value corresponding to the initial state value is written into the probability estimation value memory 503 at initialization, and the updated probability estimation value is updated at the time of updating the memory. Write the value.

The updated probability estimate is calculated by the prediction probability update unit 5
Determine with 01. The prediction probability update unit 501 is used instead of the prediction state update unit 119, and inputs a current probability estimated value, predicted value, and the like, and obtains an updated probability estimated value and predicted value. The conversion from the current probability estimation value to the updated probability estimation value is performed using a ROM table or a decoder.

Therefore, in the decoded block having the above configuration, the state value 107 does not physically exist. However, since the conversion table from the current probability estimation value to the updated probability estimation value (necessary for creating a ROM table or a decoder) is created by replacing the transition of the state value with the transition of the probability estimation value, It will be included in the table.

The number of the state value has uniqueness. That is, different state values are always assigned to different states. However, the probability estimates are not unique. That is, it is possible in principle to assign the same probability estimate to different states. But JB
Since different probability estimates are assigned to different states in the IG method, it can be said that the probability estimates have uniqueness only in the JBIG method.

If there is uniqueness in the probability estimation value, there is no problem in the processing performed by the prediction probability updating unit 501, but if there is no uniqueness, a problem occurs. That is, there is a problem that there are many types of update probability estimates for the input probability estimates. To avoid this, an identification signal is needed to distinguish between the same probability estimates. If 2n pieces have the same probability estimation value, an n-bit identification signal is required for identification. This identification signal is sent to the prediction probability update unit 5
01, which is input to a ROM table, a decoder, or the like, and specifies one of many types of update probability estimation values. Further, when the update probability estimation value on the output side is not unique, an n-bit signal for identifying the probability estimation value is required, and the identification signal is also stored in the probability estimation value memory 503.

An encoding / coding system having the configuration shown in FIGS.
The main processing required to encode / decode one pixel in the decoding block includes the following four steps.

(1) The predicted value and the state value are read from the memory. (2) Convert state values to probability estimates. (3) Perform arithmetic coding / decoding operation using the estimated probability value. (4) Update the predicted value and the state value and write them to the memory (necessary only during normalization processing). The update processing of the predicted value and the state value in the above (4)
Since the arithmetic coding operation in (3) can be performed in parallel, the processing performed in (4) in terms of timing is only the write processing to the memory.

On the other hand, the decoding block having the configuration shown in FIG. 5 has the following three steps.

(1) The predicted value and the estimated probability value are read from the memory. (2) Perform an arithmetic decoding operation using the probability estimation value. (3) Update the predicted value and the estimated probability value and write them to the memory (necessary only during normalization processing). Therefore, as compared with the configuration shown in FIGS. 1 and 3, encoding can be performed faster by a time corresponding to a process of converting a state value into a probability estimation value.

The present inventor further disclosed in Japanese Unexamined Patent Publication No.
3257 also proposes an arithmetic decoding block having a configuration as shown in FIG.

In general, pixels immediately above and to the left of the pixel having a strong correlation with the pixel of interest are used as context information from which a prediction value is obtained. Therefore, when decoding processing is performed in a raster scanning order, simple sequential processing cannot be used. If the decoding of the pixel of interest is not completed, a prediction value or the like necessary for decoding the pixel on the right side cannot be read.

Therefore, the memory storing the predicted values and the like is divided into a plurality of memory groups, and a plurality of predicted values and the like are read from the memory groups in parallel. The plurality of predicted values correspond to the case where the pixel value of interest during the decoding process is 0 and 1, and when the pixel value of interest is determined, one predicted value is selected from the plurality of predicted values. That is.

FIG. 6 shows an arithmetic decoding block having the above memory configuration and storing the probability estimation value in the memory.

In the figure, reference numeral 601 denotes a first probability estimated value memory, 602 denotes a second probability estimated value memory, and 603 selects one of two sets of predicted values / probability estimated values read from the above two memories. A selector 605 is a selector 603
Selector 607 selects a D-type flip-flop (DF / F) that latches the output of the selector 605;
10 is context information, 609 is context information 6
10 is a delay circuit that delays one cycle. The other components are the same as those indicated by the same reference numerals in the decoding block shown in FIG.

In the configuration of FIG. 6, since the predicted value and the estimated probability value are read from the memory in advance, the context information for reading the memory and the context information for writing the memory used when updating the memory are shifted by one cycle. Signal. Therefore, a two-port memory that can simultaneously input two pieces of context information (address) is used.

The signal 610 is other context information except for the pixel value of interest during the decoding process, and has less 1-bit information than the context information 103 that has been output so far. The context information 610 includes the first and second probability estimation value memories 6 as address signals for memory reading.
01,602. On the other hand, context information 6
10 is delayed by one cycle in a delay circuit 609, and supplied to the first and second probability estimation value memories 601 and 602 as an address signal for writing into the memory.

The first probability estimation value memory 601 stores the prediction value and the probability estimation value corresponding to the pixel value of interest during the decoding process being 0, and the second probability estimation value memory 603.
Stores a predicted value and a probability estimated value corresponding to a pixel value of interest during decoding processing of 1. That is, all information stored in the two memories 601 and 602 is the same as the information stored in the probability estimation value memory 503 shown in FIG.

The first and second probability estimation value memories 601,
From 602, the prediction value and the probability estimation value are read in parallel using the context information 610 as an address.

The decoding process (arithmetic decoding operation) for the pixel of interest is performed in parallel with the reading from the memory, and the decoded pixel value is determined when the memory read data is determined.
Based on the decoded pixel value, the selector 603 selects one of the two memory outputs.

The output of the selector 603 is basically the same as the content read from the probability estimation value memory 503 in FIG. 5, but the next probability estimation value is read before the update data is written. It may not be reflected in the output of the selector 603.

This is the case where all the context information from which the predicted value / probability estimation value is read and selected and all the context information used at the time of updating the memory completely match. This translates into the following conditions: (read address = write address), (decoded pixel value in current cycle = decoded pixel value one cycle before), and (when memory is updated).

When a detector (not shown) detects that the above condition is satisfied, the selector 605 switches the memory output to updated data. The output of the selector 605 is
Latched by the DF / F 607, the arithmetic decoding operation unit 30
1 to perform an arithmetic operation to decode the next pixel.

While the arithmetic operation is being performed, the context information 610, which does not include the pixel value being decoded, is one bit less.
, A new probability estimation value is read from the two probability estimation value memories 601 and 602.

In the above configuration, as described above, the arithmetic operation for decoding and the reading from the probability estimation value memories 601 and 602 can be performed in parallel, so that a higher-speed decoding process can be performed.

In the above, an example of encoding and decoding binary image data has been described. Next, a case of encoding and decoding a multi-valued image composed of a plurality of bit planes in pixel order will be described. I do. The pixel order is different from the plane order. For example, in a 2-bit plane, as shown in FIG. 7A,..., {I−1} [2], {i−1}
[1], {i} [2], {i} [1], {i + 1}
[2], {i + 1} [1], {i + 2} [2], ...
(｛｝ [1] indicates an upper bit plane,｝｝ [2] indicates a lower bit plane), and lower bits and upper bits are alternately encoded, and pixels are sequentially encoded.

The problem at this time is what to refer to the context information in each plane. When encoding each plane independently, it is sufficient to refer only to the upper bit plane when encoding the upper bits and to refer only to the lower bit plane when encoding the lower bits.

However, if it is desired to refer to the upper bits when encoding the lower bits, and also to refer to the upper bits of the same pixel, the upper bits must be encoded before the lower bits. On the other hand, the encoding order is changed as shown in FIG.
As shown in (b),..., {I-1} [1], {i
-1} [2], {i} [1], {i} [2], {i +
1 {[1], {i + 1} [2], {i + 2} [1],.
・ It can be changed as follows. By changing the encoding order, decoding becomes possible.

[0087]

When arithmetic decoding is to be performed on a plurality of bit planes of a multi-valued image using the above-described decoding block according to the conventional example, when decoding a certain bit of interest, the decoding process is required. In the worst case, all context information is determined after decoding the immediately preceding bit. Therefore, since the learning memory cannot be read out without decoding the immediately preceding bit, when performing the decoding processing by hardware, it has been a great hindrance to increase the decoding operation speed.

The present invention has been made in view of the above problems, and has as its object to increase the decoding speed of an encoded multi-valued image with hardware having a simple configuration.

[0089]

In order to achieve the above object, the arithmetic coding / decoding of the present invention for arithmetically coding / decoding multi-valued image information composed of a plurality of bit planes with reference to context information. The method wherein the context information for the pixel to be encoded / decoded is determined at least two cycles ahead of the pixel to be encoded / decoded,
The encoding / decoding order was determined.

Preferably, the encoding / decoding order is:
If the number of bit planes is m, the pixel number is represented by {} and the bit plane is represented by [].
Next to {i} [j], if j ≠ m, then {i-1} [j +
1] and j = m, {i + 1} [1].

According to a preferred embodiment, if the number of pixels to be encoded / decoded is n, {i−1} ≦ 0 and {i +
When 1｝> n, a predetermined value is encoded / decoded.

According to another preferred embodiment, when the number of pixels to be encoded / decoded is n, {i-1} ≦ 0
And {i + 1}> n, the encoding / decoding is skipped.

In order to achieve the above object, the arithmetic coding device of the present invention performs arithmetic coding by the above-mentioned arithmetic coding method. Further, the arithmetic decoding device of the present invention performs arithmetic decoding by the above-described arithmetic decoding method.

Further, in order to achieve the above object, an arithmetic decoding apparatus according to the present invention for arithmetically decoding encoded multi-valued image information comprising a plurality of bit planes with reference to context information, comprises: Decoding is performed in an order in which the context information for the pixel is determined at least two cycles before the processing timing of the decoding target pixel.

According to a preferred embodiment, a probability estimation value memory provided for each bit plane for holding the prediction value and the probability estimation value, and the prediction value and the probability estimation value are stored based on the determined context information. A prediction estimation updating unit that updates the prediction value and the probability estimation value from the probability estimation value memory using the determined context information as an address.

According to another preferred embodiment, a prediction state memory provided for each bit plane, which holds a prediction value and a state value, and a prediction value and a state value based on the determined context information. And a predicted value and a state value are read from the predicted state memory using the determined context information as an address.

Preferably, the decoding order is such that, when the number of bit planes is m, if the pixel number is represented by {} and the bit plane is represented by [], the following of {i} [j] is as follows: When j ≠ m, {i−1} [j + 1], and when j = m, {i + 1} [1].

According to a preferred embodiment, when the number of pixels to be decoded is n, {i−1} ≦ 0 and {i +
When 1｝> n, a predetermined value is encoded / decoded.

According to another preferred embodiment, when the number of pixels to be decoded is n, {i-1} ≦ 0 and {i
If +1｝> n, the decoding is skipped.

[0100]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

As described above, since the terms used differ depending on the type of arithmetic coding method, the terms used in the JBIG method, which is the standard method, are also used in the embodiment of the present invention. Is not limited to the arithmetic code of the JBIG method.

[First Embodiment] In the first embodiment, an arithmetic coding method for a multi-valued image in which one pixel is composed of 2 bits and an arithmetic decoding device corresponding to the arithmetic coding method will be described.

FIG. 8 is a diagram showing the order of encoding / decoding in the first embodiment. Arithmetic encoding / decoding is performed in the order indicated by the arrows in FIG. That is,
・, {I} [1], {i−1} [2], {i + 1}
[1], {i} [2], {i + 2} [1], {i + 1}
Encoding / decoding is performed in the order of [2], {i + 3} [1],. Here, ｛｝ [1] represents an upper bit plane, and ｛｝ [2] represents a lower bit plane.

The most significant bit of the first pixel, that is, {1}
After [1], {-1} [2] is encoded / decoded, which corresponds to the lower bits of non-existent pixels. When the number of pixels is n, the next lower bit of the second to last pixel, that is, {n-1} [2] is {n + 1}.
[1] is encoded / decoded, and this is also a nonexistent pixel. Although these bits do not need to be coded originally, for example, 0 may be coded as dummy bits, and at the time of decoding, the decoded dummy bits may be discarded to obtain the original image. According to this method, there is an advantage that the apparatus configuration can be simplified since an exceptional operation does not need to be performed at the leading end and the trailing end of the image.

When encoding the upper bit plane, only the upper bits encoded before that are referred to. That is, the context information when encoding the upper bit plane is configured using only the upper bits encoded earlier.

When the lower bit plane is encoded, the lower bits encoded before that and the upper bits encoded before the lower bits are referred to. Specifically, when encoding is performed in the above order, the lower bits that can be referenced when encoding {i} [2] are {i−1} [2], and the upper bits are the lower bits to be referenced. The upper bits encoded before encoding i−1} [2], that is, the upper bits before {i} [1]. Actually ｛i
-1} [2] A part of lower bits before [2] and {i} [1]
And reference.

Conventionally, the necessary context information was determined in the previous cycle of decoding the bit information to be decoded. However, in the first embodiment, the necessary context information is determined in the second previous cycle. The information is confirmed. Since the decoding order is exactly the same as the encoding order, as shown in FIG. 8,..., {I} [1], {i−1} [2], and {i +
1｝ [1], ｛i｝ [2], ｛i + 2｝ [1], ｛i +
The decoding process is performed in the order of 1 {2}, {i + 3} [1],.

First, a case where the encoded data of the upper bit plane is decoded according to the above decoding order will be described. Since the decoding of the upper bits refers only to the upper bits encoded before, the context information necessary to decode {i + 1} [1] is {i} [1] and the upper bits before that. Bit information. In this case, ｛i +
The decoding of {i} [1], which is the last information necessary for decoding 1 {[1], ends two cycles before the timing of processing {i + 1} i}. ing.

Next, consider the case of decoding the encoded data of the lower bit plane. Decoding of upper bits {i} [1] referred to when encoding {i} [2] is performed by:
It ends three cycles before {i} [2]. The decoding of the reference bits on the lower bit plane has been completed two cycles before. Therefore, in the decoding order shown in FIG. 8, it is understood that the context information necessary for the decoding process of the bit of interest is determined two cycles before in any plane.

In the method of generating a context using the reference bit information as described above and decoding the encoded data by hardware, the timing of signal processing is very important. In this case, the timing at which the context information is determined is particularly important. The configuration of a decoding block that can be decoded in the above decoding order will be described with reference to FIG.

In the figure, reference numeral 801 denotes context information for decoding the upper bit plane; 803, a DF / F for latching the context information 801;
Is context information when decoding the lower bit plane, and 807 is D- which latches context information 805.
F / F 809 is a probability estimation value memory used when decoding the upper bit plane, 811 is a probability estimation value memory used when decoding the lower bit plane, and 813 is one of the outputs of the two probability estimation value memories. The selector to be selected, 815 is a selector for selecting one of the output of the selector 813 and the updated probability estimation value, and 817 is the selector 81
DF / F latching the probability estimation value output from 5, 8
Reference numeral 19 denotes a DF / F that latches the updated predicted value output from the prediction / probability update unit and the estimated probability value. The other components have the same functions as the components denoted by the same reference numerals in FIG.

The timing of the decoding process in the decoding block having the above configuration is determined by the pixel bit {i + 1}.
The case of processing pixel bit {i + 3} [1] from [1] will be described with reference to FIG.

First, in the first cycle, {i + 1} [1]
The predicted value and the probability estimated value corresponding to
Read from 09. The selector 813 is controlled so as to alternately select the probability estimated value memories 809 and 811 every cycle, and selects the output from the probability estimated value memory 809 here. Also, the selector 815, when the conditions of (read address = write address), (decoded pixel value of the current cycle = decoded pixel value of one cycle before), and (at the time of memory update) are satisfied, similarly to the selector 615 of FIG. Only the output of the DF / F 819 is selected. Therefore, normally, the output of the switch 813 is selected. The read prediction value and probability estimation value are temporarily latched by the DF / F 817.

In the next cycle 2, the predicted value and the probability estimated value latched by the DF / F 817 are calculated by the arithmetic decoding operation unit 30.
1 and the encoded data of {i + 1} [1] is arithmetically decoded. As a result of this arithmetic operation, the decoded pixel value is obtained as a part of the context information. However, since the decoded pixel value is determined in the latter half of the cycle, it is once latched in the DF / F 803 to use this context information as a stable signal. I do. As a result, the context information output from the DF / F 803 is a signal delayed by one cycle, but can be used as a stable signal from the beginning of the cycle.

Since the probability estimation value is also determined in the second half of the cycle, it is latched by the DF / F 918 to use it as a stable signal.

During the cycle 2, the predicted value and the estimated probability value corresponding to {i} [2] are read from the estimated probability value memory 811 in parallel with the above processing, and the DF / F 817 is read.
Latch.

In the next cycle 3, the updated prediction / probability estimation value for {i + 1} [1] latched in the DF / F 819 is written to the probability estimation value memory 809 in accordance with the normalization processing. At the same time, the prediction value and the probability estimation value latched by the DF / F 817 are input to the arithmetic decoding operation unit 301, and the encoded data of {i} [2] is arithmetically decoded.
The decoded pixel value is latched by the DF / F 807 together with other information as a part of the context information.

During the cycle 3, the predicted value and the estimated probability value corresponding to {i + 2} [1] are read out from the estimated probability value memory 809 in parallel with the above processing, and the DF / F8
Latch by 17.

In the next cycle 4, the updated prediction / probability estimation value for {i} [2] latched in the DF / F 819 is written to the probability estimation value memory 811 in response to the normalization processing. At the same time, the prediction value and the probability estimation value latched by the DF / F 817 are input to the arithmetic decoding operation unit 301. As shown in FIG. 10, the prediction value and the probability estimation value used when decoding the encoded data of {i + 2} [1] are based on the context information of {i + 1} [1] determined in cycle 2. Value. {I + 2} [1] is arithmetically decoded using the predicted value and the probability estimate,
Further, the updated prediction / probability estimation value obtained by the prediction probability update unit 501 is latched by the DF / F 819.

During cycle 4, the predicted value and the estimated probability value corresponding to {i + 1} [2] are read out from the estimated probability value memory 811 in parallel with the above processing, and the DF / F8
Latch by 17.

In the next cycle 5, the update prediction / probability estimation value corresponding to {i + 2} [1] latched in the DF / F 819 is stored in the probability estimation value memory 80 in response to the normalization processing.
9 is written. At the same time, the prediction value and the probability estimation value latched by the DF / F 817 are output to the arithmetic decoding operation unit 301.
To enter. As shown in FIG. 10, {i + 1}
The prediction value and the probability estimation value used when decoding the encoded data of [2] are {i + 1} determined in cycle 2
This is a value based on the context information of [1] and the context information of {i} [2] determined in cycle 3. {I + 1} [2] is arithmetically decoded using the prediction value and the probability estimation value, and the updated prediction / probability estimation value obtained by the prediction probability updating unit 501 is latched by the DF / F 819.

During cycle 5, the predicted value and the estimated probability value corresponding to {i + 3} [1] are read out from the estimated probability value memory 809 in parallel with the above processing, and the DF / F8
Latch by 17.

The processing according to the above procedure is repeated for all the pixel bits.

As described above, the decoded pixel value as the context information which has been two cycles ahead is also converted to the DF once.
/ F803, and after reading the memory,
Latching at -F / F817 causes a delay of two cycles, and finally matches the phase in arithmetic decoding operation unit 301.

As described above, according to the first embodiment of the present invention, a plurality of bit planes constituting a multi-valued image are coded by being shifted by several pixels between the planes. That is, when encoding a certain bit plane, another bit plane referred to as context information is encoded several pixels ahead of the bit plane of the pixel bit to be decoded, and the decoding is performed in the same order as the encoding. Since the processing is performed, the decoding operation speed can be significantly increased when the decoding processing is performed by hardware.

[Second Embodiment] In the second embodiment, an arithmetic coding method for a multi-valued image in which one pixel is composed of 4 bits and an arithmetic decoding device corresponding to the arithmetic coding method will be described.

FIG. 11 is a diagram showing the encoding / decoding order in the second embodiment. Arithmetic encoding / decoding is performed in the order indicated by the arrows in FIG. That is,
{I} [1], {i-1} [2], {i-2} [3],
{I-3} [4], {i + 1} [1], {i} [2],
{I-1} [3], {i-2} [4], {i + 2}
[1], {i + 1} [2], {i} [3], {i-1}
Encoding / decoding is performed in the order of [4], {i + 3} [1],. Here, ｛｝ [1] represents the most significant bit plane and ｛｝ [4] represents the least significant bit plane.

When encoding the most significant bit plane, only the most significant bit encoded before is referred to. That is, the context information for encoding the most significant bit plane is configured using only the most significant bit encoded before.

When encoding a bit plane other than the most significant bit plane, reference is made to bits of the same plane encoded earlier and higher-order bits encoded earlier than the bit. In the above coding order, the bits of the same plane that can be referenced when encoding {i} [2] are {i−1} [2], and the upper bits are the bits {i−1} to be referenced.
Upper bits encoded before encoding [2], that is, upper bits before {i} [1]. Actually, a part of the bits of the same plane before {i-1} [2] and {i} [1] are referred to.

However, as in the first embodiment, there occurs a timing for processing a bit of a pixel that does not exist near the leading edge and the trailing edge of an image. That is, at the top of the image, {1}
[1], {0} [2], {-1} [3], {-2}
[4], {2} [1], {1} [2], {0} [3],
{-1} [4], {3} [1], {2} [2], {1}
[3], {0} [4], {4} [1], {3} [2],
If processing is performed in the order of {2} [3], {1} [4], the bits to be processed in the second, third, fourth, seventh, eighth, and twelfth bits actually exist. It is a pixel that does not. As in the first embodiment, a dummy bit of 0 may be encoded. However, in the second embodiment, where there is no bit information, the encoding is not performed. Effective pixel timing generation circuit 1 shown
053 and the mask circuit 1054 set the probability estimation value to 0. If the probability estimation value is 0, the values of the A register 201 and the C register 202 in the arithmetic decoding operation unit 301 do not change, which is the same as not performing the encoding process. This configuration has the advantage that the code length can be shortened because no extra code is generated compared to the method of coding the dummy bits.

In the first embodiment described above, the context information necessary for decoding the bit information to be decoded is determined two cycles before the context information. However, in the second embodiment, the necessary information is determined. The context information is determined four cycles before. Since the decoding order is exactly the same as the encoding order, the above-mentioned..., {I} [1], {i−1} [2],
{I-2} [3], {i-3} [4], {i + 1}
[1], {i} [2], {i-1} [3], {i-2}
[4], {i + 2} [1], {i + 1} [2], {i}
[3], {i-1} [4], {i + 3} [1], ...
Are performed in this order.

First, consider the most significant bit plane. Since the decoding of the most significant bit refers only to the most significant bit coded before, the context information necessary to decode {i + 1} [1] is {i}
The decoding of {i} [1], which is the most significant bit information before [1] and before, is {i + 1}
It ends four cycles before [1].

Next, another bit plane will be considered. Decoding of the upper bits {i} [j] referred to when encoding {i} [j + 1] is completed 5 cycles before {i} [j + 1]. The reference bit on the same plane ends four cycles before. Therefore, it can be understood that the context information necessary for the decoding process of the bit of interest is determined four cycles before in any plane.

The second embodiment is different from the first embodiment in that the bit plane is expanded from 2 bits to 4 bits. The second embodiment is different from the first embodiment in that a state value is used as a value held in a memory and a bypass is used. And a means for encoding only effective pixels is added.

The configuration of a decoding block for generating a context using the above-described reference bit information and decoding the encoded data by hardware will be described with reference to FIG.

In the figure, reference numeral 1010 denotes context information for decoding the most significant bit plane, reference numeral 1011 denotes a DF / F for latching the context information 1010, 1
020 is context information for decoding the second most significant bit plane, and 1021 is context information 10
DF / F that latches 20 is the context information for decoding the third most significant bit plane,
1031 latches context information 1030 D-
F / F, 1040 is context information for decoding the least significant bit plane, 1041 is context information 1
DF / F latching 040, 1012 is a prediction state memory used when decoding the most significant bit plane, 1
022 is a prediction state memory used when decoding the second most significant bit plane; 1032 is a prediction state memory used when decoding the third most significant bit plane;
1042 is a prediction state memory used when decoding the least significant bit plane, 1050 is a selector for selecting one of the outputs of the four prediction state memories 1012, 1022, 1032 and 1042, and 1051 is a prediction state output from the selector DF / F 109 for latching a value, a probability estimator 109 for converting a state value into a probability estimate LSZ, 105
Reference numeral 3 denotes an effective pixel timing generation circuit that outputs 1 when the estimated value of the effective pixel is converted, 1054 denotes a mask circuit that forcibly masks the estimated value of the invalid pixel to 0, and 1055 denotes a mask. A DF / F 1056 for latching the probability estimation value output from the circuit, a prediction state updating unit 1056 for predicting an updated state value from the current probability estimation value,
1057, a DF / F that latches the update value of the prediction state;
Reference numeral 1058 denotes a DF / F for latching the decoded bit information.
It is. The other components have the same functions as the components denoted by the same reference numerals in FIG.

The configuration in which the state value is stored in the memory is possible because the context is determined four cycles before, so that an extra delay necessary for generating the probability estimation value can be tolerated. For example, when a certain state value is output from the prediction state memory 1012, the decoded bit information is output from the exclusive NOR gate 305 by arithmetic decoding two cycles later, so that the DF / F 1058 adds one more cycle delay. After 4 cycles, the DF / F 1011 latches as part of the context of the next pixel. Since the state value has a smaller bit width than the probability estimation value, this configuration is preferable to reduce the memory capacity and the circuit scale.

It is not necessary to bypass the update data to the memories because reading from each memory is performed every four cycles. For example, if a state value is output from the predicted state memory 1012 and the state value is further updated, the updated value is set to the DF / F 1057 three cycles later. That is, if the update value is written to the memory 1012 three cycles later, the updated state value can be read in the next cycle even if the same context as that generated four cycles ago occurs.

The above processing timing is shown in FIG.
3.

As described above, according to the second embodiment, a plurality of bit planes constituting a multi-valued image are coded by being shifted by several pixels between the planes. That is, when encoding a certain bit plane, another bit plane referred to as context information is encoded several pixels ahead of the bit plane of the pixel bit to be decoded, and the decoding is performed in the same order as the encoding. Since the processing is performed, the decoding operation speed can be significantly increased when the decoding processing is performed by hardware.

Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine, a facsimile, etc.) Device).

[0142]

As described above, according to the present invention, the decoding speed of an encoded multi-level image can be increased with hardware having a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an encoding block that performs a conventional arithmetic encoding process.

FIG. 2 is a block diagram illustrating a configuration example of an arithmetic coding operation unit illustrated in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a decoding block that performs a conventional arithmetic decoding process.

FIG. 4 is a block diagram illustrating a configuration example of an arithmetic decoding operation unit illustrated in FIG. 3;

FIG. 5 is a block diagram illustrating another configuration of a decoding block that performs a conventional arithmetic decoding process.

FIG. 6 is a block diagram showing another configuration of a decoding block that performs a conventional arithmetic decoding process.

FIG. 7 is a diagram illustrating a conventional encoding / decoding order.

FIG. 8 is a diagram illustrating an encoding / decoding order in the first embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a decoding block that performs an arithmetic decoding process according to the first embodiment of the present invention.

10 is a diagram illustrating processing timing when decoding is performed by the decoding block illustrated in FIG. 9;

FIG. 11 is a diagram illustrating an encoding / decoding order in the second embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of a decoding block that performs an arithmetic decoding process according to the second embodiment of the present invention.

FIG. 13 is a diagram illustrating processing timing when decoding is performed by the decoding block illustrated in FIG. 12;

[Explanation of symbols]

101 terminal 102 binary data PIX signal 103 context information 105 prediction state memory 106 prediction value 107 state value 109 probability estimation unit 111 probability estimation value LSZ 113 exclusive NOR gate 114 coincidence / mismatch signal 115 arithmetic coding operation unit 117 encoded data 118 signal 119 prediction state update unit 120 control signal 201 A register 203 code register 205 subtractor 207 adder 209 selector 211 selector 213 shift register 215 output register 217 counter 218 terminal 219 mask circuit 220 shift clock 221 detector 301 arithmetic decoding operation Section 302 signal 304 decoded pixel value signal 305 exclusive NOR gate 306 coded data 401 subtractor 403 input buffer register 405 shift register 501 Prediction probability update unit 503 Probability estimation value memory 601 First probability estimation value memory 602 Second probability estimation value memory 603, 605 Selector 607 DF / F 609 Delay circuit 610 Context information 801, 805 Context information 803, 807 , 817, 819 DF / F 809, 811 Probability estimated value memory 813, 815 Selector 1010, 1020, 1030, 1040 Context information 1011, 1021, 1031, 1041 DF / F 1012, 1022, 1032, 1042 Prediction state Memory 1050 Selector 1051, 1055, 1057, 1058 DF / F 1053 Effective pixel timing generation circuit 1054 Mask circuit 1056 Prediction state update unit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C059 KK12 MA00 ME11 PP01 UA02 UA05 UA33 5C078 AA04 BA32 BA37 DA01 DA02 5J064 AA03 BB03 BC02 BC03 BC04 BC05 BC14 BC28 BD01 9A001 EE03 EE04 HH27

Claims (15)

[Claims] 1. An arithmetic encoding method for arithmetically encoding multi-valued image information comprising a plurality of bit planes with reference to context information, wherein context information for an encoding target pixel is at least two of said encoding target pixel. An arithmetic coding method characterized in that a coding order is determined so as to be determined in advance of a cycle. 2. When the number of bit planes is m and the number of pixels is represented by {} and the bit plane is represented by [], the encoding order is j next to {i} [j]. ≠
{i-1} [j + 1] for m, {i + for j = m
The arithmetic coding method according to claim 1, wherein 1｝ [1]. 3. When the number of pixels to be encoded is n,
3. The arithmetic encoding method according to claim 2, wherein a predetermined value is encoded when {i-1} ≤0 and {i + 1}> n. 4. When the number of pixels to be encoded is n,
3. The arithmetic coding method according to claim 2, wherein coding is skipped when {i-1} ≤0 and {i + 1}> n. 5. An arithmetic decoding method for arithmetically decoding multi-valued image information composed of a plurality of bit planes with reference to context information, wherein context information for a decoding target pixel is at least two of said decoding target pixel. An arithmetic decoding method, wherein a decoding order is determined so as to be determined in advance of a cycle. 6. The decoding order is as follows: If the number of bit planes is m, and the pixel number is represented by {} and the bit plane is represented by [], the next of {i} [j] is j ≠
{i-1} [j + 1] for m, {i + for j = m
The arithmetic decoding method according to claim 5, wherein 1｝ [1]. 7. When the number of pixels to be decoded is n,
7. The arithmetic decoding method according to claim 6, wherein a predetermined value is decoded when {i-1} ≤0 and {i + 1}> n. 8. When the number of pixels to be decoded is n,
7. The arithmetic decoding method according to claim 6, wherein decoding is skipped when {i-1} ≤0 and {i + 1}> n. 9. An arithmetic coding apparatus for arithmetically coding multi-valued image information consisting of a plurality of bit planes with reference to context information, wherein context information for the coding target pixel is a processing timing of the coding target pixel. An arithmetic coding device for performing decoding in an order determined at least two cycles earlier. 10. An arithmetic decoding device for arithmetically decoding coded multi-valued image information comprising a plurality of bit planes with reference to context information, wherein the context information for a pixel to be decoded is An arithmetic decoding apparatus, wherein decoding is performed in an order determined at least two cycles earlier than a pixel processing timing. 11. A probability estimation value memory provided for each bit plane for holding a prediction value and a probability estimation value, and a prediction estimation updating unit for updating the prediction value and the probability estimation value based on the determined context information. The arithmetic decoding apparatus according to claim 10, further comprising: reading a predicted value and a probability estimation value from the probability estimation value memory using the determined context information as an address. 12. A predictive state memory provided for each bit plane for storing a predictive value and a state value, and a predictive state update unit for updating the predictive value and the state value based on the determined context information. The arithmetic decoding apparatus according to claim 10, wherein the predicted value and the state value are read from the predicted state memory using the determined context information as an address. 13. When the number of bit planes is m and the number of pixels is represented by {} and the bit plane is represented by [], the decoding order is j next to {i} [j].
{I-1} [j + 1] for ≠ m, ｛i + for j = m
13. The method according to claim 10, wherein 1｝ [1].
The arithmetic decoding device according to any one of the above. 14. When the number of pixels to be decoded is n,
14. The arithmetic decoding apparatus according to claim 13, wherein a predetermined value is encoded / decoded when {i-1} ≤0 and {i + 1}> n. 15. When the number of pixels to be decoded is n,
14. The arithmetic decoding apparatus according to claim 13, wherein decoding is skipped when {i-1} ≤0 and {i + 1}> n.