JP2010278567A - Decoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve decoding performance when decoding image data compressed and encoded by a compression encoding algorithm using both of a predictive encoding and variable length encoding. <P>SOLUTION: A decoding device has a reverse predictive encoding part which executes predictive value calculation processing for setting each pixel whose prediction error is expressed by predictive encoding data as a processing target pixel and calculating a predictive value of a pixel value of the pixel from size relation in the pixel values of a plurality of peripheral pixels and addition processing for reconstructing the pixel value of the processing target pixel by adding the predictive error indicated by the predictive encoding data to the predictive value, and which executes first operation for referring to only the pixel values of pixels which are not arranged in a horizontal scanning line direction to the processing target pixel out of the plurality of peripheral pixels prior to second operation other than the first operation and stores an operation result of the first operation in a register until the execution of the second operation. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique for restoring original image data from predictive encoded data obtained by performing predictive encoding on image data.

  Image data compression coding techniques are roughly classified into lossy compression coding techniques and lossless compression coding techniques. Many irreversible compression encoding techniques use orthogonal transformation, and the original image data cannot be completely restored from the compression encoded data, but has an advantage that a high compression rate can be obtained. On the other hand, as an example of the lossless compression coding technique, there is a technique in which predictive coding and variable length coding are used in combination, such as JPEG-LS (Lossless-JPEG) of JPEG (Joint Photographic Experts Group). Although this type of lossless compression encoding technique cannot obtain a high compression rate, there is an advantage that the original image data can be completely restored from the compression encoded data (hereinafter referred to as compression encoded data). . For this reason, lossless compression coding technology is used for applications such as storage and exchange of medical images. Note that there is Patent Document 1 as a document related to the lossless compression coding technique.

JP-A-9-37271

  Various image processing apparatuses have been proposed in which compression-coded data of a sprite image is read from a memory and decoded, and a sprite image as a result of the decoding is displayed on a monitor. In this type of image processing apparatus, when it is required to completely restore a sprite image before compression encoding, the image data of the sprite image is converted into compression encoded data by using a lossless compression encoding technique to store the memory. It is necessary to decode (decode) the compressed encoded data stored in the memory and read from the memory. In general, the decoding performance of an image processing apparatus that decodes compression-encoded data is evaluated by the number of pixels that can be decoded per clock. In decoding of compression-encoded data obtained by lossless compression encoding technology, In many cases, sufficient decoding performance cannot be obtained. The reason is as follows.

  In a compression encoding algorithm using both predictive encoding and variable length encoding, pixels to be compression encoded (hereinafter referred to as processing target pixels) are sequentially selected in the order of arrangement in the image, and peripheral pixels (typically Specifically, the pixel value of the processing target pixel is predicted from the pixel value of each pixel located on the left side of the processing target pixel, right above and at the upper left) (hereinafter, predicted value calculation processing), and the actual pixel of the processing target pixel Compression encoding is performed by variable-length encoding the difference between the value and the predicted value (hereinafter, prediction error). For example, when the pixel Md shown in FIG. 8A is a processing target pixel, the difference between the predicted value calculated from the pixel values of the pixel Ma, the pixel Mb, and the pixel Mc and the actual pixel value of the pixel Md. Certain prediction errors are variable length coded. On the other hand, the decoding of the compressed encoded data is similar to the compression encoding using the predictive encoded data after restoring the predictive encoded data by performing the variable length decoding process which is the inverse operation of the variable length encoding process. In addition, this is realized by performing the inverse predictive coding process in the pixel arrangement order (in the order of pixel Mc → pixel Mb → pixel Ma → pixel Md in FIG. 8A). For example, in the inverse prediction encoding process for the pixel Md in FIG. 8A, a prediction value calculation process for predicting the pixel value of the pixel Md from the pixel values of the decoded peripheral pixels is performed, and the prediction error is added to the prediction value. Is added (hereinafter referred to as addition processing) to obtain a pixel value Xd. The point to be noted here is that when the pixel Md shown in FIG. 8A is decoded, it is necessary to obtain the pixel value of the pixel Ma on the left side of the pixel Md. The addition process can be performed only in units of one pixel. For this reason, if a plurality of pixels are to be decoded at a time using a clock as a trigger, it is necessary to repeatedly execute the predicted value calculation process and the addition process within one clock by the number of pixels to be decoded. For example, in FIG. 8B, when trying to decode the pixels Mx1 to Mx3 at a time with one clock using the prediction errors Diff1 to Diff3 of the pixels Mx1 to Mx3, one pixel as shown in FIG. 8C. It is necessary to sequentially execute the process Pn (n = 1 to 3) including the predicted value calculation process and the addition process for the minute. For this reason, the number of pixels that can be decoded at one clock is naturally limited depending on the time required to execute the process P-n (the total of the calculation time of the predicted value calculation process and the addition process and the input / output waiting time). Will be. This is the reason why sufficient decoding performance cannot be obtained in an apparatus that decodes compression-encoded data obtained by the lossless compression encoding technique.

  The present invention has been made in view of the above problems, and improves decoding performance when decoding image data compression-encoded by a compression encoding algorithm using both predictive encoding and variable-length encoding. The purpose is to provide technology.

  In order to solve the above-mentioned problem, the present invention is calculated from the magnitude relationship of the pixel values of a plurality of surrounding pixels located in the vicinity of the target pixel when each of the plurality of pixels constituting the image is the target pixel. Predictive encoded data obtained by arranging prediction errors representing the difference between the predicted value of the pixel value of the target pixel and the actual pixel value of the target pixel in the pixel arrangement order is obtained, and the image is obtained from the predictive encoded data. In the decoding device that restores image data representing a pixel, each pixel in which a prediction error is represented by the prediction encoded data is set as a processing target pixel, and the predicted value of the pixel value is determined from the magnitude relationship of the pixel values of the plurality of surrounding pixels. An inverse predictive encoding unit that executes a predictive value calculation process to be calculated and an addition process for restoring the pixel value by adding a prediction error indicated by the predictive encoded data for the pixel to be processed to the predictive value A first calculation that refers only to pixel values of the plurality of peripheral pixels that are not aligned with the pixel to be processed in the horizontal scanning line direction is executed prior to the other second calculations. A decoding device is provided that includes an inverse predictive encoding unit that holds a calculation result of the first calculation until the execution of the second calculation.

  In order to solve the above problem, the present invention is calculated from the magnitude relationship of the pixel values of a plurality of surrounding pixels located in the vicinity of the target pixel when each of the plurality of pixels constituting the image is the target pixel. The prediction error is variable-length encoded into prediction encoded data obtained by arranging prediction errors representing the difference between the predicted value of the pixel value of the target pixel and the actual pixel value of the target pixel in the pixel arrangement order. In a decoding device that obtains compressed encoded data obtained by performing variable length encoding processing and restores image data representing the image from the compressed encoded data, variable length that is an inverse operation of the variable length encoding processing A variable length decoding unit that performs decoding processing on the compressed encoded data and restores the predicted encoded data, and a prediction error represented by the predicted encoded data obtained by the variable length decoding unit A prediction value calculation process for calculating a prediction value of the pixel value from the magnitude relationship of the pixel values of the plurality of surrounding pixels, and a prediction obtained by the variable length decoding unit for the pixel to be processed A reverse prediction encoding unit that performs an addition process of adding a prediction error indicated by encoded data to the prediction value to restore a pixel value, and a processing target pixel and a horizontal scanning line among the plurality of peripheral pixels The first calculation that refers only to the pixel values that are not arranged in the direction is executed prior to the other second calculation, and the calculation result of the first calculation is held until the second calculation is executed. There is provided a decoding device characterized by having an inverse predictive encoding unit.

  According to such a decoding apparatus, the first calculation that refers only to the pixel value of a plurality of peripheral pixels that are not aligned with the pixel to be processed in the horizontal scanning line direction is different from the second calculation other than that. It is executed in advance (for example, the first operation is executed one clock ahead of the second operation), and the number of prediction value calculation processes and addition processes that can be executed during one clock increases. . For this reason, the number of pixels that can be decoded at one clock at a time is increased as compared to the conventional case, and the decoding performance can be improved.

It is a figure which shows the structural example of the image processing LSI300 which is one Embodiment of this invention. 3 is a diagram illustrating a configuration example of a pattern data decoder 305 of the image processing LSI 300. FIG. It is a figure for demonstrating the decoding process by the pattern data decoder. It is a figure which shows the structural example of the 1st reverse prediction encoding part 542. It is a figure which shows the structural example of the 2nd reverse prediction encoding part 544. It is a figure for demonstrating the reverse prediction encoding of the pixel located in the right end of these three pixels, when a prediction error is zero about three continuous pixels. It is a figure which shows the decoding result about the three pixels. It is a figure which shows the outline of the decoding procedure of the compression coding which used prediction coding and variable length coding together, and the image data to which the compression coding was performed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating a configuration example of an image processing LSI 300 according to an embodiment of the present invention. The image processing LSI 300 is incorporated in a game machine, for example, and displays a sprite image representing a game character or the like on the monitor 403 under the control of a CPU (Central Processing Unit) 402 that functions as a control center of the game machine.

  The sprite pattern memory 401 stores compression-coded data for a plurality of types of sprite images each representing a game character or the like. These compression-encoded data are obtained by performing lossless compression encoding using predictive encoding and variable-length encoding on image data representing pixel values of each pixel constituting a sprite image. The reason why lossless compression coding is used for compression coding of image data of sprite images is that game characters and the like are often designed by graphic designers, so that their design is not impaired, before compression coding. This is because it is necessary to completely restore the sprite image. These compressed and encoded data are generated by the following procedures <1> to <3>.

<1> First, when each of a plurality of pixels constituting a sprite image is a target pixel, a plurality of peripheral pixels located in the vicinity of the target pixel (in this embodiment, as shown in FIG. 8A described above). The predicted value for the pixel value of the pixel of interest is calculated from the magnitude relationship of the pixel values of the pixels located on the left of the pixel of interest, directly above and on the upper left. For example, when the pixel Md illustrated in FIG. 8A is the target pixel, and the pixel values of the pixel Ma, the pixel Mb, and the pixel Mc are the pixel value Xa, the pixel value Xb, and the pixel value Xc, the predicted value X is Calculate as follows.
(A) When the pixel value Xc is the maximum among the pixel value Xa, the pixel value Xb, and the pixel value Xc, if the pixel value Xa> the pixel value Xb, the predicted value X = the pixel value Xb (case 1)
If pixel value Xb> pixel value Xa, predicted value X = pixel value Xa (Case 2)
(B) When the pixel value Xc is the smallest among the pixel value Xa, the pixel value Xb, and the pixel value Xc, if the pixel value Xa <the pixel value Xb, then the predicted value X = the pixel value Xb (Case 3)
If pixel value Xb <pixel value Xa, predicted value X = pixel value Xa (case 4)
(C) In other cases (when the pixel value Xc is not maximum and not minimum)
Predicted value X = pixel value Xa + pixel value Xb−pixel value Xc (case 5)

  <2> Next, a prediction error that is a difference between the prediction value X and the actual pixel value is calculated for each pixel constituting the sprite image, and the prediction errors are arranged in the pixel arrangement order to obtain “prediction encoded data”. And For example, if the actual pixel value of the pixel Md is the pixel value Xd, the difference between the pixel value Xd and the predicted value X (pixel value Xd−predicted value X) is the prediction error.

  <3> Next, the compression-encoded data is obtained by performing variable-length encoding processing on each prediction error represented by the predicted encoded data. In this variable-length encoding process, entropy encoding including encoding by zero run length (encoding as ZERO = N when N prediction errors of consecutive N (an integer of 2 or more) are zero) is performed. An algorithm may be adopted. This is to further increase the compression rate. An example of the entropy encoding algorithm is a Huffman encoding algorithm.

  In the image processing LSI 300, a CPU I / F (interface) 301 is a device that receives various types of control information from the CPU 402. The storage unit 302 is a device that stores control information provided from the CPU 402 via the CPU I / F 301, and is configured by, for example, a RAM (Random Access Memory). The control information given from the CPU 402 includes the storage destination address in the sprite pattern memory 401 for the compression encoded data of the sprite image to be decoded and reproduced, the display position of the sprite image on the display screen of the monitor 403, and the sprite image. Instructions regarding enlargement / reduction of the image are included.

  The control unit 303 is a control center that controls each unit in the image processing LSI 300 in accordance with various control information stored in the storage unit 302. The pattern memory I / F 304 is a device that reads out the compressed encoded data of the sprite image from the sprite pattern memory 401 under the control of the control unit 303. The pattern data decoder 305 receives the compressed encoded data of the sprite image from the sprite pattern memory 401 via the pattern memory I / F 304 under the control of the control unit 303, performs decoding, and decodes the image data before the compression encoding. It is a device that outputs. The pattern data decoder 305, the sprite rendering processor 306, and the line buffers 307A and 307B are sprite image data to be displayed on the monitor 403 in units of one line (one horizontal scanning line) under the control of the control unit 303. And the process of reflecting the image data on the display screen of the monitor 403 is performed. That is, the image processing LSI 300 is a line buffer type image processing apparatus that reproduces an image in units of one line.

  More specifically, the line buffers 307A and 307B each have a capacity for storing image data for one line of the monitor 403. The control unit 303 uses these line buffers 307A and 307B alternately. For example, during the period when the image data for one line in the line buffer 307A is displayed on the monitor 403, the image data for the next line is displayed. In the period in which the sprite rendering processor 306 executes rendering to be written to the line buffer 307B and the image data for one line in the line buffer 307B is displayed on the monitor 403, the image data for the next line is stored in the line buffer 307A. Causes the sprite rendering processor 306 to execute the writing rendering. Further, the control unit 303 performs control for causing the pattern data decoder 305 to output image data of one line of sprite images to be rendered in time for rendering performed by the sprite rendering processor 306. That is, the compression encoded data necessary for obtaining the image data of one line of sprite image is read from the sprite pattern memory 401 and supplied to the pattern data decoder 305, and control is performed to perform the decoding. . Here, a plurality of types of sprite images may be displayed on one line of the monitor 403. In such a case, the control unit 303 reads out compressed encoded data necessary for obtaining image data for one line of all sprite images to be displayed from the sprite pattern memory 401 and supplies the compressed data to the pattern data decoder 305. Then, control for performing the decoding is performed. The pattern data decoder 305 performs the decoding of the compression encoded data necessary for obtaining the image data for one line, using a system clock given from a clock generator (not shown in FIG. 1) as a trigger. However, the present embodiment is characterized in that the configuration of the pattern data decoder 305 is devised so that a larger number of pixels can be decoded than in the past in one clock. This will be described in detail later.

The display controller 308, the image data controller 309, and the monitor I / F 310 are means for alternately reading out image data for one line from the line buffers 307A and 307B, supplying the image data to the monitor 403, and causing the monitor 403 to display an image. More specifically, the display controller 308 supplies a vertical synchronization signal and a horizontal synchronization signal to the monitor 403 via the monitor I / F 310, and in addition, the image data controller 309 is instructed to read out image data in synchronization with the horizontal synchronization signal. Send. The image data controller 309 alternately selects the line buffers 307A and 307B each time an image data read command is received, reads image data for one line from the selected line buffer, and monitors the monitor 403 via the monitor I / F 310. Send to.
The above is the configuration of the image processing LSI 300.

FIG. 2 is a block diagram illustrating a configuration example of the pattern data decoder 305.
As shown in FIG. 2, the pattern data decoder 305 includes a variable length decoding unit 3052 and an inverse prediction encoding unit 3054. The variable length decoding unit 3052 performs the variable length decoding process, which is the inverse operation of the variable length encoding process described above, on the compressed encoded data given via the pattern memory I / F 304 to restore the prediction encoded data. To the inverse predictive coding unit 3054.

  The inverse predictive encoding unit 3054 performs reverse predictive encoding processing, which is an inverse operation of the predictive encoding processing described above, on the predictive encoded data provided from the variable length decoding unit 3052, and restores image data. The image data is output. As shown in FIG. 2, the inverse prediction encoding unit 3054 includes a first inverse prediction encoding unit 542 and a second inverse prediction encoding unit 544. The first inverse predictive encoding unit 542 has a prediction error that is not zero in the prediction encoded data obtained by the variable length decoding unit 3052, or a pixel that has zero prediction error but adjacent pixels has zero prediction error. Inverse prediction encoding (prediction value calculation processing and addition processing) of non-pixels is performed on a pixel-by-pixel basis. On the other hand, the second inverse prediction encoding unit 544 collectively performs inverse prediction encoding of two consecutive pixels (pixels arranged in the horizontal direction) in which each prediction error is zero.

  For example, when the pixels Mx1 to Mx3 illustrated in FIG. 3A are to be subjected to inverse predictive coding processing, when any of the prediction errors Diff1 to Diff3 indicated by the predictive encoded data is not zero, FIG. As shown in B), the first inverse predictive encoding unit 542 is driven three times during one clock as in the conventional case, and the inverse predictive encoding of the pixels Mx1 to Mx3 is performed pixel by pixel in the pixel arrangement order. However, the first inverse predictive encoding unit 542 of the present embodiment is configured to perform inverse predictive encoding of each pixel by a method that clearly shows the features of the present invention, and thus more than conventional ones. These pixels can be decoded in one clock.

  On the other hand, when Diff1 and Diff2 are zero and Diff3 is not zero, the inverse prediction encoding unit 3054 drives the second inverse prediction encoding unit 544 as shown in FIG. Then, after the inverse predictive encoding of the pixels Mx1 and Mx2 is collectively performed, the first inverse predictive encoding unit 542 is driven to perform the inverse predictive encoding of the pixel Mx3. As described above, in this embodiment, the processing is speeded up by performing inverse predictive coding for two consecutive pixels with a prediction error of 0 at once, so that the subsequent pixels can be decoded in the free time. Thus, the number of pixels that can be decoded in one clock increases. Note that when the prediction error represented by the prediction encoded data is zero for K (K is an integer of 3 or more) consecutive pixels, the second inverse predictive encoding unit 544 is equal to the number of quotients obtained by dividing K by 2. Then, the first inverse predictive coding unit 542 may be driven by the remaining number of times when K is divided by 2. Hereinafter, the first inverse prediction encoding unit 542 and the second inverse prediction encoding unit 544 will be mainly described.

FIG. 4 is a block diagram illustrating a configuration example of the first inverse predictive coding unit 542.
As shown in FIG. 4, the first inverse predictive encoding unit 542 includes seven full adders (full adders 54201 to 54207), three registers (registers 54208 to 54210), a concatenation calculator 54211, and a selector 54212. Contains. Hereinafter, the role of each component of the first inverse predictive coding unit 542 will be described by taking as an example the case of decoding the pixel Mx1 shown in FIG.

  As described above with reference to FIG. 8A, the predicted value of the pixel value of the processing target pixel is determined from the magnitude relationship of the pixel values of the three surrounding pixels. When the pixel Mx1 in FIG. 3A is a processing target pixel, the pixel Ma1, the pixel Mc1, and the pixel Mb1 in FIG. 3A are peripheral pixels. The full adders 54201, 54202, and 54203 in FIG. 4 serve as a comparator that determines the magnitude relationship between the pixel values of the peripheral pixels. More specifically, the full adder 54201 calculates and outputs a value Xc1a1 obtained by subtracting the pixel value Xa1 of the pixel Ma1 from the pixel value Xc1 of the pixel Mc1, and the full adder 54202 outputs the pixel value of the pixel Mb1. A value Xb1a1 obtained by subtracting the pixel value Xa1 from Xb1 is calculated and output, and the full adder 54203 calculates and outputs a value Xc1b1 obtained by subtracting the pixel value Xb1 from the pixel value Xc1. As shown in FIG. 4, the output data Xc1a1 of the full adder 54201 and the output data Xb1a1 of the full adder 54202 are given to the concatenation calculator 54211, and the output data Xc1b1 of the full adder 54203 is adjusted in the output timing by the register 54208. Then, it is given to the concatenation calculator 54211. The reason for adjusting the output timing by the register 54208 only for the output data Xc1b1 of the full adder 54203 will be clarified later.

The concatenation calculator 5421 gives the selector 54212 the 2-bit control signal S1 shown in Table 1 according to the combination of the sign bit values of the output data of the full adders 54201, 54202, and 54203. For example, the concatenated arithmetic unit 5421 is configured to output each of the output data Xc1b1, Xc1a1, and Xb1a1 when the sign bit of each of the output data Xc1b1, Xc1a1, and Xb1a1 is 0 (that is, when each output data is a non-negative value). When the sign bit is 1 (that is, when each output data is a negative value), a 2-bit control signal S1 having a value of “00” is given to the selector 54212, and so on.

  The full adder 54206 calculates a value Xa1_Diff = Xa1 + Diff1 obtained by adding the prediction error Diff1 to the pixel value Xa1, and outputs it to the selector 54212. The full adder 54204 adds the prediction error Diff1 to the pixel value Xb1, and calculates and outputs a value W_Diff = pixel value Xb1−pixel value Xc1 + Diff1 obtained by subtracting the pixel value Xc1 from the addition result. The output data W_Diff of the full adder 54204 is given to the full adder 54207 through output timing adjustment by the register 54209. The full adder 54207 calculates a value Xa1b1c1_Diff = pixel value Xa1 + pixel value Xb1−pixel value Xc1 + Diff1 obtained by adding the pixel value Xa1 to the output data W_Diff given via the register 54209, and supplies the calculated value to the selector 54212. The full adder 54205 calculates and outputs a value Xb1_Diff = pixel value Xb1 + Diff1 obtained by adding the prediction error Diff to the pixel value Xb1. The output data Xb1_Diff of the full adder 54205 is given to the selector 54212 through adjustment of the output timing by the register 54210.

  The selector 54212 outputs the output data Xa1_Diff of the full adder 54206, the output data Xa1b1c1_Diff of the full adder 54207, or the full adder 54205 given via the register 54210 according to the value of the control signal S1 given from the concatenation calculator 5421. Output data Xb1_Diff is output as a pixel value Xd1. More specifically, the selector 54212 outputs Xa1_Diff as the pixel value Xd1 when the signal value of the control signal S1 is “00”, and when the signal value of the control signal S1 is “01”. Xb1_Diff is output as the pixel value Xd1, and when the signal value of the control signal S1 is “10”, Xa1b1c1_Diff is output as the pixel value Xd1. In this way, the pixel value of the pixel Xd output from the selector 54212 is output to the processing circuit at the subsequent stage after adjusting the output timing by a register (not shown).

  For example, when pixel value Xc1> pixel value Xa1> pixel value Xb1, output data Xc1b1> 0, output data Xc1a1> 0, and output data Xb1a1 <0. Therefore, the sign bit of output data Xc1b1 and Xc1a1 is 0, and output data The sign bit of Xb1a1 is 1, and the control signal S1 is “01” (see Table 1 above). For this reason, Xb1 + diff1 is output as the pixel value Xd1. The case where the pixel value Xc1> the pixel value Xa1> the pixel value Xb1 is the case where the pixel value Xc1 is the maximum and the pixel value Xa1> the pixel value Xb1, so this is nothing but the case described above (Case 1). . When pixel value Xa1> pixel value Xc1> pixel value Xb1, the sign bits of the output data Xc1b1, Xc1a1, and output data Xb1a1 are 0, 1, 0, so the control signal S1 is “10”. Pixel value Xa1 + pixel value Xb1-pixel value Xc1 + diff1 is output as pixel value Xd1. The case of pixel value Xa1> pixel value Xc1> pixel value Xb1 is a case where the pixel value Xc1 is neither the maximum nor the minimum, and this is none other than the above (Case 5). As described above, in this embodiment, each of the above-described (Case 1) to (Case 5) is performed by causing each of the full adders 54201 to 54207, the concatenation computing unit 54211, and the selector 54212 to perform the above-described computations. Output data is obtained. That is, letting each of the full adders 54201 to 54207, the concatenated computing unit 5421, and the selector 54212 perform the above-described computations is equivalent to performing the above-described prediction value calculation processing and addition processing.

  Each of the registers 54208, 54209, and 54210 in FIG. 4 outputs the data provided from the preceding circuit with a delay of one clock. The reason why such a circuit for adjusting the output timing is provided is as follows. Of the computations constituting inverse predictive coding, only the pixel values of peripheral pixels (pixels Xc1 and Xb1 in FIG. 3A) that are not on the same line as the pixel to be processed are referred to, and the left of the pixel to be processed (Refer to pixel Xa1 in FIG. 3A) that does not refer to the pixel value (specifically, calculation in full adder 54203, calculation in full adder 54204, and calculation in full adder 54205: , “First operation”) can be executed one clock ahead of other operations (hereinafter referred to as second operation). Each of the registers 54208, 54209, and 54210 in FIG. 4 is provided to hold an operation result of the first operation executed one clock ahead for the second operation.

  For this reason, as shown in FIG. 3B, even when the first inverse predictive encoding unit 542 is driven three times to perform inverse predictive encoding of the pixels Mx1 to Mx3, the pixel value Xd1 to the pixel value Among the operations for calculating Xd3, the first operation is executed prior to the second operation at the immediately preceding clock (for example, a clock for decoding the pixels Mc1 to Mb3). As a result, the calculation time for obtaining the three pixel values is shortened, and as a result, the number of inverse predictive encoding processes that can be executed per clock is increased as compared with the prior art.

Next, the second inverse prediction encoding unit 544 will be described.
FIG. 5 is a diagram illustrating a configuration example of the second inverse predictive coding unit 544. As illustrated in FIG. 5, the second inverse predictive coding unit 544 includes 11 full adders (full adders 54401 to 54411), four registers (registers 5441 to 54415), and a concatenation calculator 54416. , Selector 54417. Among these components, the registers 54412-54415 put the first operation described above one clock ahead of the other second operations in the same manner as the registers 54208-54210 in the first inverse predictive coding unit 542. This is for holding the calculation result. Hereinafter, when Diff1 = Diff2 = 0 in FIG. 3A, the pixel value Xd1 of the pixel Mx1 and the pixel value Xd2 of the pixel Mx2 are changed to the pixel value Xa1 of the left pixel Ma1 of the pixel Mx1, and the upper left of the pixel Mx1. A procedure for collectively calculating the pixel value Xc1 of the pixel Mc1, the pixel value Xb1 of the pixel Mb1 directly above the pixel Mx1 (that is, the upper left of the pixel Mx2), and the pixel value Xb2 of the pixel Mb2 immediately above the pixel Mx2 will be described. The role played by each component shown in FIG. 5 in this procedure will be described.

  When Diff1 = 0, the pixel value Xd1 of the pixel Mx1 in FIG. 3A is equal to the predicted value determined by the magnitude relationship among the pixel values of the pixel Ma1, the pixel Mc1, and the pixel Mb1 (that is, the addition process is This prediction value is any one of the pixel value Xa1, the pixel value Xb1, or the pixel value Xa1 + the pixel value Xb1−the pixel value Xc1. Since Diff2 = 0, the pixel value Xd2 of the pixel Mx2 is also equal to the predicted value determined by the magnitude relationship among the pixel value Xd1, the pixel value Xb1, and the pixel value Xb2, and this predicted value is the pixel value Xd1, the pixel value Xb2, Alternatively, the pixel value Xd1 + the pixel value Xb2−the pixel value Xb1. Here, since the pixel value Xd1 is any one of the pixel value Xa1, the pixel value Xb1, or the pixel value Xa1 + the pixel value Xb1−the pixel value Xc1, the magnitude between these values and the pixel value Xb2 If the determination of the relationship and the above three determinations for obtaining the value of the pixel value Xd1 are combined, the pixel value Xd1 and the pixel value Xd2 can be calculated in a lump.

The pixel value Xa1, the pixel value Xb1, or the pixel value Xa1 + the pixel value Xb1−the pixel value Xc1 (a value that is a candidate for the pixel value Xd1), the determination of the magnitude relationship between the pixel value Xb1 and the pixel value Xb2, and the pixel value Xd1 If the overlap among the above three determinations for obtaining the value of the pixel value is excluded, determination of the magnitude relationship among the pixel value Xa1, the pixel value Xb1, and the pixel value Xc1, the pixel value Xa1 and the pixel value Xb2 Determination of the magnitude relationship between the pixel value Xb1 and the pixel value Xb2, determination of the magnitude relationship between the pixel value Xb1 and the pixel value Xa1 + pixel value Xb1-pixel value Xc1, and the pixel value Xb2 and the pixel value Xa1 + pixel value Xb1- There are a total of seven determinations of the magnitude relationship of the pixel value Xc1. Therefore, if these seven determinations are made, the pixel value Xd1 and the pixel value Xd2 can be calculated collectively in the manner shown in Tables 2 and 3. In the following Tables 2 and 3, the magnitude relationship between the pixel values is represented by the sign bit of the difference between the two values to be determined. For example, Xb1c1 in Table 2 means a sign bit of the difference between the pixel value Xb1 and the pixel value Xc1, and that this sign bit is zero means that the difference Xb1-Xc1 between the pixel value Xb1 and the pixel value Xc1 is non-negative. Value, that is, pixel value Xb1 ≧ pixel value Xc1. In Tables 2 and 3, when the value of the sign bit is blank, it indicates that the value of the sign bit may be either 0 or 1. Note that the first inverse predictive encoding unit 542 described above calculates a value obtained by subtracting the pixel value Xb1 from the pixel value Xc1 in order to determine the magnitude relationship between the pixel value Xb1 and the pixel value Xc1, The second inverse predictive coding unit 544 is different in that a value Xb1c1 obtained by subtracting the pixel value Xc1 from the pixel value Xb1 is calculated (the same applies to Xa1c1). This is because Xb1c1 and Xa1c1 are used in the subsequent processing.

  The full adders 54401 to 54407 in FIG. 5 are for generating data used for the above seven determinations. For example, the full adder 54401 calculates and outputs the above-described Xb1c1, and the output data Xb1c1 is given to the concatenation calculator 54416 and the full adder 54409 through adjustment of the output timing by the register 54412. The full adder 54402 calculates and outputs a value Xb2b1 obtained by subtracting the pixel value Xb1 from the pixel value Xb2, and the output data Xb2b1 is subjected to output timing adjustment by the register 54413, and the concatenated arithmetic unit 54416 and the full adder 54410. Given to. The full adder 54404 calculates Xa1c1, the full adder 54405 calculates Xb1a1, the full adder 54406 calculates a value Xb2a1 obtained by subtracting the pixel value Xa1 from the pixel value Xb2, and provides data indicating the calculation result. This is given to the concatenation calculator 54416. The output data Xa1c1 also represents the magnitude relationship between the pixel value Xa1 + the pixel value Xb1−the pixel value Xc1 and the pixel value Xb1. This is because pixel value Xa1 + pixel value Xb1−pixel value Xc1−pixel value Xb1 = pixel value Xa1−pixel value Xc1.

  The full adder 54403 calculates and outputs a value Xb1c1b2 obtained by subtracting the pixel value Xc1 and the pixel value Xb2 from the pixel value Xb1. The output data Xb1c1b2 of the full adder 54403 is supplied to the full adder 54407 after adjusting the output timing by the register 54414. The full adder 54407 adds the pixel value Xa1 to the output data Xb1c1b2 of the full adder 54403 given through the register 54414, and concatenates the addition result Xa1b1c1b2 = pixel value Xa1 + pixel value Xb1−pixel value Xc1−pixel value Xb2. This is given to the arithmetic unit 54416. The output data Xa1b1c1b2 of the full adder 54407 represents the magnitude relationship between the pixel value Xa1 + the pixel value Xb1−the pixel value Xc1 and the pixel value Xb2.

  The full adder 54409 gives the selector 54417 the sum Xa1b1c1 = pixel value Xa1 + pixel value Xb1−pixel value Xc1 of the output data Xb1c1 and the pixel value Xa1 given from the register 54512. The full adder 54410 provides the selector 54417 with the sum Xa1b2b1 = pixel value Xa1 + pixel value Xb2−pixel value Xb1 of the output data Xb2b1 and the pixel value Xa1 given from the register 54413. The full adder 54408 calculates a value Xb2c1 = pixel value Xb2−pixel value Xc1 obtained by subtracting the pixel value Xc1 from the pixel value Xb2, and supplies the calculated value to the register 54415. The output data Xb2c1 of the full adder 54408 is supplied to the full adder 54411 after adjusting the output timing by the register 54415. The full adder 54411 calculates the sum Xa1b2c1 = pixel value Xa1 + pixel value Xb2−pixel value Xc1 of the output data Xb2c1 and the pixel value Xa1, and supplies the result to the selector 54417.

  The concatenation calculator 54416 generates a control signal S2 having a value corresponding to the combination of the sign bit values of the output data Xb1c1, Xb2b1, Xa1c1, Xb1a1, Xb2a1 and Xa1b1c1b2 according to Table 2 and Table 3 above, and selector 54417 To give. For example, the concatenation calculator 54416 outputs the pixel value Xb1 as the pixel value Xd1 and the pixel value Xd2 when the value of each sign bit of the output data Xb1c1, Xa1c1, Xb1a1, Xb2a1, and Xb2b1 is zero. For example, the selector 54417 is supplied with a control signal S2 having a value for instructing to output the value Xb2. In addition to the control signal S2, the selector 54417 is supplied with output data Xa1b1c1, Xa1b2b1, and Xa1b2c1, and pixel values Xa1, pixel values Xb1, and pixel values Xb2 as input data. The selector 54417 outputs the pixel value Xd1 and the pixel value Xd2 in accordance with the value of the control signal S2 given from the concatenation calculator 54416.

  As described above, according to the second inverse predictive encoding unit 544, the inverse predictive encoding of the pixel Mx1 and the pixel Mx2 is collectively performed using the pixel value Xa1, the pixel value Xc1, the pixel value Xb1, and the pixel value Xb2. Done. In addition, in each of the above processes, the first calculation that can be performed regardless of the decoding result of the pixel Xa1 among the calculations required for the inverse predictive encoding of the pixel Mx1 and the pixel Mx2 is performed with the clock immediately before the calculation result. By holding this, the number of prediction value calculation processes and addition processes that can be executed per clock can be increased, and the number of pixels that can be decoded at one clock can be increased.

Although one embodiment of the present invention has been described above, the following modifications may of course be added to this embodiment.
(1) In the above-described embodiment, a case has been described in which inverse prediction encoding of two consecutive pixels to be processed with a prediction error of zero is performed in a batch. However, if the view is changed, the prediction error is zero. The inverse prediction encoding of the right one of the two consecutive processing target pixels is performed by calculating the pixel value of the pixel located immediately above each processing target pixel, the pixel adjacent to the left and upper left of the left processing target pixel. Based on the pixel value, this can be performed independently of the inverse prediction encoding of the left processing target pixel, and as is apparent from reference to Tables 2 and 3, the reverse prediction of the right processing target pixel is performed. This means that the pixel value of the pixel to be processed on the left side is inevitably obtained during the encoding process.

  And this means that if all the prediction errors of N (N is an integer of 2 or more) processing target pixels arranged in the horizontal direction are all zero, the pixel of each pixel located immediately above each processing target pixel The pixel value of the rightmost processing target pixel can be calculated from the value, the pixel value of each pixel located on the left and upper left of those N processing target pixels, and in the calculation process, The pixel values of the N-1 processing target pixels are inevitably obtained, ”and can be generalized. More specifically, when the prediction errors of N (N is an integer of 2 or more) processing target pixels arranged in the horizontal direction are all zero, the pixel value of each pixel located immediately above each processing target pixel , The pixel value of each pixel located at the upper left and the left side of the leftmost processing target pixel among these N pixels, and the pixel value of each of the N−1 processing target pixels calculated from these pixel values The pixel value of the rightmost of the N processing target pixels is calculated by determining the magnitude relationship between the values that are candidates for (for example, pixel value Xa1 + pixel value Xb1−pixel value Xc1 in Tables 2 and 3) In the calculation process, the pixel values of other N-1 processing target pixels are inevitably determined. The reason is as follows.

First, it is clear from the description of the second inverse predictive encoding unit 544 that the above generalization holds when N = 2.
Next, consider the case of N = k + 1 assuming that the above generalization holds when N = k. Specifically, when the prediction errors Diff1 to Diffk + 1 are zero for each of the pixels Mx1 to Mxk + 1 illustrated in FIG. 3A, based on the pixel values of the pixels Ma1, Mc1, and Mb1 to Mbk + 1. Consider whether the pixel value of the pixel Mxk + 1 can be obtained. In FIG. 3A, the pixel value of the pixel Mxk + 1 can be obtained from the magnitude relationship among the pixel values of the pixel Mxk, the pixel Mbk, and the pixel Mbk + 1. On the other hand, the pixel value of the pixel Mxk is the pixel value Xa1, the pixel value Xc1, the pixel values Xb1 to Xbk, and the pixel value candidates of the pixels Mx1 to Mxk−1 calculated from these pixel values based on the above assumption. It can be obtained by determining the magnitude relationship between the values. The pixel value of the pixel Mxk determined in this way is naturally included in the pixel value candidate of the pixel Mxk calculated from the pixel value Xa1, the pixel value Xc1, and the pixel values Xb1 to Xbk. Therefore, the pixel value Xa1, the pixel value Xc1, the pixel values Xb1 to Xbk, the pixel value candidates of the pixels Mx1 to Mxk−1 calculated from these pixel values, and the pixel value candidates of the pixel Mxk And the pixel value Xbk + 1 are determined to determine the pixel value of the pixel Mxk + 1 and the pixel value of the pixel Mxk. From the above assumption, if the pixel value of the pixel Mxk is obtained, the pixel values of the pixels Mx1 to Mxk−1 are also inevitably obtained. Thus, assuming that the above generalization holds when N = k, the above generalization also holds when N = k + 1. Therefore, the above generalization for an arbitrary integer N of 2 or more is performed by so-called mathematical induction. Chemicalization holds. Although it can be generalized as described above, when the value of N increases, the circuit for performing the inverse predictive encoding of N processing target pixels arranged in the horizontal direction in which each prediction error is zero. The circuit scale becomes large. Therefore, it is only necessary to appropriately determine how many of the plurality of processing target pixels arranged in the horizontal direction in which the prediction error is zero are to be subjected to inverse predictive coding in relation to the circuit scale.

  For example, in FIG. 3A, when Diff1 = Diff2 = Diff3 = 0, for the pixel value Xd3 of the pixel Mx3, the pixel value Xa1, the pixel value Xc1, the pixel value Xb1, the pixel value Xb2, and the pixel value Xb3 are set. The calculation shown in the following formulas (1) to (18) is performed, and it can be obtained in the manner shown in FIG. 6 based on the calculation results. As is apparent from FIG. 6, α1 is a value that becomes a candidate pixel value of the pixel Mx1 or Mx2, and α2 and α5 are values that become candidate pixel values of the pixel Mx2. Further, as shown in FIG. 6, the pixel value Xd1 and the pixel value Xd2 are inevitably obtained in the process of calculating the pixel value Xd3. Note that the magnitude relationship between α1 and the pixel value Xb1 in FIG. 6 may be determined based on the value of the sign bit of Xa1c1. This is because α1−pixel value xb1 is equal to Xa1c1 when calculated. Similarly, the magnitude relationship between α2 and the pixel value Xb1 may be determined based on the value of the sign bit of Xa1b1, and the size relationship between α5 and the pixel value Xb2 may be determined based on the value of the sign bit of Xa1c1. . In FIG. 6, the state of the pixel value Xc1 (the pixel located at the upper left with respect to the processing target pixel) is MIN when the pixel value Xc1 <the pixel value Xb1 and the pixel value Xc1 <the pixel value Xa1. The state where the pixel value Xc1 is MAX means the case where the pixel value Xc1> the pixel value Xb1 and the pixel value Xc1> the pixel value Xa1, and the case where the state of the pixel value Xc1 is neither of them. Similarly, regarding the pixel value Xb1 and the pixel value Xb2, whether or not the pixel value Xb1 and the pixel value Xb2 are the maximum or the minimum with respect to other peripheral pixels when they are located in the upper left with respect to the processing target pixel. Mean.

Xb1c1 = pixel value Xb1−pixel value Xc1 (1)
Xa1c1 = pixel value Xa1−pixel value Xc1 (2)
Xb1a1 = pixel value Xb1−pixel value Xa1 (3)
Xb2b1 = pixel value Xb2-pixel value Xb1 (4)
Xb2a1 = pixel value Xb2-pixel value Xa1 (5)
Xb3b2 = pixel value Xb3-pixel value Xb2 (6)
Xb3a1 = pixel value Xb3-pixel value Xa1 (7)
α1 = pixel value Xa1 + pixel value Xb1−pixel value Xc1 (8)
α2 = pixel value Xa1 + pixel value Xb2−pixel value Xb1 (9)
α3 = pixel value Xa1 + pixel value Xb3−pixel value Xb2 (10)
α4 = pixel value Xa1−pixel value Xb1 + pixel value Xb2 (11)
α5 = pixel value Xa1−pixel value Xc1 + pixel value Xb2 (12)
α6 = pixel value Xa1 + pixel value Xb1−pixel value Xc1−pixel value Xb3−pixel value Xb2 (13)
α7 = pixel value Xa1−pixel value Xc1 + pixel value Xb3 (14)
α1Xb2 = pixel value Xa1 + pixel value Xb1−pixel value Xc1−pixel value Xb2 (15)
α1Xb3 = pixel value Xa1 + pixel value Xb1−pixel value Xc1−pixel value Xb3 (16)
α2Xb3 = pixel value Xa1 + pixel value Xb2−pixel value Xb1−pixel value Xb3 (17)
α5Xb3 = pixel value Xa1−pixel value Xc1 + pixel value Xb2−pixel value Xb3 (18)

(2) In the above-described embodiment, when the prediction errors of two pixels arranged in the horizontal direction are both zero, inverse prediction encoding of the two pixels is performed collectively. The second inverse prediction encoding unit 544 performs inverse prediction encoding on the right side of the pixels by the second inverse prediction encoding unit 544, and in parallel with this, the first inverse prediction encoding unit 542 performs inverse prediction encoding of the left side pixel. Of course it is good. That is, when the prediction errors of N pixels (N is an integer of 2 or more) arranged in the horizontal direction are all zero, the pixel value of each pixel positioned directly above each pixel to be processed, N of them The second inverse predictive coding unit 5442 performs only the process of calculating the pixel value of the rightmost processing target pixel from the pixel values of the pixels located on the upper left and the left side of the leftmost processing target pixel, and the other Of course, the N-1 processing target pixels may be decoded by another method (for example, the first inverse predictive encoding unit 542 is driven N-1 times).

(3) FIG. 7 (A) to FIG. 7 (N) are diagrams showing the results of inverse predictive coding for three consecutive pixels with a prediction error of zero. Here, it should be noted that when the pixel value of the pixel located at the left end among the three pixels to be subjected to inverse predictive encoding is the pixel value of the pixel located immediately above the pixel, each subsequent process The pixel value of the target pixel is also a point that is the pixel value of the pixel located directly above each (see FIG. 7A). This is because when the pixel value of the pixel located at the left end becomes the pixel value of the pixel located directly above, the pixel value of the pixel on the left is equal to the pixel value of the pixel on the upper left, This is because only the situation of (Case 1) or (Case 3) described above occurs, and in any case, the pixel value of the pixel is the pixel value of the pixel immediately above it.

  In other words, the prediction error for each of a plurality of consecutive processing target pixels is zero, and the pixel value of any of the processing target pixels is equal to the pixel value of the pixel located directly above it. In this case, since only the situation of (Case 1) or (Case 3) occurs with respect to the processing target pixel on the right side of that, the pixel values of the subsequent processing target pixels are located immediately above each. It becomes equal to the pixel value of the pixel to be processed. Paying attention to this point, the prediction error for each of a plurality of continuous processing target pixels is zero, and the pixel value of any of the processing target pixels whose pixel value is directly above the pixel value In the case where they are equal, a circuit for outputting the pixel value of the pixel located immediately above each of the subsequent pixels may be provided in the inverse predictive coding unit 3054. In this way, the number of pixels that can be decoded during one clock can be further increased.

(4) In the above-described embodiment, the present invention is applied to the inverse predictive encoding unit 3054 of the pattern data decoder 305 that decodes image data compressed and encoded by a compression encoding algorithm that uses both predictive encoding and variable length encoding. Applied. However, the variable length decoding unit 3052 is not an essential requirement of the present invention. Of course, the invention may be applied. Of course, the present invention may be applied to a predictive coding apparatus in charge of predictive coding when compression coding is applied to image data.

(5) In the above-described embodiment, the inverse predictive encoding unit 3054 is configured by an electronic circuit (hardware) such as a full adder or a register. However, the pattern data decoder 305 is configured by a DSP, and this DSP is subjected to variable length decoding. A program (for example, firmware of an image processing LSI) that functions as the conversion unit 3052 and the inverse prediction encoding unit 3054 may be provided, and such a program may be stored on a computer-readable recording medium such as a CD-ROM. It may be distributed by writing or by downloading via a telecommunication line such as the Internet.

(6) In the above-described embodiment, the first calculation is performed by one clock preceding the second calculation in the calculation in the second inverse prediction encoding unit 544, but the second inverse prediction encoding unit 544 is executed. It is not always essential to perform the first calculation prior to the second calculation. In addition, in the calculation in the first inverse predictive encoding unit 542, when the first calculation is executed prior to the second calculation, it may of course be preceded by a plurality of clocks such as two clocks. In the above-described embodiment, entropy coding including zero-run length coding is performed as variable-length coding. This is for improving the compression rate, and does not necessarily require zero-run length coding. Absent.

  DESCRIPTION OF SYMBOLS 300 ... Image processing LSI, 301 ... CPU I / F, 302 ... Memory | storage part, 303 ... Control part, 304 ... Pattern memory I / F, 305 ... Pattern data decoder, 3052 ... Variable length decoding part, 3054 ... Inverse prediction encoding 542 ... first inverse prediction encoding unit, 542 ... second inverse prediction encoding unit, 306 ... sprite rendering processor, 307A, 307B ... line buffer, 308 ... display controller, 309 ... image data controller, 310 ... monitor I / F, 401 ... sprite pattern memory, 402 ... CPU, 403 ... monitor.

Claims (2)

When each of a plurality of pixels constituting the image is a target pixel, the predicted value of the pixel value of the target pixel calculated from the magnitude relationship of the pixel values of a plurality of peripheral pixels located in the vicinity of the target pixel and the target In a decoding device that obtains predictive encoded data obtained by arranging prediction errors representing a difference from an actual pixel value of a pixel in order of arrangement of the pixels, and restores image data representing the image from the predictive encoded data,
Predicted value calculation processing for calculating each pixel whose prediction error is represented by the predicted encoded data as a processing target pixel, and calculating a predicted value of the pixel value from the pixel values of the plurality of surrounding pixels, and the processing target And an addition process for restoring a pixel value by adding a prediction error indicated by the predictive encoded data to the prediction value, and a pixel to be processed among the plurality of neighboring pixels. A first calculation that refers only to pixel values of pixels that are not aligned in the horizontal scanning line direction is executed prior to the other second calculations, and the first calculation is performed until the second calculation is executed. A decoding apparatus comprising: an inverse predictive coding unit that holds a calculation result of a calculation. When each of a plurality of pixels constituting the image is a target pixel, the predicted value of the pixel value of the target pixel calculated from the magnitude relationship of the pixel values of a plurality of peripheral pixels located in the vicinity of the target pixel and the target Compression encoding obtained by subjecting prediction encoded data obtained by arranging prediction errors representing a difference between actual pixel values of pixels in the order of pixel arrangement to variable length encoding processing for variable length encoding of the prediction errors. In a decoding device that acquires data and restores image data representing the image from the compression-encoded data,
A variable length decoding unit that performs a variable length decoding process, which is an inverse operation of the variable length encoding process, on the compressed encoded data, and restores the predicted encoded data;
Each pixel whose prediction error is represented by the predictive encoded data obtained by the variable length decoding unit is a processing target pixel, and the predicted value of the pixel value is calculated from the magnitude relationship of the pixel values of the plurality of surrounding pixels. Inverse prediction for executing prediction value calculation processing and addition processing for adding a prediction error indicated by prediction encoded data obtained by the variable length decoding unit to the prediction value for the pixel to be processed to restore the pixel value A first calculation that refers to only the pixel values of the plurality of peripheral pixels that are not arranged in the horizontal scanning line direction among the plurality of peripheral pixels precedes the other second calculations. And an inverse predictive encoding unit that holds the calculation result of the first calculation until execution of the second calculation,
A decoding device comprising:

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