JPH0795693B2 - Encoding / decoding device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to an encoding / decoding device,
In particular, it relates to a coding / decoding device for image information and the like.

[0002]

2. Description of the Related Art In coding a Markov information source, a target symbol to be coded is predicted from a reference symbol which has already been coded for an output symbol sequence of the information source, and the prediction error signal is used as a reference symbol pattern. Thus, each prediction error signal is classified into several groups according to the predictive predictive value, and coding is performed using a code suitable for each. Here, the generation of this prediction error signal is called prediction conversion, the classification into groups is called integration, and the group identifier is called order. Further, the prediction error signal to be encoded will be called a prediction error symbol.

This predictive conversion and order selection method is to cope with local changes in the statistical properties of the information source.
A technique for performing adaptive processing is disclosed in Japanese Patent Application No. 1-127134. As for the coding method of the prediction error symbol, the subtraction type arithmetic coding method is described in IBM Research and Development Information 19
Vol. 32, No. 6, November 1988 (IBM Journal
l ofResearch and Development
nt, Vol. 32, No. 6, Nov. 1988) "Overview of the basic principle of a binary arithmetic encoder for Q-coder".
(An overview of the basic
princicle of the Q-Coder
adaptive-binary arith-met
ic coder) and (JP-A-2-202267). These are a kind of number line display coding method that maps a symbol sequence between 0.0 and 1.0 on the number line and encodes the coordinates as a code word. When splitting
It is performed only by addition and subtraction.

The process of predictive conversion, integration and encoding according to the conventional technique will be described below with reference to FIG. For simplicity, the information source is a binary image signal and the reference symbol is shown in FIG.
12 pixels, and the integrated number is 16.

In FIG. 25, reference numeral 1 is a reference symbol generator which selectively outputs a reference symbol from a sequence of information source symbols 101, and 2 is a reference symbol pattern 102 which is an output thereof, and outputs the degree 103 and the predicted value 104 of the target symbol. Order / predicted value memory, 3 is a predictive converter that creates a prediction error symbol 105 based on the predicted value 104, and 4 is an order 10
An area width table for outputting the area width 106 of the arithmetic code based on 3, 5 is an arithmetic encoder, and 6 is an order / predicted value control circuit for controlling reading and updating of the order / predicted value memory 2. Here, since the number of reference symbols is set to 12, 212 kinds of order / predicted value tables (contents of the memory 2) are required as shown in FIG. Regarding the order value, the integration is made into 16 groups, and therefore this is identified. Here, the higher the predictive predictive ratio, the higher the order.

Next, the operation will be described with reference to FIG.
The symbol 101 (image signal) generated from the information source is stored in the reference symbol generator 1 and its sequence is stored.
The signal of 12 pixels shown in 6 is selected and output as the reference symbol pattern 102. Based on this, the order / predicted value memory 2 outputs the predicted value 104 and the order 103 of the target symbol from the table contents shown in FIG.
The information is converted and output as the area width 106 in the area table 4 shown in FIG.

On the other hand, the generated symbol 101 is the prediction converter 3
The prediction error symbol 105 is created by exclusive ORing with the prediction value 104. Since this prediction error symbol is a binary image signal to be encoded, it is 0 when the prediction matches.
(MPS: More Probeable Symbol
l), 1 if there is no match (LPS: Less Prob
Able Symbol).

In the arithmetic encoder 5, the prediction error symbol 105 is mapped on a number line based on the region width 106 signal, and coding is executed. That is, in the prediction error symbol sequence, the i-th symbol is ai, and the LP at the i-th time point is
When the mapping range (allocation area) of S is S, the mapping range (effective area) Ai of the symbol sequence at the i-th time point and its lower bound coordinate Ci are such that when the symbol ai is MPS, the MPS area is below the effective area. If it is taken to the side, Ai = Ai-1-S Ci = Ci-1 When the symbol ai is LPS, Ai = S Ci = Ci-1 + (Ai-1-S).

Here, when the effective area Ai becomes 1/2 or less, it is multiplied by a power of 2 in order to improve the calculation accuracy. At this time, overflow of coordinates Ci (portion above the decimal point)
Minutes are output as a code bit sequence. Hereinafter, this exponentiation process is called normalization. Ai update value = Ai * 2m (1/2 <Ai update value ≦ 1) Ci update value = Ci * 2m

In the arithmetic code, it is known that high efficiency coding extremely close to the information source entropy can be performed by setting S to the appearance probability (= prediction error probability) of LPS. Therefore, arithmetic coding can be performed by the above processing by selecting an S value suitable for the predictive predictive value corresponding to the order. FIG. 28 is an example of a correspondence table of the degree and the area width S. The values in the table are those obtained by multiplying the numerical values in the above formula by 2 @ 16.

Next, the adaptive processing of prediction and integration will be described. The order / predicted value control circuit 6 counts the number of consecutive MPSs and LPSs from the output symbol sequence of the predictive converter 3, and, for example, when k MPSs are detected and one LPS is detected, the procedure is as follows. The contents of the order / predicted value table memory 2 are rewritten. The values of k and l are preset in the order / predicted value control circuit 6 according to each order.

When one LPS is detected, the order / predicted value table memory 2 subtracts 1 from the order value corresponding to the reference symbol pattern at that time. This is an operation for adapting the order / predicted value to the information source currently being coded by lowering the order indicating the accuracy of the prediction because the prediction in the reference symbol state is wrong. Is. When the order reaches the lowest order and the order cannot be reduced any more, the predicted value is inverted. By this operation, the predicted value with extremely bad hit rate is rewritten.

When k MPSs are detected, the order / predicted value table memory 2 adds 1 to the order value corresponding to the reference symbol pattern at that time. This is because the prediction in the reference symbol state is correct, so by increasing the order indicating the accuracy of the prediction, the order / predicted value is adapted to the information source currently being encoded. It is an action. If the degree has already reached the highest degree, no addition is performed. When the prediction is extremely accurate by this operation, the S value is reduced by increasing the order, and the code amount output from the arithmetic encoder 5 can be suppressed.

By the above operation, the order / predicted value control circuit 6
Can rewrite the order / predicted value table according to the property of the information source, and realize the arithmetic coding with high coding efficiency.

[0015]

However, in this conventional device, the order / prediction value memory 2 is a general-purpose RAM because of its capacity (212 × 5 bits in the above embodiment).
I have no choice but to use. On the other hand, as is apparent from the above description, in the arithmetic coding based on the Markov model, the reference symbol pattern is created for each symbol, the order / predicted value memory 2 is searched, and the area of the number line is calculated. A4 size original document is 8 pixels / mm horizontally and 7.7 l vertically
In the case of encoding with a resolution of ine / mm, it is about 1.3 seconds, which is significantly higher in processing speed than an encoding / decoding device based on another encoding method such as MMR encoding.

The present invention has been made in order to solve the above problems, and a code capable of significantly increasing the processing speed by making the order / prediction value memory for a specific reference symbol pattern accessible at high speed. The purpose is to obtain an encryption device and a decoding device.

Another invention has been made in order to solve the above-mentioned problems, and the search of the order / prediction value table for the next symbol and the area calculation of the number line for the symbol are performed in parallel. By doing so, it is an object to obtain an encoding device and a decoding device that can significantly speed up the processing.

Further, another invention has been made to solve the above-mentioned problems, and when a specific reference symbol pattern is continuous, it is possible to significantly calculate the area of the number line by batch processing. An object of the present invention is to obtain an encoding device and a decoding device capable of various processing speed increases.

[0019]

According to a first aspect of the present invention, there is provided an encoding device, which uses an identifier based on a prediction value of a symbol to be coded and a prediction matching rate, corresponding to a pattern of reference symbols. A memory that stores a certain order, a detector that detects that the pattern of the reference symbol is a specific pattern, a register that stores a predicted value and the order for the specific pattern, and a detector output based on the detector output. A selector for selecting the memory and the register output, an arithmetic coding means for coding the encoding target symbol based on the prediction value / order information output from this selector, and the above-mentioned encoding target symbol for predictive matching. A determination means for determining whether or not there is a determination value; and an order / prediction value control circuit for rewriting the prediction value and the order for the reference symbol pattern based on the determination result. It is.

A decoding device according to the inventions of claims 3 and 4 stores a memory for storing a predicted value of the decoding target symbol and an order which is an identifier based on a predicted matching rate, corresponding to a pattern of a reference symbol. A detector that detects that the pattern of the reference symbol is a specific pattern, a register that stores the predicted value and order for the specific pattern, and the memory and the register output based on the detector output. A selector, an arithmetic decoding means for decoding the code bit sequence based on the predicted value / order information output from the selector, and a judging means for judging whether or not the decoding target symbols are predictively matched. And an order / predicted value control circuit that rewrites the predicted value and the order for the reference symbol pattern based on the determination result.

According to a fifth aspect of the present invention, there is provided an encoding device, which stores a predicted value of the symbol to be coded and an order which is an identifier based on a predicted matching rate in correspondence with a pattern of a reference symbol, and the memory. Order / prediction value register for storing the predicted value and order of the target symbol to be encoded read from, determination means for determining whether or not the target symbol to be encoded matches prediction, and based on the determination result Order / predicted value control circuit for rewriting the predicted value and order of the memory in the reference symbol pattern, and the order / predicted value according to the comparison result of the reference symbol pattern for the symbol to be coded and the reference symbol pattern for the immediately preceding symbol. The detector that updates the contents of the register and the predicted value / order information stored in the above order / predicted value register Those having a arithmetic coding means for coding the coding target symbol and.

According to a sixth aspect of the present invention, there is provided a coding device, which stores a predicted value of the coding target symbol and an order which is an identifier based on a predicted matching rate in correspondence with a pattern of a reference symbol, and the code. Determination means for determining whether or not the symbol to be coded is predictively matched, an order / predicted value control circuit for rewriting the predicted value and order of the memory in the reference symbol pattern based on the result of the determination, and immediately preceding encoding According to the result of comparison between the register for storing the predicted value and the order after rewriting for the target symbol and the reference symbol pattern for the above-mentioned symbol to be coded and the reference symbol pattern for the immediately preceding symbol, the order / predicted value from the memory or the immediately preceding Select one of the registers that store the predicted value and order for the symbol to be coded. A selector for, on the basis of the selector output, is obtained by a arithmetic coding means for coding the coding target symbol.

Decoding devices according to the inventions of claim 7 and claim 8 store the predicted value of the decoding target symbol and the order which is an identifier based on the predicted matching rate, corresponding to the pattern of the reference symbol, A memory for outputting in parallel predicted values and orders corresponding to a plurality of reference symbol patterns, and a selector for selectively outputting a set of predicted values and orders among memory outputs for a plurality of reference symbol patterns. Arithmetic decoding means for decoding the coded bit sequence based on the order / prediction value, a register for storing the output of the memory, and a judgment means for judging whether or not the decoding target symbols are predictively matched. And an order / prediction value control circuit that rewrites the prediction value and the order for the reference symbol pattern based on the determination result, and the reference for the decoding target symbol. According to the comparison result of the reference symbol pattern for the symbol pattern and the previous symbol, in which a detector to update the contents of the degree and predicted value register.

Decoding devices according to the inventions of claims 7 and 9 store the predicted value of the decoding target symbol and the order which is an identifier based on the predicted matching rate, corresponding to the pattern of the reference symbol, A memory for outputting in parallel predicted values and orders corresponding to a plurality of reference symbol patterns, and a selector for selectively outputting a set of predicted values and orders among memory outputs for a plurality of reference symbol patterns. Arithmetic decoding means for decoding the coded bit sequence based on the degree / predicted value, determination means for determining whether or not the decoding target symbols are predictively matched, and the reference based on the determination result An order / prediction value control circuit that rewrites a prediction value and an order for a symbol pattern, and a prediction value and an order after rewriting for the immediately preceding decoding target symbol are stored. A detector, a detector that detects whether or not the reference symbol pattern for the symbol to be decoded matches the reference symbol pattern for the immediately preceding symbol, and the order / predicted value selected by the above selector based on the detector output. Alternatively, it is provided with a second selector that selects either the order / predicted value from the register that stores the predicted value and the order for the immediately preceding decoding target symbol.

The encoding apparatus according to the inventions of claims 10 and 11 stores the predicted value of the symbol to be coded and the order which is an identifier based on the predictive matching rate, corresponding to the pattern of the reference symbol. Based on the output of the detector, a memory, a detector for detecting that the patterns of reference symbols for a plurality of continuous encoding target symbols are all specific patterns, and all the encoding target symbols predictively match each other. , The encoding target symbols are encoded one symbol at a time according to the prediction value / order information stored in the memory, or the plurality of encoding target symbols are collectively encoded to operate. Arithmetic encoding means, determination means for determining whether or not the encoding target symbols predictively match, and the reference symbol pattern based on the determination result. Those having a degree and predicted value controller for rewriting the predicted value and the order of the memory in the emissions.

A decoding device according to the invention of claim 12 and claim 13 includes a memory for storing a predicted value of a symbol to be decoded and an order which is an identifier based on a predicted matching rate, corresponding to a pattern of reference symbols. A detector for detecting that all the reference symbol patterns for the plurality of decoding target symbols are specific patterns when it is assumed that a plurality of consecutive decoding target symbols are predictively matched; Based on the output, a process of encoding one symbol for each symbol to be encoded according to the prediction value / order information stored in the memory or collectively decoding the plurality of symbols to be decoded An arithmetic decoding unit that operates by switching, a determination unit that determines whether or not the decoding target symbol predictively matches, and the reference based on the determination result. Those having a degree and predicted value controller for rewriting the predicted value and degree for emissions Bol pattern.

[0027]

According to the inventions of claims 1 and 2, when the pattern of the reference symbol is in a specific pattern, the register output is selected for reading and updating the order / predicted value, and other patterns Then, the coding speed is improved by selecting and using the output signal from the memory.

According to the inventions of claims 3 and 4,
When the reference symbol pattern is in a specific pattern, the register output is selected for reading and updating the order / predicted value, and for other patterns, the output signal from the memory is selected and used for decoding speed. Is improved.

According to the fifth aspect of the present invention, the predicted value and the order used in the encoding process are stored in the order / predicted value register according to the result of comparison between the reference symbol pattern for the symbol to be coded and the reference symbol for the immediately preceding symbol. After updating the content, the encoding speed is improved by encoding the encoding target symbol based on the updated prediction value / order information.

According to the sixth aspect of the present invention, the prediction value and the order used in the encoding process depend on whether or not the reference symbol pattern for the symbol to be encoded and the reference symbol for the immediately preceding symbol match. The coding speed is improved by selecting and using the predicted value after the rewriting process and the order or the output signal from the memory for the symbol to be coded.

According to the seventh and eighth aspects of the present invention, whether the pattern of the reference symbol for the symbol to be decoded and the reference symbol for the immediately preceding symbol match as the predicted value and order used in the decoding process. Accordingly, the decoding speed is improved by selecting and using the predicted value and the order after the rewriting process or the output signal from the memory for the immediately preceding symbol to be decoded.

According to the inventions of claims 7 and 9, whether the pattern of the reference symbol for the symbol to be decoded and the reference symbol for the immediately preceding symbol match as the predicted value and order used in the decoding process. Depending on whether or not the order / prediction value selected by the selector or the rewrite processing prediction value and the order or the output signal from the register for storing the order / prediction value for the immediately preceding decoding target symbol are selected and used, respectively. This improves the decoding speed.

According to the tenth and eleventh aspects of the invention, when the reference symbol pattern for a plurality of consecutive symbols to be encoded is a specific pattern,
In the arithmetic encoder, the encoding speed is improved by collectively performing the arithmetic operation on a plurality of symbols.

According to the twelfth and thirteenth aspects of the invention, when the reference symbol pattern for a plurality of consecutive decoding target symbols is a specific pattern,
The decoding speed is improved by collectively performing arithmetic operations on a plurality of symbols in the arithmetic encoder.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first invention will be described below with reference to illustrated embodiments. FIG. 1 shows an encoding apparatus according to an embodiment of the present invention. In FIG. 1, the difference from the conventional encoding apparatus of FIG. 25 is that reference symbol patterns 102 to 12 of FIG.
A detector 7 for detecting whether all the pixels are 0 (white pixels),
A register 8 that stores an order and a predicted value when all 12 pixels are 0, and a memory 2 depending on whether all 12 pixels are 0
And that the selector 9 for switching the output of the register 8 and the update signal for writing to these is added.

FIG. 2 is a block diagram showing the internal structure of the arithmetic encoder 5. In the figure, 5a is an A register for storing the effective area Ai on the number line, and 5b is an MPS area width 11
7 is a subtracter, 5c is a C register for storing the lower bound coordinate 118, and 5d is a C register value for LPS 11
The adder 5e for calculating 9 temporarily stores the carry output 120 which is the overflow (shift-out) signal of the C register, carries out a carry when updating the C register 5c, and the stored contents of the sign bit are continuous. When the number of eight "1" s is reached, a process of inserting "0" from the bottom of the least significant bit to suppress the effect of the carry process after that to the insertion "0" or less (hereinafter referred to as bit stuffing process). A code register 5f for performing the above is a timing control circuit for controlling the movement of the arithmetic encoder 5.

Next, the operation of this embodiment will be described.
3 and 4 are timing charts showing an operation example of this embodiment. For ease of explanation, first, the case where the reference symbol patterns 102 shown in FIG. 3 are not all "0" and the case where they are all "0" will be described separately.

First, when all the reference symbol patterns 102 are not "0", when the prediction target symbol is input to the present coding apparatus as the information source symbol 101, it is already processed in the reference symbol generator 1. The signal of the reference pixel of 12 pixels shown in FIG.
It is determined that all are not “0”. The selector 9 receives this and outputs the output signal in the reference symbol pattern read from the order / prediction value memory 2 to the region width table 4 and the prediction converter 3. Here, in this embodiment, the reading process of the order / predicted value memory 2 is 10M.
Two HZ system clock cycles are set to 200 nsec.

The order signal 112 is converted by the area width table 4 into the area width signal 106 shown in FIG.
Reference numeral 13 is a prediction converter 3 which performs an exclusive OR operation on the information source symbol 101 to generate a prediction error symbol 105. After that, the calculation of the effective area Ai and the lower bound coordinate Ci and the update of the order / predicted value are performed as follows. (1) When normalization and order / prediction value updating is not performed (# 1 in FIG. 3)
It is executed in a cycle. (2) If there is normalization and there is no update of order / prediction value (# 2 in FIG. 3), the area / coordinate calculation processing other than normalization is executed in one cycle of the system clock, and normalization is executed in m clocks. (3) When there is no normalization and there is an update of order / predicted value (# 3 in FIG. 3)
After the cycle, the contents of the order / predicted value memory 2 are updated. The memory is updated in two system clock cycles. (4) When there is normalization and updating of order / predicted value (Fig. 3
# 4) After the area / coordinate calculation processing excluding the normalization is performed in one cycle of the system clock, the normalization is performed in m clocks and the order / predicted value memory 2 is updated in parallel. At this time, the processing of the next symbol is performed after both the normalization and the update of the memory 2 are completed.

Here, the control of the area calculation and the coordinate calculation including the determination of LPS and MPS is performed by the prediction error symbol 105.
Further, based on the MSB signal of the A register output 116, the timing control circuit 5f of the arithmetic encoder 5 performs the update control of the order / predicted value memory 2 by the order / predicted value control circuit 6.

In the sign register 5e, the carry process is performed in parallel with the above-mentioned (excluding normalization) area / coordinate calculation. At the time of normalization, the carry from the 8th bit is output as code 107 along with the shift of the internal register. At this time, when all the bits of the 8-bit internal register are "1", the bit stuff signal 122 is sent to the timing control circuit 5f, the normalized clock 121 is temporarily stopped, and the system clock 1 cycle is used to perform the internal operation. 1-bit shift of the register (LSB shift-in signal is set to "0") is performed.

All reference symbol patterns 102 are "0".
In this case, the selector 9 selects the output of the order / predicted value register 8 instead of the output of the order / predicted value memory 2 as the order and predicted value signal. Since only the delay (10 nsec or less) in the selector 9 needs to be taken into consideration in this process, a special cycle for reading the order / predicted value becomes unnecessary. Further, the update of the order / predicted value is possible in one system clock cycle. Therefore, the processing when the reference symbol patterns 102 are all "0" is as shown in FIG.

In the above, the case where all of the reference symbol patterns 102 are "0" or other cases are explained separately, but in the actual image signal coding, these occur in a mixed manner. Therefore, the operation timing is a combination of the cases of FIGS. 3 and 4.

As is apparent from the above description, in the encoding processing time T in this embodiment, the number of symbols other than "0" for all reference symbol patterns is Na, the number of symbols for all "0" is Nb, and the code is If the number of bits is Nc, T = 200 * Na + 100 * (Na + Nb) + 100 *
It becomes Nc + 100 * α (nsec). Here, α is the number of clocks required for addition (required for updating when there is no normalization processing) when the update processing is not completed at the end of the normalization processing when updating the order / predicted value.

Therefore, the standard resolution is horizontal 8 pixels / m.
Assuming that the ratio of all reference symbol patterns to be “0” is 2/3 and the compression ratio is 30 for an A4 size document of m, vertical 7.7 lines / mm, Na = 1728 * 2376 * (1/3) Nb = 1728 * 2736 * (2/3) Nc = 1728 * 2736 * (1/30), and the encoding processing time T becomes about 0.7 seconds. Here, since the update of the order / predicted value is about 1/50 to 1/200 of all symbols, the influence of α is ignored.

On the other hand, in the conventional coding apparatus, if Na = 1728 * 2376 Nb = 0 Nc = 1728 * 2736 * (1/30) in the above equation, the coding processing time T is about 1.25 seconds. Therefore, it can be seen that the present invention can realize a significant improvement in the encoding processing speed.

Next, FIG. 5 shows a block configuration of a decoding device according to an embodiment of the second invention. In the figure, 10
Is an arithmetic decoder that reproduces the prediction error symbol 105 from the code bit sequence 107 based on the region width signal 106, and 11 performs an exclusive OR operation of the prediction error symbol 105 and the prediction value 113 to obtain the information source symbol 101. This is a predictive inverse converter for reproduction, and the other part is the same circuit as the embodiment of FIG.

FIG. 6 is a block diagram showing the internal structure of the arithmetic decoder 10. 10a is an effective area Ai on the number line.
A is a register for storing the MPS area width 117, 10c is a register for storing the lower bound coordinates, 10d is a subtracter for calculating the C register value 119 in the case of LPS, and 10e is a sign bit sequence 107. Is stored temporarily, and the most significant signal of the internal 9-bit register is sent to the C register in accordance with the normalized shift clock 122, and the contents of the lower 8 bits of the stored sign bit become eight consecutive "1" s. In this case, a code register for inputting 1 bit from the code bit sequence 107 and performing addition at the lowest position of the internal 9-bit register to perform stuff bit removal processing for deleting the bit stuff signal inserted in the encoder. 10f is a timing control circuit for controlling the movement of the arithmetic decoder 10.

Next, the operation of this embodiment will be described. In the decoding of the arithmetic code, if the relative coordinates that are the contents of the C register are Ci and the area width of the LPS at the time of the i-th prediction error symbol ai is S, then Ci-1 <(Ai-1 -S) Then, ai is MPS Ai = Ai-1-S Ci = Ci-1 Ci-1 ≧ (Ai-1-S), and if ai is LPS Ai = S Ci = Ci-1 (Ai-1-S) .

If the effective area Ai becomes 1/2 or less, the normalization process is performed to increase the calculation accuracy to 2
To the power of. At this time, the carry input signal 123 is input from the code register 10e from the least significant bit of Ci. Ai update value = Ai * 2m (1 / 2Ai update value ≦ 1) Ci update value = Ci * 2m

7 and 8 are timing charts showing an operation example of the present embodiment. FIG. 7 shows a case where the reference symbol patterns 102 are not all "0", and FIG. 8 shows a case where they are all "0". The operations of creating the reference symbol pattern 102, creating and updating the order / predicted value are the same as those in the embodiment of FIG.

Regarding the reproduction of the prediction error symbol ai and the calculation of the effective area Ai and the relative coordinates Ci, first, in the timing control circuit 10f, as described above, Ci-1 and (Ai
-1-S) is performed to determine the symbol ai (MPS or LPS), based on which Ai and Ci are calculated and set in the A register 10a and the C register 10c. This series of processing is performed in one cycle of the system clock.

As a result of this calculation, when the effective area Ai is less than 1/2, the above normalization processing is performed in m clocks. At this time, the contents of the lower 8 bits of the sign bit stored in the sign register 10e are consecutive 8 "1" s.
In this case, the normalized clock 121 is temporarily stopped, 1 bit is input from the code bit sequence 107, and the addition is performed at the lowest position of the internal 9-bit register.

Therefore, the decoding processing time T is the same as that at the time of encoding. T = 200 * Na + 100 * (Na + Nb) + 100 *
Since Nc + 100 * α (nsec), even in this embodiment, a great improvement can be realized as compared with the conventional decoding device. Further, in the above-described embodiment, the special register is provided only in the state of all “0” as the reference symbol pattern to speed up the processing. However, for example, a plurality of reference symbol patterns including the state of “1” are included. The register may be provided.

The third aspect of the present invention will be described below with reference to the illustrated embodiments. FIG. 9 shows an encoding apparatus according to an embodiment of the present invention. In FIG. 9, the difference from the conventional encoding apparatus of FIG. 25 is that the reference symbol pattern from the reference symbol pattern 102 to the immediately preceding encoding target symbol is changed. And the detector 7 for detecting whether or not the reference symbol pattern for the symbol to be encoded matches, the order 103 and the predicted value output 104 from the order / predicted value memory 2, or the order / predicted value control circuit 6 The point is that the order / prediction value register 8b for temporarily storing the update signal 108 is provided, and this output is used as an input to the region width table 4 and the prediction converter 3.

FIG. 10 is a block diagram showing the internal structure of the arithmetic encoder 5. In the figure, 5a is an A register for storing the effective area Ai on the number line, 5b is a subtractor for calculating the MPS area width 117, 5c is a C register for storing the lower bound coordinate 115, and 5d is a C register for the LPS. An adder for calculating the value 116, 5e is a carry output 117 which is an overflow (shift out) signal of the C register.
Is temporarily stored to carry a carry when updating the C register 5c, and if the stored sign bit contents are eight consecutive "1" s, "0" is inserted from the bottom of the least significant bit. Then, a code register 5f for performing processing (hereinafter referred to as bit stuffing processing) for suppressing the effect of the carry processing thereafter to this insertion "0" or less is a timing control circuit for controlling the operation of the arithmetic encoder 5. is there.

Next, the operation of this embodiment will be described.
FIG. 11 is a timing chart showing an operation example of this embodiment.
First, when the encoding target symbol is input to the present encoding device as the information source symbol 101, the reference symbol generator 1
26, the signal of the reference pixel of 12 pixels already processed in FIG. 26 is output, and the order and prediction value in the reference symbol pattern are read from the order / prediction value memory 2 and stored in the order / prediction value register 8. It In this embodiment, the process of creating the reference symbol pattern and storing it in the register 8 is 100 nsec for one cycle of the system clock of 10 MHZ.

The order signal 111 is converted into the area width signal 106 shown in FIG.
Reference numeral 12 is a prediction converter 3 which performs an exclusive OR operation on the information source symbol 101 to generate a prediction error symbol 105. After that, the calculation of the effective area Ai and the lower bound coordinate Ci and the update of the order / predicted value are performed as follows. (1) When normalization and order / prediction values are not updated (# 1 in FIG. 19), the calculation of the above area and coordinates is executed in one cycle of the system clock. (2) When there is normalization and there is no update of order / predicted value (# 2 in FIG. 19) The area / coordinate calculation processing other than normalization is executed in one cycle of the system clock, and normalization is executed in m clocks.

(3) When there is no normalization and the order / prediction value is updated (# 3 in FIG. 19) After the area and coordinates are calculated in one cycle of the system clock, the contents of the order / prediction value memory 2 are changed. Update. The memory is updated in one system clock cycle. (4) When there is normalization and update of order / predicted value (Fig. 19)
# 4) After the area / coordinate calculation processing excluding the normalization is performed in one cycle of the system clock, the normalization is performed in m clocks and the order / predicted value memory 2 is updated in parallel. At this time, the coordinate calculation process of the next symbol is performed after both the normalization and the update of the memory 2 are completed.

Here, the control of the area calculation and the coordinate calculation including the determination of LPS and MPS is performed by the prediction error symbol 105.
The timing / control circuit 5f of the arithmetic encoder 5 performs the update control of the order / predicted value memory 2 based on the MSB signal of the A register output 113 and the order / predicted value control circuit 6.

In the sign register 5e, the carry process is performed in parallel with the above-mentioned (excluding normalization) area / coordinate calculation. At the time of normalization, the carry from the 8th bit is output as code 107 along with the shift of the internal register. At this time, when all the bits of the 8-bit internal register are "1", the bit stuff signal 119 is sent to the timing control circuit 5f, the normalized clock 118 is temporarily stopped, and at the same time, one cycle of the system clock is used. 1-bit shift of the register (LSB shift-in signal is set to "0") is performed.

Since the order / predicted value may be updated in the reading process from the order / predicted value memory 2 and the calculation of the effective area Ai / lower bound coordinate Ci, conventionally, the serial / serial process is performed. It had been. In the present embodiment, this is performed in parallel with the calculation of the effective area Ai / lower bound coordinate Ci for the target symbol to be encoded and the reading process from the order / predicted value memory 2 for the next symbol to be encoded as follows. To process.

That is, when the order / prediction value register 8 outputs the order signal and prediction value signal of the target symbol to be coded, the order / prediction value memory 2 outputs the order and predicted value for the next target symbol to be coded. It is read using one cycle of the system clock. After that, the processing is performed as follows. (1) When normalization and order / prediction values are not updated (# 1 in FIG. 19) After the above area and coordinates are calculated, the area / coordinate calculation of the next encoding target symbol is performed. (2) When normalization is performed and order / prediction value is not updated (# 2 in FIG. 19) After normalization is completed, the process proceeds to the area / coordinate calculation of the next encoding target symbol. (3) When normalization is not performed and order / prediction value is updated (# 3 in FIG. 19) The contents of the order / prediction value memory 2 are updated by referring to the reference pattern (reference symbol) for the symbol output from the detector 7. The pattern 102 delayed by one symbol) and the update signal 108 from the order / prediction control circuit 6 are used. At this time, reference symbol pattern 1
If 02 (signal for the next encoding target symbol) and the reference pattern for the encoding target symbol match, the contents of the order / prediction value register are updated based on the detection signal 110. These content updates are processed in one cycle of the system clock, and then the area / coordinate calculation of the next encoding target symbol is performed. (4) When there is normalization and update of order / predicted value (Fig. 19)
# 4) The contents of the order / predicted value are updated in the same manner as (3).
If the normalization processing after the content update is not completed, it is waited for and the operation proceeds to the area / coordinate calculation of the next encoding target symbol.

As is apparent from the above description, the encoding processing time T in this embodiment is T = 100 + 100 * Na + 100 * Nc + 100 * α, where Na is the total number of symbols and Nc is the number of code bits.
(Nsec). Here, α is the number of clocks required to update the order and the predicted value in the above case (3). Therefore, A with a standard resolution of 8 pixels / mm horizontally and 7.7 lines / mm vertically
Assuming a compression ratio of 30 for a 4-size original, Na = 1728 * 2376 Nc = 1728 * 2736 * (1/30), and the encoding processing time T is about 0.4 seconds. Here, the update of the order / predicted value is about 1/50 to 1/200 of all symbols, and the case of (3) above is limited to the case where the prediction result is MPS and normalization does not occur. Ignored the effect of.

On the other hand, in the conventional encoding device, similarly, T = (100 + 100) * Na + 100 * Nc + 100
* Α (nsec). Therefore, if the calculation is performed under the same conditions as described above, the encoding processing time T becomes about 0.8 seconds, and it is understood that the present invention can realize a significant improvement in the encoding processing speed.

Next, FIG. 12 shows a block configuration of an encoding apparatus which is another embodiment of the present invention. In the figure, 9 is an update order / prediction value register, and 10 is an order / prediction value memory 2
Order / predicted value register 8 for storing the read signal from
And an output of the update order / predicted value register 9 are selected.

In this embodiment, only the read signal from the order / predicted value memory 2 is stored in the order / predicted value register 8, and the updated order / predicted value register 9 is subjected to the adaptive processing of the order and the predicted value (updated). If an update value is performed, a signal of the selector 10 output value used for area calculation is stored), and the detection signal 110 causes the reference pattern of the target symbol to be encoded immediately before. If the same as the reference pattern of the symbol, the output from the update order / prediction value register 9 is used, and if different, the output from the order / prediction value register 8 is used to perform the region width calculation and the predictive conversion. The other processing is the same as that of the embodiment shown in FIG. However, the detection signal 110 from the detector 7
Is delayed by one symbol as compared with the case of the embodiment of FIG.

Next, FIG. 13 shows a block configuration of a decoding apparatus which is an embodiment of the fourth invention. In the figure, 11
Is an arithmetic decoder that reproduces the prediction error symbol 105 from the code bit sequence 107 based on the region width signal 106, and 12 performs an exclusive OR operation of the prediction error symbol 105 and the prediction value 112 to obtain the information source symbol 101. It is a predictive inverse converter for reproduction. Further, 2 is A among the reference pixels in FIG.
In the order / prediction value memory, which inputs the reference symbol pattern of 11 pixels excluding, and outputs order and prediction value signals (two kinds of 103a, 104a and 103b, 104b, respectively) for two kinds of states in which A is 1 and 0 Yes, 8 is a register which receives this output and also stores two kinds of orders and predicted values. Further, 13 is a selector for selecting one of two kinds of orders and prediction values according to the information source symbol 101 immediately before reproduced by the prediction inverse converter 12, and updating from the order / prediction value control circuit 6. 26. For receiving the signal 108 and updating the contents of the order / prediction value memory 2 and the contents of the order / prediction value register 8 in which the reference pixel A of FIG. 26 is either 1 or 0 in accordance with the reproduced information source symbol. First selection update signal 108a and second selection update signal 108b
Has the function of creating. The other parts have the same circuit as the embodiment of FIG.

FIG. 14 is a block diagram showing the internal structure of the arithmetic decoder 11. 11a is an effective area A on the number line.
A register for storing i, 11b is MPS area width 114
, 11c is a register for storing the lower bound coordinates, 11d is a subtractor for calculating the C register value 116 in the case of LPS, 11e is the temporary storage of the sign bit sequence 107, and the subtraction is performed according to the normalized shift clock 118. The highest-order signal of the internal 9-bit register is sent to the C register, and when the contents of the lower 8 bits of the stored code bit become eight consecutive "1" s, the code bit sequence 107 to 1
A code register for performing stuff bit removal processing for deleting a bit stuff signal inserted in the encoder by inputting bits and performing addition at the lowest position of the internal 9-bit register. It is a timing control circuit that controls movement.

Next, the operation of this embodiment will be described. In the decoding of the arithmetic code, if the relative coordinates that are the contents of the C register are Ci and the area width of the LPS at the time of the i-th prediction error symbol ai is S, then Ci-1 <(Ai-1-S). Then ai is MPS Ai = Ai-1-S Ci = Ci-1 Ci-1 ≥ (Ai-1-S), and if ai is LPS Ai = S Ci = Ci-1 (Ai-1-S) .

Here, when the effective area Ai becomes 1/2 or less, the normalization processing is 2 to increase the calculation accuracy.
To the power of. At this time, the carry input signal 117 is input from the encoding register 11e from the least significant bit of Ci. Ai update value = Ai * 2m (1 / 2Ai update value ≦ 1) Ci update value = Ci * 2m

FIG. 15 is a timing chart showing an operation example of this embodiment. First, for the decoding target symbol, based on the reference symbol pattern of 11 pixels excluding A among the reference pixels in FIG. 26, the order and the prediction value for two kinds of states in which A is 1 and 0 are read from the memory 2 and registered. Store in 8. These processes are performed during the time of one cycle of the system clock. After that, the information source symbol A which is reproduced immediately before is A.
One of these two types of order and prediction value is selected according to the value of, and the information symbol is reproduced and the order and prediction value are updated.

Regarding the reproduction of the prediction error symbol ai and the calculation of the effective area Ai and the relative coordinates Ci, first, in the timing control circuit 11f, as described above, Ci-1 and (Ai
-1-S) is compared to determine the symbol ai (MPS or LPS), and based on this, Ai and Ci are calculated and set in the A register 11a and the C register 11c. This series of processing is performed in one cycle of the system clock.
As a result of this calculation, when the effective area Ai is less than 1/2, the above normalization processing is performed in m clocks. Here, when the contents of the lower 8 bits of the sign bit stored in the sign register 11e become eight consecutive "1" s, the normalized clock 118 is temporarily stopped and one bit is input from the sign bit sequence 107. And the addition is performed at the lowest position of the internal 9-bit register.

When it is necessary to update the order / predicted value, an update signal is issued from the order / predicted value control circuit 6, and the selector 13
In accordance with the value of the information source symbol reproduced immediately before, the reference pixel A has a selection update signal (108a, 108a,
108b) is generated and the contents of the order / predicted value memory 2 are updated. At this time, when the reference pattern 102 of the order / predicted value memory 2 read immediately before matches the update reference symbol pattern, the contents of the order / predicted value register 8 are updated at the same time. This updating process is performed after setting the A register and the C register, and is executed in one system clock period.

Therefore, the decoding processing time T is the same as the encoding time T = 100 + 100 * Na + 100 * Nc + 100 * α
Since it is (nsec), even in the present embodiment, a great improvement can be realized as compared with the decoding device according to the conventional technique.

FIG. 16 shows a block configuration of a decoding device which is another embodiment. In this embodiment, as in FIG. 13, a register 9 for updating is provided separately from the register 8a for storing the read signal of the memory 2, and a selector 10 is added. However, like the embodiment of FIG. 12, in this embodiment, the detector 7 is different from that of the embodiment of FIG.
The detection signal output 110 of 1 is delayed by one symbol.

In the above embodiment, the order and the predicted value are updated by L
The method of counting and controlling the number of PS and MPS was used.
A method of controlling updating may be used only at the timing of normalization as in the IBM research and development information.

The fifth invention will be described below with reference to the illustrated embodiments. FIG. 17 shows an encoding apparatus according to an embodiment of the present invention. In FIG. 17, the difference from the conventional encoding apparatus of FIG. 25 is that the eight symbols to be encoded immediately before the reference symbol pattern 102 are included. 26, the detector 7 for detecting whether all 12 reference pixels are “0” (white pixels) and the coded symbols are also “0”, and when all 12 reference pixels are “0” A register 8 for storing the order and the predicted value, and an a11 “0” state order signal 110 indicating that the output is the highest order 16 when the detector 7 output and all 12 reference pixels from the register 8 are “0”. Similarly, a11 "0" state prediction signal 11 indicating that the prediction value is "0"
That is, the first AND circuit 9 for calculating the logical product of 1 is added.

FIG. 18 is a block diagram showing the internal structure of the arithmetic encoder 5. In the figure, 5a is an A register for storing the effective area Ai on the number line, 5b is a subtracter for calculating the MPS area width 114, 5c is a C register for storing the lower bound coordinate 115, and 5d is a C register for the LPS. An adder for calculating the value 116, 5e is a carry output 117 which is an overflow (shift out) signal of the C register.
Is temporarily stored to carry a carry when updating the C register 5c, and if the stored sign bit contents are eight consecutive "1" s, "0" is inserted from the bottom of the least significant bit. Then, a code register 5f for performing processing (hereinafter referred to as bit stuffing processing) for suppressing the effect of the carry processing thereafter to this insertion "0" or less is a timing control circuit for controlling the operation of the arithmetic encoder 5. is there.

Further, the output of the A register is 0x100 for 5g.
The area detector 5h for detecting that the voltage exceeds 0 + 0X 0008 is a second AND circuit 5h for calculating the logical product of this output and the switching signal 112 which is the output of the first AND circuit 9 When the AND circuit output of 1 is 1, it is a switcher that multiplies the area width signal 106 by 8. Of these, 5
The circuits from a to 5f are used in the conventional arithmetic encoder, and the difference between this embodiment and the conventional device is 5g to 5i.
Is the time when was added.

Next, the operation of this embodiment will be described.
19 and 20 are timing charts showing an operation example of this embodiment. For ease of explanation, when all the reference symbol patterns 102 for consecutive 8 coded symbols are not “0” (hereinafter, simply referred to as a11 “0” state), the reference symbol pattern 102 for consecutive 8 coded symbols is shown. Will be described separately by dividing into cases where all are "0".

First, in the a11 "0" state, when the prediction target symbol is input to the present coding apparatus as the information source symbol 101, the reference pixel generator 1 has already processed 12 pixels of 12 pixels shown in FIG. The signal of the reference pixel is output 102, and it is determined in the detector 7 that the reference symbol patterns for the continuous 8 coded symbols are not all “0”. Therefore, the detection signal 109 is "0".
Is output. At the same time, the order / prediction value memory 2 outputs the order signal 103 in the reference symbol pattern.
Also, the output signal of the prediction value signal 104 is read. Here, in the present embodiment, the reading process of the memory 2 is 10 MHz.
The system clock is set to 100 nsec for one cycle.

The order signal 103 is converted into a region width signal 106 shown in FIG.
Reference numeral 04 is a prediction converter 3 which performs an exclusive OR operation on the information source symbol 101 to generate a prediction error symbol 105. After that, the calculation of the effective area Ai and the lower bound coordinate Ci and the update of the order / predicted value are performed as follows. (1) When normalization and order / prediction values are not updated (# 1 in FIG. 19), the calculation of the above area and coordinates is executed in one cycle of the system clock. (2) When there is normalization and there is no update of order / predicted value (# 2 in FIG. 19) The area / coordinate calculation processing other than normalization is executed in one cycle of the system clock, and normalization is executed in m clocks. (3) When there is no normalization and there is an update of the order / predicted value (# 3 in FIG. 19) The area and coordinates are calculated in one cycle of the system clock, and then the contents of the order / predicted value memory 2 are updated. The memory is updated in two system clock cycles. (4) When there is normalization and update of order / predicted value (Fig. 19)
# 4) After the area / coordinate calculation processing excluding the normalization is performed in one cycle of the system clock, the normalization is performed in m clocks and the order / predicted value memory 2 is updated in parallel. At this time, the processing of the next symbol is performed by normalization and memory 2.
It will be done after the update of both ends.

Here, when the order / predicted value is updated in the a11 "0" state, the contents of the order / predicted value register 8 for the a11 "0" state are updated at the same time as the order / predicted value memory 2. .

The control of the area calculation and the coordinate calculation including the determination of LPS and MPS is performed by the prediction error symbols 105 and A.
Based on the MSB signal of the register output 113, the timing control circuit 5f of the arithmetic encoder 5 performs the update control of the order / predicted value memory 2 by the order / predicted value control circuit 6.

In the sign register 5e, the carry process is performed in parallel with the above-mentioned (excluding normalization) area / coordinate calculation. At the time of normalization, a carry code 107 from the 8th bit is output together with the shift of the internal register. At this time, when all the bits of the 8-bit internal register are "1", the bit stuff signal 119 is sent to the timing control circuit 5f, the normalized clock 118 is temporarily stopped, and at the same time, one cycle of the system clock is used. 1-bit shift of the register (LSB shift-in signal is set to "0") is performed.

When all the reference symbol patterns 102 for 8 consecutive encoded symbols are "0", the first and second
The AND circuit determines whether or not to collectively process the arithmetic operations. That is, the output 121 of the second AND circuit 5h is
The corresponding 8 encoded symbols are all "0" (detection signal 10
9 is “1”), and a11 “0” state order is 16 (a
When the 11 "0" state order signal 110 is "1") and the predicted value of the same state is "0" (a11 "0" state predicted value "1"), it becomes "1". When this is "0", the processing is performed at the timing shown in FIG.

In the case of batch processing, the area width signal 106 is multiplied by 8 by the switch 5i, and "0X 0008" is subtracted by the subtractor 5b.
Is used as the subtraction input 123 for arithmetic operation. A just before
Since the register output 113 exceeds 0X0008 and becomes 0X1000 or more even if the verification processing is performed, the normalization processing does not occur. Further, since the order and the predicted value are not updated, the next coded symbol, that is, the 9th pixel is continuously coded. This area arithmetic processing can be performed in one cycle of the system clock. The operation of this process is shown in FIG.

In the above, the case where all of the continuous 8 reference symbol patterns 102 are "0" or other cases have been described separately, but in actual image signal encoding, these occur in a mixed manner. Therefore, the operation timing is as shown in FIG.
1 and each case of FIG. 12 are combined.

As is clear from the above description, the coding processing time T in this embodiment is such that when the batch processing is possible, that is, all the reference symbol patterns for the 8 consecutive coding target pixels are "0", and All the corresponding 8 coded symbols are "0", the degree of the a11 "0" state is 16, the predicted value of the same state is "0", and the effective area width is 0X 100.
Assuming that the number of encoding target symbols in the case of exceeding 0 + 0X 0008 is Na, the number of other encoding target symbols is Nb code, and the number of code bits is Nc, T = 100 (Na / 8 + Nb) + 100 * (Na / 8 + Nb ) + 100 * Nc + 100 * α (nsec). Here, α is the required number of clocks when updating the order / predicted value in (3) above.

Therefore, the standard resolution is horizontal 8 pixels / m.
Assuming that the ratio of pixels that can be collectively processed is 2/3 and the compression rate is 30 as an A4 size document of m, vertical 7.7 lines / mm, Na = 1728 * 2376 (2/3) Nb = 1728 * 2376 * (1/3) Nc = 1728 * 2736 * (1/30), and the encoding processing time T becomes about 0.35 seconds. Here, since the update of the order / predicted value is about 1/50 to 1/200 of all symbols, the influence of α is ignored.

On the other hand, in the conventional encoding apparatus, if Na = 0 Nb = 1728 * 2376 Nc = 1728 * 2736 * (1/30) in the above equation, the encoding processing time T is about 0.83 seconds. Therefore, it can be seen that the present invention can realize a significant improvement in the encoding processing speed.

Next, FIG. 21 shows a block configuration of a decoding apparatus which is an embodiment of the sixth invention. In the figure, 10 is an arithmetic decoder that reproduces a prediction error symbol 105 from a code bit sequence 107 based on a region width signal 106, and 11 is an information obtained by performing an exclusive OR operation of the prediction error symbol 105 and a prediction value 104. It is a predictive inverse transformer that reproduces the source symbol 101. Reference numeral 12 denotes a batch processing identification signal 121 from the arithmetic decoder 10 and, in the case of normal processing, a prediction inverse converter 11
In the case of batch processing, the output is an information symbol switch (selector) that outputs eight consecutive "0" signals as the information source symbol 101, and the other parts are the same circuits as in the embodiment of FIG.

FIG. 22 is a block diagram showing the internal structure of the arithmetic decoder 11. 10a is an effective area A on the number line.
A register for storing i, 10b is MPS area width 117
Is a register for storing the lower bound coordinates, 10d is a subtractor for calculating the C register value 119 in the case of LPS, 10e is a temporary storage of the sign bit sequence 107, and is stored in accordance with the normalized shift clock 122. The highest-order signal of the internal 9-bit register is sent to the C register, and when the contents of the lower 8 bits of the stored code bit become eight consecutive "1" s, the code bit sequence 107 to 1
A code register 10f for performing stuff bit removal processing for deleting the bit stuff signal inserted in the encoder by inputting bits and performing addition at the lowest position of the internal 9-bit register is the arithmetic decoder 10. It is a timing control circuit that controls movement. Furthermore, 10g
Is a region detector that detects that the output of the A register exceeds 0X 1000 + 0X 0008, and 10h is a second AND circuit that calculates the logical product of this output and the switching signal 112 that is the output of the first AND circuit 9. 10i is this second
When the AND circuit output of 1 is 1, it is a switcher that multiplies the area width signal 106 by 8.

Next, the operation of this embodiment will be described. In the decoding of the arithmetic code, if the relative coordinates that are the contents of the C register are Ci and the area width of the LPS at the time of the i-th prediction error symbol ai is S, then Ci-1 <(Ai-1-S). Then ai is MPS Ai = Ai-1-S Ci = Ci-1 Ci-1 ≥ (Ai-1-S), and if ai is LPS Ai = S Ci = Ci-1 (Ai-1-S) .

Here, when the effective area Ai becomes 1/2 or less, the normalization processing is performed as 2 to improve the calculation accuracy.
To the power of. At this time, the carry input signal 117 is input from the code register 10e from the least significant bit of Ci. Ai update value = Ai * 2m (1 / 2Ai update value ≦ 1) Ci update value = Ci * 2m

23 and 24 are timing charts showing an operation example of this embodiment. 23 shows a case where normal processing is performed as in FIG. 19, and FIG. 24 shows a case where batch processing is performed. The operations of creating the reference symbol pattern 102, creating and updating the order / predicted value are the same as those in the embodiment of FIG.

Next, in the case of normal processing, regarding the reproduction of the prediction error symbol ai and the calculation of the effective area Ai and the relative coordinates Ci, first, in the timing control circuit 10f, as described above, Ci-1 and (Ai-1- S) is compared to determine the symbol ai (MPS or LPS), based on which Ai and Ci are calculated and the A registers 10a and C are calculated.
It is set in the register 10c. This series of processing is performed in one cycle of the system clock. As a result of this calculation, when the effective area Ai becomes less than 1/2, the above normalization processing is performed in m clocks. At this time, if the contents of the lower 8 bits of the sign bit stored in the sign register 10e become eight consecutive "1" s, the normalized clock 118
Is temporarily stopped, 1 bit is input from the sign bit sequence 107, and addition is performed at the lowest position of the internal 9-bit register.

In the case of collective processing, that is, except for the pixels for which the restoration of the information source symbols has not been completed, the reference symbol patterns for all 8 consecutive encoding target pixels are "0" (the detection signal 109 is "1"). , And the degree of the a11 “0” state is 16 (the a11 “0” state degree signal 110 is “1”), and the predicted value of the state is “0” (a11 “0”).
The state prediction value signal 111 is “1”), and the effective area width 11
If 3 exceeds 0X 1000 + 0X 0008 (area detector output 120 is "1"), "0X 0008" is used as the area width subtraction signal 122 by the switch 10i, as in the case of FIG. Arithmetic operations are performed on consecutive symbols. This processing is performed in one cycle of the system clock as in FIG. As the information source symbol 101 restored at this time, 8 consecutive "0" s are output from the information source symbol switching unit 12 regardless of the output of the predictive inverse transformer 11.

Therefore, the decoding processing time T becomes T = 100 (Na / 8 + Nb) + 100 * (Na / 8 + Nb) + 100 * Nc + 100 * α (nsec) as in the case of encoding. It is possible to realize a significant improvement compared to the digitalization device.

Further, in the above embodiment, the special register is provided only for the state of all "0" as the reference symbol pattern to speed up the processing. However, for example, the state of all the reference symbol patterns including "1" is included. Alternatively, a plurality of registers may be provided. Further, in the present embodiment, the batch processing is performed only when the order is the highest 16;
In the case of the 5th order, the effective area width 13 is 0X 1000 + 0X 10
The same batch processing may be performed by using 00 as the criterion of the area detector 5g.

Further, in the above embodiment, the order and the predicted value in a specific symbol pattern state are read from the order / predicted value memory 2. However, as in the first invention, a circuit for switching the order and the predicted value is provided. When all the reference symbol patterns are “0”, the order / prediction value memory 2 may not be read or updated.

In the above embodiment, the method of adapting the order and the prediction value based on the number of MPS or LPS occurrences is shown. However, as described in the above IBM R & D information, the symbol at the time of normalization occurs. The same effect as above can be obtained even if the method is applied according to MPS or LPS.

[0104]

The encoding apparatus according to the first and second aspects of the present invention provides the predicted value of the symbol to be coded and the order which is an identifier based on the predictive matching rate, corresponding to the pattern of the reference symbol. A memory for storing and a detector for detecting that the pattern of the reference symbol is a specific pattern,
A register for storing the predicted value and the order for the specific pattern, a selector for selecting the memory and the register output based on the detector output, and a code based on the predicted value / order information output from the selector Arithmetic coding means for coding the symbol to be coded, judgment means for judging whether or not the symbol to be coded predictively matches, and rewriting the predicted value and order for the reference symbol pattern based on the judgment result. Since the order / predicted value control circuit is provided, when the pattern of the reference symbol is in a specific pattern, the register output is selected for reading and updating the order / predicted value, and in other patterns, from the memory. Since the output signal can be selected and used, there is an effect that the coding speed is improved.

A decoding device according to the inventions of claims 3 and 4 stores a memory for storing the predicted value of the decoding target symbol and the order which is an identifier based on the predicted matching rate, corresponding to the pattern of the reference symbol. A detector that detects that the pattern of the reference symbol is a specific pattern, a register that stores the predicted value and order for the specific pattern, and the memory and the register output based on the detector output. A selector, an arithmetic decoding means for decoding the code bit sequence based on the predicted value / order information output from the selector, and a judging means for judging whether or not the decoding target symbols are predictively matched. And the order / prediction value control circuit that rewrites the prediction value and the order for the reference symbol pattern based on the determination result. If the pattern is in a specific pattern, the register output can be selected to read and update the order / predicted value, and in other patterns, the output signal from the memory can be selected and used, improving the decoding speed. There is an effect of doing.

An encoding apparatus according to a fifth aspect of the present invention includes a memory for storing the predicted value of the symbol to be coded and the order which is an identifier based on the predictive matching rate corresponding to the pattern of the reference symbol, and this memory. Order / prediction value register for storing the predicted value and order of the target symbol to be encoded read from, determination means for determining whether or not the target symbol to be encoded matches prediction, and based on the determination result Order / predicted value control circuit for rewriting the predicted value and order of the memory in the reference symbol pattern, and the order / predicted value according to the comparison result of the reference symbol pattern for the symbol to be coded and the reference symbol pattern for the immediately preceding symbol. The detector that updates the contents of the register and the predicted value / order information stored in the above order / predicted value register And the arithmetic coding means for coding the coding target symbol are provided, so that the result of comparison between the reference symbol pattern for the coding target symbol and the reference symbol for the immediately preceding symbol is used as the prediction value and order used in the coding process. According to the above, after updating the contents of the order / prediction value register, the encoding target symbol can be coded based on the updated prediction value / order information, so that the coding speed is improved.

According to a sixth aspect of the present invention, there is provided a coding apparatus, which stores a predicted value of the target symbol to be coded corresponding to a pattern of a reference symbol and a degree which is an identifier based on a predicted matching rate, and the code. Determination means for determining whether or not the symbol to be coded is predictively matched, an order / predicted value control circuit for rewriting the predicted value and order of the memory in the reference symbol pattern based on the result of the determination, and immediately preceding encoding According to the result of comparison between the register for storing the predicted value and the order after rewriting for the target symbol and the reference symbol pattern for the above-mentioned symbol to be coded and the reference symbol pattern for the immediately preceding symbol, the order / predicted value from the memory or the immediately preceding Select one of the registers that store the predicted value and order for the symbol to be coded. And the arithmetic coding means for coding the target symbol for encoding based on the output of the selector. Therefore, as a predictive value and order signal used in the encoding process, reference to the target symbol for encoding is provided. Depending on whether or not the symbol pattern matches the reference symbol for the immediately preceding symbol, it is possible to select and use the predicted value after the rewriting process and the order or the output signal from the memory for the immediately preceding symbol to be encoded. As a result, the coding speed is improved.

According to the seventh and eighth aspects of the present invention, the predicted value of the decoding target symbol and the order which is an identifier based on the predicted matching rate are stored in correspondence with the reference symbol pattern, and a plurality of references are stored. A memory that outputs the predicted value and the order corresponding to the symbol pattern in parallel, a selector that selectively outputs one set of the predicted value and the order among the memory outputs for the plurality of reference symbol patterns, and a selected order Arithmetic decoding means for decoding a coded bit sequence based on a prediction value, a register for storing the output of the memory, a determination means for determining whether or not the decoding target symbol is predictively matched, and An order / prediction value control circuit that rewrites a prediction value and an order for the reference symbol pattern based on the determination result, and a reference symbol for the encoding target symbol According to the comparison result of the reference symbol pattern for turn and the previous symbol, the degree and
Since a detector for updating the contents of the prediction value register is provided, whether the pattern of the reference symbol for the symbol to be decoded and the reference symbol for the immediately preceding symbol match as the prediction value and order signal used in the decoding process. Depending on whether or not the prediction value and the order after the rewriting process or the output signal from the memory can be selected and used for the immediately preceding symbol to be decoded, the decoding speed is improved.

According to the inventions of claims 7 and 9, the predicted value of the symbol to be decoded and the order which is an identifier based on the predicted matching rate are stored in correspondence with the pattern of the reference symbol, and a plurality of references are stored. A memory that outputs the predicted value and the order corresponding to the symbol pattern in parallel, a selector that selectively outputs one set of the predicted value and the order among the memory outputs for the plurality of reference symbol patterns, and a selected order Arithmetic decoding means for decoding the coded bit sequence based on the prediction value, determination means for determining whether or not the decompression target symbols are predictively matched, and for the reference symbol pattern based on the determination result An order / prediction value control circuit that rewrites the prediction value and the order, and a register that stores the renewed prediction value and order for the immediately preceding symbol to be decoded. A detector reference symbol pattern for the reference symbol pattern and the previous symbol for decoded symbol it is detected whether or not the match, on the basis of the detector output, degree and which is selected by the selector
Since a second selector is provided for selecting either the predicted value or the predicted value for the immediately preceding decoding target symbol and the order / predicted value from the register that stores the order, the predicted value used for the decoding process and As the order signal, the order / predicted value selected by the selector or the rewriting process for the immediately preceding decoding target symbol depending on whether the pattern of the reference symbol for the decoding target symbol and the reference symbol for the immediately preceding symbol match. It is possible to select and use the output signal from the register for storing the subsequent prediction value and order or the order / prediction value, which is effective in improving the decoding speed.

According to the tenth and eleventh aspects of the present invention, a memory for storing the predicted value of the coding target symbol and the order which is an identifier based on the predicted matching rate, corresponding to the pattern of the reference symbol, A detector for detecting that the patterns of reference symbols for a plurality of continuous encoding target symbols are all specific patterns and all the encoding target symbols predictively match, and the memory based on the detector output. Arithmetic coding that operates by switching between processing for coding the coding target symbols one symbol at a time according to the prediction value / order information stored in the above or for collectively coding the plurality of coding target symbols Means and
A determination unit that determines whether or not the encoding target symbols are predictively matched, and an order / predicted value control circuit that rewrites the predicted value and the order of the memory in the reference symbol pattern based on the determination result are provided. Therefore, when the pattern of the reference symbols for a plurality of consecutive symbols to be encoded is in a specific pattern, the arithmetic encoder can collectively perform the arithmetic operation on the plurality of symbols. This has the effect of increasing speed.

According to the twelfth and thirteenth aspects of the present invention, a memory for storing the predicted value of the symbol to be decoded and the order which is an identifier based on the predictive matching rate in correspondence with the pattern of the reference symbol is continuous. When it is assumed that a plurality of decoding target symbols are predictively matched, a detector for detecting that all the patterns of reference symbols for the plurality of decoding target symbols are specific patterns, and a detector output based on the detector output. In addition, the operation is performed by switching the process of encoding the symbol to be encoded one symbol at a time according to the prediction value / order information stored in the memory or collectively decoding the plurality of symbols to be decoded. Arithmetic decoding means for determining whether or not the decoding target symbol predictively matches, and the reference symbol pattern based on the determination result. Since an order / predicted value control circuit that rewrites the predicted value and the order for a symbol is provided, when the reference symbol pattern for a plurality of consecutive decoding target symbols is in a specific pattern, in the arithmetic encoder Since it is possible to collectively perform arithmetic operations on a plurality of symbols, there is an effect that the decoding speed is improved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an encoding apparatus according to an embodiment of the first present invention.

FIG. 2 is a block configuration diagram showing an internal configuration of an arithmetic encoder in this embodiment.

FIG. 3 is a timing chart showing an operation example according to the present embodiment.

FIG. 4 is a timing diagram showing an operation example according to the present embodiment.

FIG. 5 is a block configuration diagram of a decoding device showing an embodiment of a second invention.

FIG. 6 is a block configuration diagram showing an internal configuration of an arithmetic decoder in the present embodiment.

FIG. 7 is a timing diagram showing an operation example according to the present embodiment.

FIG. 8 is a timing diagram showing an operation example according to the present embodiment.

FIG. 9 is a block configuration diagram of an encoding apparatus according to an embodiment of the third invention.

10 is a block diagram showing an internal configuration of an arithmetic encoder in the embodiment of FIG.

FIG. 11 is a timing diagram illustrating an operation example according to the embodiment of FIG.

FIG. 12 is a block diagram of an encoding device according to another embodiment of the present invention.

FIG. 13 is a block configuration diagram of a decoding device showing an embodiment of the fourth invention.

14 is a block diagram showing an internal configuration of an arithmetic decoder in the embodiment of FIG.

FIG. 15 is a timing diagram showing an operation example according to the embodiment of FIG.

FIG. 16 is a block diagram of a decoding device showing another embodiment of the present invention.

FIG. 17 is a block configuration diagram of an encoding device according to an embodiment of the fifth invention.

FIG. 18 is a block diagram showing an internal configuration of an arithmetic encoder in the embodiment of FIG.

19 is a timing diagram showing an operation example according to the embodiment of FIG.

20 is a timing diagram showing an operation example according to the embodiment of FIG.

FIG. 21 is a block diagram of a decoding device showing an embodiment of the sixth invention.

22 is a block diagram showing the internal structure of the arithmetic decoder in the embodiment of FIG. 21. FIG.

23 is a timing diagram showing an operation example according to the embodiment of FIG. 21. FIG.

FIG. 24 is a timing diagram showing another operation example according to the embodiment of FIG. 21.

[Fig. 25] Fig. 25 is a block configuration diagram of an encoding device according to a conventional technique.

FIG. 26 is a diagram showing positions of reference symbols used for encoding.

FIG. 27 is a diagram showing the contents of an order / predicted value table.

FIG. 28 is a diagram showing the contents of an area width table.

[Explanation of symbols]

 2nd order / predicted value memory 3 Prediction converter 5 Arithmetic encoder 6 Order / predicted value control circuit 7 Detector 8 Order / predicted value register 9, 12 Selector 10 Arithmetic decoder 11 Predictive inverse converter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Tomohiro Kimura 5-1-1, Ofuna, Kamakura-shi, Kanagawa Mitsubishi Electric Corporation Communication Systems Laboratory (72) Fumitaka Ono 5-1-1, Ofuna, Kamakura-shi, Kanagawa No. Mitsubishi Electric Co., Ltd. Communication Systems Laboratory (56) Reference JP-A-2-305225 (JP, A) JP-A-2-202267 (JP, A) JP-A-2-65373 (JP, A) US Patent 5313204 (US, A) European Patent Application Publication 510627 (EP, A)

Claims (13)

[Claims] 1. A coding apparatus for predicting a coding target symbol from a pattern of a plurality of reference symbols at a predetermined position of an output symbol sequence of an information source and coding a prediction error signal thereof, the reference symbol Corresponding to the pattern of, a memory that stores the predicted value of the encoding target symbol and an order that is an identifier based on the predictive matching rate, a detector that detects that the pattern of the reference symbol is a specific pattern, A register for storing the predicted value and the order for the specific pattern, a selector for selecting the memory and the register output based on the detector output, and a code based on the predicted value / order information output from the selector code KaSo location, characterized by comprising an arithmetic encoding means for encoding the encoding target symbol. 2. A determination means for determining whether or not the encoding target symbols are predictively matched, and an order / prediction value control circuit for rewriting a prediction value and an order for the reference symbol pattern based on the result of the determination. The encoding device according to claim 1, further comprising: 3. A code bit sequence in which a prediction error signal is encoded is decoded by predicting a symbol to be encoded from a pattern of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source. In the decryption device,
A memory for storing the predicted value of the decoding target symbol corresponding to the pattern of the reference symbol and the order which is an identifier based on the predicted matching rate; and a detector for detecting that the pattern of the reference symbol is a specific pattern. , A register for storing a predicted value and order for the specific pattern, a selector for selecting the memory and register output based on the detector output, and a predicted value / order information output from the selector. A decoding device comprising arithmetic decoding means for decoding a code bit sequence. 4. Determining means for determining whether or not the decoding target symbols are predictively matched, and an order / predicted value control circuit for rewriting a predicted value and an order for the reference symbol pattern based on the result of the determination. The decoding device according to claim 3, wherein the decoding device is provided. 5. A coding apparatus for predicting a symbol to be coded from a pattern of a plurality of reference symbols at a predetermined position of an output symbol sequence of an information source and coding a prediction error signal thereof, the reference symbol comprising: And a memory for storing the predicted value of the coding target symbol and the order which is an identifier based on the prediction matching rate, and the predicted value and the order of the coding target symbol read from the memory. An order / prediction value register, a determination unit for determining whether or not the encoding target symbols are predictively matched, and a order / order for rewriting the prediction value and order of the memory in the reference symbol pattern based on the determination result. The predictive value control circuit, the reference symbol pattern for the symbol to be coded, and the reference symbol pattern for the immediately preceding symbol. A detector that updates the contents of the order / prediction value register according to the comparison result of the code and an arithmetic operation that encodes the encoding target symbol based on the prediction value / order information stored in the order / prediction value register. An encoding device comprising: an encoding unit. 6. A coding device for predicting a coding target symbol from a pattern of a plurality of reference symbols at a predetermined position of an output symbol sequence of an information source and coding a prediction error signal thereof, the reference symbol A memory for storing a predicted value of the encoding target symbol corresponding to the pattern and an order that is an identifier based on a prediction matching rate; and a determining unit for determining whether or not the encoding target symbol predictively matches. An order / prediction value control circuit that rewrites the prediction value and order of the memory in the reference symbol pattern based on the determination result; a register that stores the rewriting prediction value and order for the immediately preceding symbol to be encoded; The comparison result of the reference symbol pattern for the target symbol and the reference symbol pattern for the immediately preceding symbol. According, degree and predicted value from said memory or,
A selector for selecting one of the registers for storing the predicted value and the order for the immediately preceding symbol to be encoded, and an arithmetic encoding means for encoding the symbol to be encoded based on the output of the selector. An encoding device characterized by the above. 7. An encoding target symbol is predicted from patterns of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source, and a code bit sequence obtained by encoding the prediction error signal is decoded. In the decoding device, the predicted value of the decoding target symbol and the order which is an identifier based on the predicted matching rate are stored in correspondence with the pattern of the reference symbol, and the predicted value and the order corresponding to the plurality of reference symbol patterns are arranged in parallel. And a selector for selectively outputting a set of prediction values and orders of the memory outputs for a plurality of reference symbol patterns,
A decoding device comprising an arithmetic decoding means for decoding an encoded bit sequence based on the selected order / predicted value. 8. A register for storing the output of the memory, a judgment means for judging whether or not the decoding target symbols are predictively matched, and a prediction value and order for the reference symbol pattern based on the result of the judgment. And a detector that updates the contents of the order / prediction value register according to the result of comparison between the reference symbol pattern for the decoding target symbol and the reference symbol pattern for the immediately preceding symbol. The decoding device according to claim 7, wherein: 9. A determination means for determining whether or not the decoding target symbols are predictively matched, and an order / prediction value control circuit for rewriting a prediction value and an order for the reference symbol pattern based on the result of the determination. A register that stores the predicted value and order after rewriting for the immediately preceding decoding target symbol, a detector that detects whether the reference symbol pattern for the decoding target symbol matches the reference symbol pattern for the immediately preceding symbol, and A second order selecting either the order / predicted value selected by the selector or the order / predicted value from a register storing the predicted value and the order for the immediately preceding symbol to be decoded, based on the detector output; The decoding device according to claim 7, further comprising a selector. 10. A coding apparatus for predicting a coding target symbol from a pattern of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source and coding a prediction error signal thereof, the reference symbol Corresponding to the pattern, the memory that stores the predicted value of the encoding target symbol and the order that is an identifier based on the predictive matching rate, and the pattern of the reference symbol for a plurality of consecutive encoding target symbols are all specified. A detector that detects that all the symbols to be coded are predictive and coincides with a pattern, and based on the output of the detector, the symbols to be coded are symbol-by-symbol by the prediction value / order information stored in the memory. An arithmetic coder that operates by switching the processing of whether to code or to collectively code the plurality of coding target symbols. An encoding device comprising a stage. 11. Determining means for determining whether or not the encoding target symbols are predictively coincident, and order / predictive value control for rewriting the predictive value and the order of the memory in the reference symbol pattern based on the determination result. The encoding device according to claim 10, further comprising a circuit. 12. A code bit sequence for encoding a prediction error signal by predicting a symbol to be encoded from a pattern of a plurality of reference symbols at predetermined positions of an output symbol sequence of an information source and decoding the prediction error signal. In the decoding device, when the prediction value of the decoding target symbol corresponding to the pattern of the reference symbol and the order which is the identifier based on the prediction matching rate are stored, and a plurality of consecutive decoding target symbols predictively match If it is assumed that the reference symbol patterns for the plurality of decoding target symbols are all specific patterns, and a predictive value stored in the memory based on the detector output. Whether the encoding target symbols are encoded one symbol at a time according to the order information, or whether the plurality of decoding target symbols are collectively decoded. A decoding device comprising an arithmetic decoding means that operates by switching the processing of. 13. Determining means for determining whether or not the decoding target symbols are predictively matched, and an order / predictive value control circuit for rewriting a predictive value and an order for the reference symbol pattern based on a result of the determination. The decoding device according to claim 12, further comprising: