JPH0567021A - Serial data communication method and device - Google Patents

Abstract

PURPOSE:To shorten a data transferring time by adding a simple constitution, as for a method and device by which serial data are transmitted and received between plural digital signal processors connected like a loop. CONSTITUTION:At the time of transmitting the serial data by inverting a transferring direction(step 50 and 51), when an inhibit signal INH* is invalid, the INH* is made valid(step 52-54), and when a busy signal SNBSY* is invalid, a direction signal SNDIR is inverted(step 55-57), the INH* is made invalid(step 58), the SNBSY* is made valid(step 59), the serial data are transmitted(step 60), and the SNBSY* is made invalid (step 61)

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data communication method and device for transmitting / receiving serial data between a plurality of digital signal processing devices connected in a loop.

[0002]

2. Description of the Related Art For example, in the control of an articulated robot equipped with a camera and a force sensor, a plurality of MPUs share the processing, so that multifunctional real-time processing can be performed at high speed. If a general-purpose bus such as a VME bus is used to transfer data between such MPUs, the configuration of the data communication device becomes complicated.

Therefore, the MPUs are connected as shown in FIG. 6 to simplify the configuration of the data communication device. That is, the output port PO of MPU1 and the input port PI of MPU2 are connected by a communication line DL12, the output port PO of MPU2 and the input port PI of MPU3 are connected by a communication line DL23, and the output port PO of MPU3 and the input port of MPU4 are connected. The PI is connected by the communication line DL34, the output port PO of the MPU4 and the input port PI of the MPU1 are connected by the communication line DL41, and data is transferred between the four MPUs.

[0004]

However, since the data transfer direction is one direction, for example, from MPU1 to MP
When transferring data to U4, from MPU1 to MPU2,
There has been a problem that data must be transferred in order from MPU2 to MPU3 and then from MPU3 to MPU4, and the transfer time becomes long.

In view of the above problems, an object of the present invention is to provide a serial data communication method and device which can shorten the data transfer time between a plurality of digital signal processing devices by adding a simple configuration. To provide.

[0006]

A method and apparatus for serial data communication according to the present invention will be described with reference to the reference numerals of corresponding constituent elements in the drawings.

In the method of the present invention, as shown in FIG.
For example, in a method in which four digital signal processing devices 11 to 14 are connected in a loop through signal lines DL12, DL23, DL34, and DL41 and serial data is transmitted and received between the digital signal processing devices 11 to 14, each digital signal The processing devices 11 to 14 use the transfer direction signal SNDIR.
The serial data input terminal and output terminals P1 and P2 are switched according to the above, and the following communication control is performed.

This communication control is performed, for example, as shown in FIG.
When the serial data is transmitted with the transfer direction reversed (steps 50 and 51), another digital signal processing device 1
When the transfer direction reverse rotation reservation signal INH * by 1 to 14 is invalid, the transfer direction reverse rotation reservation signal INH * is validated (steps 52 to 54), and the signal transfer in-progress signal SNBSY by the other digital signal processing devices 11 to 14 is obtained. When * is invalid, the transfer direction signal SNDIR is inverted (steps 55 to 57), the transfer direction reverse rotation reservation signal INH * is invalidated (step 58), and the transferring signal is validated (step 59). , Serial data is transmitted (step 60), and the in-transmission signal is invalidated after the serial data is transmitted (step 61).

In the present invention, as shown in FIG.
For example, in a device in which four digital signal processing devices 11 to 14 are connected in a loop via signal lines DL12, DL23, DL34, and DL41, and serial data is transmitted and received between the digital signal processing devices 11 to 14, the transfer direction is reversed. A first control signal line CL1 for transmitting / receiving the reservation signal INH *, a second control signal line CL2 for transmitting / receiving the transfer direction signal SNDIR, and a third control signal line for transmitting / receiving the signal-in-transmission signal SNBSY *. CL3 is commonly connected to the digital signal processing devices 11 to 14, and each of the digital signal processing devices 11 to 14 switches the input end and the output end P1, P2 of the serial data according to the transfer direction signal SNDIR. A switching means, for example, an input / output switching circuit 20 as shown in FIG. 2, and a communication control means for performing the communication control are provided.

In the present invention, by adding the above-mentioned first to third control signal lines, the input / output switching means and the communication control means having a simple structure to the conventional structure, data collision is prevented even if the data transfer direction is reversed. That is, the data transfer direction is variable, and the data transfer time between a plurality of digital signal processing devices can be shortened.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

(1) First Embodiment FIG. 1 shows a connection between digital signal processing devices for transferring serial data between the digital signal processing devices 11-14.

Each of the digital signal processors 11 to 14 is provided with input / output ports P1 and P2 capable of switching between input and output. The input / output port P1 of the digital signal processing device 11 is connected to the input / output port P2 of the digital signal processing device 12 via the communication line DL12, and the input / output port P1 of the digital signal processing device 12 is connected to the digital signal via the communication line DL23. It is connected to the input / output port P2 of the processing device 13 and is connected to the input / output port P1 of the digital signal processing device 13.
Is connected to the input / output port P1 of the digital signal processing device 14 via the communication line DL34, and the digital signal processing device 1
The input / output port P2 of No. 4 is connected to the input / output port P2 of the digital signal processing device 11 via the communication line DL41. Also, an inhibit signal (transfer direction reverse rotation reservation signal)
A control signal line CL1 for transmitting / receiving INH *, a control signal line CL2 for transmitting / receiving a direction signal (transfer direction signal) SNDIR, and a control signal line for transmitting / receiving a busy signal (signal during signal transfer) SNBSY * CL3 and CL3 are commonly connected to the control input / output terminals of the respective digital signal processing devices 11-14. Here, * indicates negative logic.

Each of the digital signal processing devices 11 to 14 has a structure as shown in FIG.

That is, the input / output ports P1 and P2 are
Input port P of MPU 10 via input / output switching circuit 20
I and the output port PO. The input / output switching circuit 20 includes three-state buffer gates 21 to 24 and an inverter 25, which have the same configuration.
The input terminal of the buffer gate 21 is the input / output port P.
1 and the output terminal of the buffer gate 24, and the output terminal is connected to the input port PI of the MPU 10 and the output terminal of the buffer gate 23. The input terminal of the buffer gate 22 is the output port PO of the MPU 10.
And the input terminal of the buffer gate 24, and the output terminal is connected to the output port PO and the input terminal of the buffer gate 23. Such an input / output switching circuit 20 can usually be replaced by a programmable input / output port built in the MPU 10.

The direction input signal SNDIR is supplied to the control input terminals of the buffer gates 21 and 22 and the direction signal SNDIR inverted by the inverter 25 is supplied to the control input terminals of the buffer gates 23 and 24. When the direction signal SNDIR is set to the high level ('H'), the buffer gates 21 and 22 are in the through state, the buffer gates 23 and 24 are in the cutoff state, and the input / output port P1 becomes the input port, and the input / output port P2 becomes an output port. Further, when the direction signal SNDIR is set to a low level ('L'), the buffer gates 21 and 22 are cut off, the buffer gates 23 and 24 are set to the through state, and the input / output port P1 becomes an output port. The output port P2 becomes the input port. Therefore, the data transfer direction is clockwise when the direction signal SNDIR is at a high level in FIG.
Counterclockwise when DIR is low.

Data input terminals DI1 and DI of the MPU 10
2 and DI3 are connected to the control signal lines CL1, CL2 and CL3, respectively, and are connected to the data output terminal DO of the MPU 10.
1, DO2 and DO3 are connected to the data input terminals of the D flip-flops 31, 32 and 33, respectively. The data output terminals of the D flip-flops 31, 32 and 33 are control signal lines CL1, CL2 and CL, respectively.
Connected to 3. A control signal line (not shown) from the MPU 10 is connected to clock input terminals of the D flip-flops 31 to 33.

Although the D flip-flops 31 to 33 are arranged outside the MPU 10 in FIG. 2, the D flip-flops 31 to 33 are composed of bits of a register of a parallel input / output port of the MPU 10 and their contents are rewritten by a bit set / reset instruction. May be.

The outputs of the D flip-flops 31 to 33 are open collector outputs, and their collectors are connected to pull-up resistors to be wired OR. Therefore, when one or more of the digital signal processing devices 11 to 14 reset their D flip-flops 31, the control signal line CL1 becomes low level, and the digital signal processing devices 11 to 11
When one or more of 14 sets the D flip-flop 32, the control signal line CL2 becomes low level, and when one or more of the digital signal processing devices 11 to 14 resets the D flip-flop 33, the control signal line CL3 becomes low level. Becomes

Serial data communication control between the digital signal processing devices 11 to 14 is performed by the software configuration of the MPU 10. FIG. 3 is a flowchart showing a data transmission procedure. This data transmission procedure is the same for each of the digital signal processing devices 11-14. Less than,
Numerical values in parentheses indicate step identification numbers in FIG.

(50) The direction signal SNDIR is read from the data input terminal DI2.

(51) If the data transfer direction to be transmitted is the reverse direction of the current data transfer direction, the processes of steps 52 to 57 are performed, and if it is the same direction, the process proceeds to step 57.

(52) Read the inhibit signal INH * from the data input terminal DI1.

(53) If the inhibit signal INH * is low level (valid), the process returns to step 51.

(54) If the inhibit signal INH * is high level (invalid), the D flip-flop 31 is reset to set the inhibit signal INH * to low level.

(55) Read the busy signal SNBSY * from the data input terminal DI3.

(56) If the busy signal SNBSY * is low level (valid), the process returns to step 55.

(57) If the busy signal SNBSY * is high level (invalid), the transfer direction is set. This is S
The D flip-flop 32 may be reset only when NDIR is set to low level (valid).

(58) The D flip-flop 31 is set to set the inhibit signal INH * to high level.

(59) The busy signal SNBSY * is set to low level.

(60) Serial data output port PO
Output from and transfer.

(60) When the serial data transfer is completed, the D flip-flop 33 is set to set the busy signal S.
NBSY * goes high and D flip-flop 32 is set to bring SNDIR high.

The procedure for receiving serial data is the same as the conventional one, and the description thereof is omitted. In this way, data transfer between the digital signal processing devices 11 to 14 is performed.

For example, as shown in FIG. 4, when the direction signal SNDIR is at a high level and data is being transferred from the digital signal processor 13 to the digital signal processor 12, the digital signal processor 14 sends the data to the digital signal processor 11. When transferring, the following processing is performed. That is, the digital signal processing device 14 sets the inhibit signal INH * to the low level, and then when the busy signal SNBSY * goes to the high level, sets the direction signal SNDIR to the low level and sets the inhibit signal INH.
The * is set to the high level and the busy signal SNBSY * is set to the low level to transmit the serial data to the digital signal processing device 11. Thereafter, the busy signal SNBSY * is set to high level and the direction signal SNDIR is set to high level.

During data transfer from the digital signal processing device 13 to the digital signal processing device 12, another data transfer in this transfer direction, for example, data transfer from the digital signal processing device 14 to the digital signal processing device 13 is performed. It is possible. Similarly, during data transfer from the digital signal processing device 14 to the digital signal processing device 11, another data transfer in this transfer direction, for example, the digital signal processing device 1
Data can be transferred from the digital signal processor 13 to the digital signal processor 13.

In the present embodiment, the digital signal processing device 11
2 to the input / output switching circuit 2 as shown in FIG.
0, D flip-flops 31 to 33 (these are usually MP
U10 itself), and the control signal lines CL1 to CL3 are connected to the digital signal processing device 1 as shown in FIG.
1 to 14 are commonly connected to the digital signal processing device 11 to 11.
With a simple configuration in which the software of steps 51 to 57 as shown in FIG. 3 is added to each of the fourteen, the data transfer direction can be made variable and the data transfer time can be shortened.

(2) Second Embodiment FIG. 5 shows a more specific circuit configuration of the device shown in FIG.

In this serial data communication apparatus, a DSP (digital signal processor) 10A of model MB86232 is used as the MPU 10 shown in FIG. 2, and the buffer gates 24 and 22 shown in FIG. 2 are constituted by a three-state buffer gate 26 of model 74F244. The buffer gates 23 and 21 shown in FIG.
The three-state type buffer gate 27 is used. Numbers 1 to 19 in the figure are buffer gates 26 and 2.
7 is the actual pin number.

The DSP 10A has a serial input port i and a serial output port i (i = 0, 1),
In this example, the serial input port 1 and the serial output port 0 are for forward data transfer, and the serial input port 0 and the serial output port 1 are for reverse data transfer.

An output signal from the serial output port i is: SOi: serial output data SYOi: a data output start synchronizing signal from the serial output port i SOCi: a clock for reading data from the serial output port i 20 MHz SOBi: serial output port i Output side busy signal to 4 When output is at high level, data output is prohibited.

The input signal to the serial input port i is: SINi: serial input data SYIi: synchronous signal for starting data writing to the serial input port i SICi: clock for writing data to the serial input port i SIBi: serial input port i Input register SIi
The busy signal of 4 is in the state of not accepting input data when high level.

The data input terminals of the D flip-flops 31 to 33 are connected to the data input / output terminals D1 to D3 of the parallel input / output port, and the data output terminals are controlled via the open collector output buffer gates 34 to 36, respectively. It is connected to the signal lines CL1 to CL3. The clock input terminals of the D flip-flops 31 to 33 have DS
A control signal line (not shown) from P10A is connected.

The D flip-flops 31 to 33 are arranged outside the DSP 10A in FIG.
It consists of the register bit of the parallel input / output port of
The contents may be rewritten by a bit set / reset instruction.

The control signal line CL1 is connected to the flag input terminal F1 of the DSP 10A via the buffer gate 37,
The control signal line CL2 is connected via the buffer gate 38 to the control input terminal 2G of the buffer gate 26 and the buffer gate 27.
Control input terminal 1G, input terminal of inverter 25 and D
The parallel input / output port data line D0 of the SP 10A is connected, and the control signal line CL3 is connected via the buffer gate 39 to the flag input terminal F0 of the DSP 10A. The output terminal of the inverter 25 is a buffer gate 26
Is connected to the control input terminal 1G of the above and the control input terminal 2G of the buffer gate 27.

When the direction signal SNDIR is set to the high level, the data read clock SOC0 and the data output start synchronizing signal SYO output from the DSP 10A.
0, the input register busy signal SIB1 and the serial output data SO0 are signals SIOCK1, TRG1, and
SB1 and SD1 are taken out from the input / output port P1 and the signals SIOCK2, T are output from the input / output port P2.
RG2, SB2 and SD2 are a data write clock SIC1 and a data write start synchronization signal SY, respectively.
I1, the output side busy signal SOB0 and the serial input data SIN1 are input to the DSP 10A.

When the direction signal SNDIR is set to the low level, the data read clock SOC1 and the data output start synchronizing signal S output from the DSP 10A.
YO1, input register busy signal SIB0 and serial output data SO1 are signals SIOCK2 and TRG, respectively.
2, SB2 and SD2 are taken out from the input / output port P2, and the signal SIOCK from the input / output port P1.
1, TRG1, SB1 and SD1 are input to the DSP 10A as a data write clock SIC0, a data write start synchronization signal SYI0, an output busy signal SOB1 and serial input data SIN0, respectively.

The other points are the same as those of the first embodiment.

[0048]

As described above, in the serial data communication method and apparatus according to the present invention, the above-mentioned first to third control signal lines, the input / output switching means and the communication control means having a simple structure are added to the conventional structure. As a result, the data transfer direction becomes variable, and the data transfer time between a plurality of digital signal processing devices can be shortened, which contributes to speeding up of the high-performance robot control by the multiprocessor system. large.

[Brief description of drawings]

FIG. 1 is a connection diagram between digital signal processing devices according to a first embodiment of the present invention.

FIG. 2 is a communication-related configuration diagram of the digital signal processing device of FIG.

FIG. 3 is a flowchart showing a data transmission procedure.

FIG. 4 is a time chart of data transmission / reception.

FIG. 5 is a communication-related configuration diagram of a digital signal processing device according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a problem of the conventional technique.

[Explanation of symbols]

 10 MPU 10A DSP 11-14 Digital signal processing device 20 Input / output switching circuit 21-24, 26, 27 Buffer gate 31-33 D flip-flop 34-39 Buffer gate PI input port PO output port P1, P2 Input / output port DI1- DI3 data input terminal DO1 to DO3 data output terminal CL1, CL2, CL3 control signal line F0, F1 flag input terminal INH * inhibit signal SNDIR direction signal SNBSY * busy signal

Claims (2)

[Claims] 1. A plurality of digital signal processing devices (11 to 1)
4) is a signal line (DL12, DL23, DL34, DL4)
In the serial data communication method in which the digital signal processing devices are connected in a loop via 1) to transmit and receive serial data between the digital signal processing devices, each digital signal processing device inputs serial data according to a transfer direction signal (SNDIR). When the end and the output end (P1, P2) are switched and the transfer direction is reversed and serial data is transmitted, the transfer direction reverse rotation reservation signal (INH *) by the other digital signal processing device becomes invalid. The transfer direction reverse rotation reservation signal is enabled when the digital signal processing device is in the other direction, the transfer direction signal is inverted when the signal being transferred (SNBSY *) by the other digital signal processing device is invalid, and the transfer direction reverse rotation reservation signal is invalidated. In addition, it is possible to enable the signal during transfer, transmit serial data, and disable the signal during transfer after transmitting the serial data (50 to 61). Serial data communication method for the butterflies. 2. A plurality of digital signal processing devices (11 to 1)
4) is a signal line (DL12, DL23, DL34, DL4)
In a serial data communication device connected in a loop via 1) for transmitting and receiving serial data between the digital signal processing devices, a first control signal line (CL1) for transmitting and receiving a transfer direction reverse rotation reservation signal (INH *) ) And the transfer direction signal (SNDI
The second control signal line (CL2) for transmitting and receiving R) and the third control signal line (CL3) for transmitting and receiving the signal during signal transfer (SNBSY *) are commonly connected to the digital signal processing device. Then, each of the digital signal processing devices switches input / output switching means (2) for switching between an input end and an output end (P1, P2) of serial data according to the transfer direction signal.
0), when transmitting the serial data with the transfer direction reversed, the transfer direction reverse reservation signal is validated when the transfer direction reverse reservation signal by the other digital signal processing device is invalid, When the signal being transferred by another digital signal processing device is invalid, the transfer direction signal is inverted, the transfer direction inversion reservation signal is disabled, and the transferring signal is enabled, and the serial signal is transmitted. A serial data communication device, comprising: a communication control unit (10, 50 to 61) that transmits data and invalidates a signal during transfer after transmitting the serial data.