JPH0566571A - Baking method for resist - Google Patents
Baking method for resistInfo
- Publication number
- JPH0566571A JPH0566571A JP22757791A JP22757791A JPH0566571A JP H0566571 A JPH0566571 A JP H0566571A JP 22757791 A JP22757791 A JP 22757791A JP 22757791 A JP22757791 A JP 22757791A JP H0566571 A JPH0566571 A JP H0566571A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- substrate
- hot plate
- baking
- hot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はレジストのベーキング方
法, 特に多層レジストのベーキング方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resist baking method, and more particularly to a multilayer resist baking method.
【0002】半導体デバイスの微細化に伴い, フォトリ
ソグラフィ工程で基板上の段差の大きい部分でのパター
ニングが困難となってきている。そこで,段差を緩和
(多層レジスト採用の目的の一つ)させるために多層レ
ジストが用いられているが, 下層レジストとスピンオン
グラス(SOG) からなる中間層のキュアベーク時に, 基板
温度が急激に上昇すると下層レジストが破裂するため,
ベーキング方法の改善が求められていた。With the miniaturization of semiconductor devices, it has become difficult to perform patterning in a portion having a large step on a substrate in a photolithography process. Therefore, a multi-layer resist is used to alleviate the step (one of the purposes of adopting the multi-layer resist). Because the lower layer resist bursts,
There was a need for improved baking methods.
【0003】[0003]
【従来の技術】図3は従来例によるベーキングの説明図
である。図において,1,2,3はホットプレートで,
それぞれ温度をa℃,b℃,c℃(a<b<c)に設定
し,各ホットプレート上の滞留時間をt秒とする。2. Description of the Related Art FIG. 3 is an explanatory view of baking according to a conventional example. In the figure, 1, 2, 3 are hot plates,
The temperatures are set to a ° C., b ° C., and c ° C. (a <b <c), and the residence time on each hot plate is t seconds.
【0004】このように,温度設定を変えた複数のホッ
トプレート上を基板は搬送装置により移動してゆくこと
により,基板温度を段階的に上げる工夫がなされてい
る。In this way, the substrate is moved on the plurality of hot plates whose temperature settings are changed by the transfer device so that the substrate temperature is raised stepwise.
【0005】[0005]
【発明が解決しようとする課題】従来例では,複数のホ
ットプレート上を基板が通過するため,ゴミがつきやす
くなる。また,多段式ベーキングであるため,搬送ロボ
ットに対する熱影響が増し,搬送中の室温状態の基板に
対して熱が伝わるといった問題が生じていた。In the conventional example, since the substrate passes over a plurality of hot plates, dust is easily attached. Further, since the baking is performed in multiple stages, there is a problem in that the heat influence on the transfer robot is increased and the heat is transferred to the substrate in the room temperature state during the transfer.
【0006】従って,基板は汚染を受けやすく,基板温
度の制御ができないため塗布膜厚分布の悪化という問題
が起こることになる。本発明は基板の汚染および基板搬
送系への熱影響の抑制とを目的とする。Therefore, the substrate is apt to be contaminated and the temperature of the substrate cannot be controlled, which causes a problem that the coating film thickness distribution is deteriorated. An object of the present invention is to suppress contamination of a substrate and thermal influence on a substrate transfer system.
【0007】[0007]
【課題を解決するための手段】上記課題の解決は, 1)レジストを塗布した基板をホットプレート表面に平
行にかつ一定距離離して該ホットプレート上に載せ,該
一定距離の間隔を調節して該基板の昇温時間を所定の値
に設定して,基板当たり1枚のホットプレートで該基板
の加熱を行うレジストのベーキング方法,あるいは 2)前記レジストが,多層レジストの下層レジストとス
ピンオングラス(SOG) からなる中間層である前記1)記
載のレジストのベーキング方法,あるいは 3)前記ホットプレートを複数個用いて,基板の並行加
熱を行う前記1)または 2)記載のレジストのベーキング方法により達成され
る。To solve the above-mentioned problems, 1) a substrate coated with a resist is placed on the hot plate parallel to the surface of the hot plate at a certain distance, and the interval of the certain distance is adjusted. The resist is baked by setting the temperature rise time of the substrate to a predetermined value and heating the substrate with one hot plate per substrate, or 2) the resist is a lower layer resist of a multilayer resist and a spin-on-glass ( SOG), which is an intermediate layer, which is the resist baking method described in 1) above, or 3) The baking method of resist described in 1) or 2) above in which the substrates are heated in parallel using a plurality of hot plates. To be done.
【0008】[0008]
【作用】図1 (A)〜(D) は本発明の原理説明図である。
図1(A) は通常の近接式ホットプレートで,1はホット
プレート,4は基板をホットプレートに近接して載せる
ためのプロキシミティギャップピンである。1 (A) to 1 (D) are explanatory views of the principle of the present invention.
FIG. 1 (A) shows a normal proximity hot plate, 1 is a hot plate, and 4 is a proximity gap pin for mounting a substrate close to the hot plate.
【0009】この場合,基板とホットプレート間が近接
しているため,基板温度の時間経過は図1(B) のように
急激に立ち上がる。図1(C) において,プロキシミティ
ギャップピンの高さを増すと,基板温度の時間経過は図
1(D) のようになだらかにに立ち上がる。In this case, since the substrate and the hot plate are close to each other, the substrate temperature rises rapidly as shown in FIG. 1 (B). When the height of the proximity gap pin is increased in Fig. 1 (C), the substrate temperature rises gradually as shown in Fig. 1 (D).
【0010】本発明はこの事実を利用して,基板温度の
立ち上がり特性を所望の立ち上がり特性に合わせてプロ
キシミティギャップピンの高さを調整することにより,
1個のホットプレートでベーキングするようにしたもの
である。The present invention takes advantage of this fact by adjusting the height of the proximity gap pin in accordance with the desired rising characteristic of the substrate temperature,
Baking is done with one hot plate.
【0011】[0011]
【実施例】図2(A),(B) は本発明の一実施例の説明図で
ある。図2(A) において,ホットプレート1,2,3を
並行処理し,各ホットプレート上の基板の滞留時間を3
t秒(例えばt=60秒)とする。EXAMPLE FIGS. 2A and 2B are explanatory views of an example of the present invention. In Fig. 2 (A), hot plates 1, 2 and 3 were processed in parallel, and the residence time of the substrate on each hot plate was set to 3
It is t seconds (for example, t = 60 seconds).
【0012】この場合の,各ホットプレート上の基板温
度の時間経過を図2(A) に示す。室温から2t秒後に最
終温度c℃(例えば 270℃)に達するようにプロキシミ
ティギャップピン2の高さを調節し,最終温度での加熱
をt秒続けた後基板を取り出す。FIG. 2A shows the time course of the substrate temperature on each hot plate in this case. The height of the proximity gap pin 2 is adjusted so as to reach the final temperature c ° C. (for example, 270 ° C.) 2 t seconds after the room temperature, heating at the final temperature is continued for t seconds, and then the substrate is taken out.
【0013】この場合,スループット低下の問題はホッ
トプレート1,2,3を並行処理することにより解決で
きる。このように実施例ではホットプレート1枚/基板
で処理できる。In this case, the problem of reduced throughput can be solved by processing the hot plates 1, 2, 3 in parallel. Thus, in the embodiment, one hot plate / substrate can be processed.
【0014】[0014]
【発明の効果】本発明ではホットプレート1枚/基板で
処理できるため,基板上へのゴミの付着および基板搬送
系への熱影響が抑制され,塗布膜厚分布の向上に寄与す
ることができた。According to the present invention, since one hot plate / substrate can be used for processing, adhesion of dust on the substrate and thermal influence on the substrate transfer system can be suppressed, which contributes to improvement of the coating film thickness distribution. It was
【図1】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図2】 本発明の一実施例の説明図FIG. 2 is an explanatory diagram of an embodiment of the present invention.
【図3】 従来例によるベーキングの説明図FIG. 3 is an explanatory diagram of baking according to a conventional example.
1,2,3 ホットプレート 4 基板をホットプレートに近接して載せるプロキシミ
ティギャップピン1,2,3 Hot plate 4 Proximity gap pin for placing the substrate close to the hot plate
Claims (3)
ト表面に平行にかつ一定距離離して該ホットプレート上
に載せ,該一定距離の間隔を調節して該基板の昇温時間
を所定の値に設定して,基板当たり1枚のホットプレー
トで該基板の加熱を行うことを特徴とするレジストのベ
ーキング方法。1. A substrate coated with a resist is placed on the hot plate parallel to the surface of the hot plate and at a fixed distance, and the interval of the fixed distance is adjusted to set the temperature rising time of the substrate to a predetermined value. Then, the method for baking a resist is characterized in that the substrate is heated by one hot plate per substrate.
ジストとスピンオングラス(SOG) からなる中間層である
ことを特徴とする請求項1記載のレジストのベーキング
方法。2. The resist baking method according to claim 1, wherein the resist is an underlayer resist of a multilayer resist and an intermediate layer made of spin-on-glass (SOG).
板の並行加熱を行うこと特徴とする請求項1または2記
載のレジストのベーキング方法。3. The method for baking a resist according to claim 1, wherein the substrate is heated in parallel by using a plurality of the hot plates.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22757791A JPH0566571A (en) | 1991-09-09 | 1991-09-09 | Baking method for resist |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22757791A JPH0566571A (en) | 1991-09-09 | 1991-09-09 | Baking method for resist |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0566571A true JPH0566571A (en) | 1993-03-19 |
Family
ID=16863099
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22757791A Withdrawn JPH0566571A (en) | 1991-09-09 | 1991-09-09 | Baking method for resist |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0566571A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100487699B1 (en) * | 1999-10-25 | 2005-05-03 | 엔이씨 엘씨디 테크놀로지스, 엘티디. | Resist film baking apparatus and resist film baking method |
KR100689920B1 (en) * | 2004-01-15 | 2007-03-09 | 가부시끼가이샤 도시바 | Film forming method and substrate processing device |
JP2007214367A (en) * | 2006-02-09 | 2007-08-23 | Tokyo Electron Ltd | Heat treatment apparatus, heat treatment method and program |
WO2015012123A1 (en) * | 2013-07-26 | 2015-01-29 | 日東電工株式会社 | Production method for sheet, and sheet production apparatus |
-
1991
- 1991-09-09 JP JP22757791A patent/JPH0566571A/en not_active Withdrawn
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100487699B1 (en) * | 1999-10-25 | 2005-05-03 | 엔이씨 엘씨디 테크놀로지스, 엘티디. | Resist film baking apparatus and resist film baking method |
KR100689920B1 (en) * | 2004-01-15 | 2007-03-09 | 가부시끼가이샤 도시바 | Film forming method and substrate processing device |
JP2007214367A (en) * | 2006-02-09 | 2007-08-23 | Tokyo Electron Ltd | Heat treatment apparatus, heat treatment method and program |
WO2015012123A1 (en) * | 2013-07-26 | 2015-01-29 | 日東電工株式会社 | Production method for sheet, and sheet production apparatus |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981203 |