JPH11274030A - Method and device for resist processing, and method for coating resist - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control film-thickness distribution and dimension distribution of a resist film in the surface of a semiconductor. SOLUTION: A resist coating part which coats a resist on a semiconductor wafer 1, a development part for developing, a wafer temperature adjusting part for controlling the temperature of the semiconductor wafer 1, a bake process part for baking the semiconductor wafer l, support plates 3 which, provided at the wafer temperature adjusting part and the bake process part, support the semiconductor wafer 1, a plurality of temperature control elements 4, which provided in each concentric region of the support plate 3, heating or cooling respective regions, and a temperature control part 5 which controls heating or cooling of the temperature control element 4 for each region, are provided. When the semiconductor wafer 1 is processed for resist at the resist coating part and the development part, the temperature of the semiconductor wafer 1 is controlled by each region before and after the resist process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a processing substrate and a semiconductor wafer, and more particularly, to a resist processing technique for controlling the thickness of a resist film in a resist processing step.

[0002]

2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

In a resist processing apparatus used in a resist processing step of a semiconductor manufacturing process, a resist coating section (resist processing section) for applying a resist and temperature control such as a baking process or a cooling process for a semiconductor wafer are performed. A wafer temperature processing section and a developing section (resist processing section) for developing a resist film on the semiconductor wafer after exposure are provided (however, there is an apparatus without a resist coating section or a developing section).

In such a resist processing apparatus, when the baking temperature and time after resist application and before development are changed, or when the temperature of the resist solution or the developing solution is changed, the change in the film thickness and dimensions of the resist film is prevented. Therefore, technical development is being conducted in a direction to suppress a temperature change in each processing unit.

The resist processing apparatus is described in, for example, “Industrial Research Institute Co., Ltd., published on November 25, 1994,“ Ultra LSI Manufacturing and Testing Equipment Guidebook <1995.
Year Edition>, Electronic Materials Separate Volume (1994 Separate Volume) ", 77-8
It is described on page 3.

[0006]

However, the resist processing apparatus in the above-described technique is designed to suppress a temperature change in all processing units (the resist processing unit and the wafer temperature processing unit).

As a result, when a semiconductor wafer is carried into a coating or developing processing section, even if a temperature difference occurs in the surface of the semiconductor wafer, the resist processing apparatus takes this surface into consideration in terms of the structure or arrangement of each processing section. The problem is that it is not possible to correct the temperature difference in the inside.

Even when there is no temperature difference, the difference in the evaporation rate of the solvent in the resist solution or the offset in the in-plane dimension of the semiconductor wafer caused by the etching in the next step is canceled out. There is a problem that even if an attempt is made to adjust the film thickness or the resist dimensions of the resist film by providing a temperature difference within an arbitrary range in the plane of the semiconductor wafer, this cannot be achieved.

It is an object of the present invention to provide a resist processing method and apparatus, and a resist coating method, which make it possible to control the thickness distribution and the size distribution of a resist film in the plane of a semiconductor wafer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the resist processing method of the present invention comprises:
Placing the processing substrate on a substrate supporting member installed in a processing chamber, and controlling the temperature of the substrate supporting member for each of a plurality of regions, thereby processing the plurality of processing substrates supported by the substrate supporting member. Controlling the temperature of each of the regions and performing a resist process on the processing substrate, wherein the temperature of the processing substrate is controlled before or after the resist processing.

Thus, a temperature difference can be provided in the plane of the processing substrate. As a result, when a resist processing is performed on the processing substrate, the thickness distribution of the resist film and the size distribution of the resist dimensions are controlled. it can.

Further, in the resist processing method of the present invention, the step of mounting a semiconductor wafer on a substrate supporting member provided in a processing chamber and the control of the temperature of the substrate supporting member for each of a plurality of regions are performed. A step of controlling the temperature of the semiconductor wafer supported by the substrate support member for each of the plurality of regions, and a step of performing a resist process on the semiconductor wafer, wherein at least one of before and after the resist process This is for controlling the temperature of the semiconductor wafer.

Thus, the temperature of the semiconductor wafer can be controlled for each of a plurality of regions, so that a temperature difference can be provided in the plane of the semiconductor wafer.

Therefore, when a resist is applied (resist processing) to a semiconductor wafer, the thickness distribution of the resist film can be controlled.

Further, the resist processing apparatus of the present invention is provided with a resist processing section for performing a resist processing of a semiconductor wafer, a wafer temperature processing section for controlling a temperature of the semiconductor wafer, and installed in the wafer temperature processing section; A substrate support member for supporting a semiconductor wafer, a plurality of temperature control elements provided for each of a plurality of regions of the substrate support member, and heating or cooling the respective regions, and performing the heating or cooling of the temperature control element. A temperature control unit for separately controlling each of the plurality of regions, wherein the resist processing unit performs the resist processing on the semiconductor wafer, and the wafer temperature processing unit before and / or after the resist processing. The temperature of the semiconductor wafer can be controlled for each of the plurality of regions.

Further, in the resist coating method of the present invention, the step of mounting a semiconductor wafer on a substrate supporting member provided in a processing chamber and the control of the temperature of the substrate supporting member for each of a plurality of regions are performed. A step of controlling the temperature of the semiconductor wafer supported by the substrate support member for each of the plurality of regions, and a step of applying a resist to the semiconductor wafer, at least one of before and after the resist application This is for controlling the temperature of the semiconductor wafer.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic diagram showing an embodiment of the structure of a resist processing apparatus according to the present invention, and FIG. 2 is a structure of a substrate support member provided in a wafer temperature processing section of the resist processing apparatus shown in FIG. 4A is a cross-sectional view, FIG. 3B is a bottom view, FIG. 3 is a flowchart showing an example of an embodiment of a resist coating procedure in the resist processing method of the present invention, and FIG. FIG. 5 is a flowchart illustrating an example of an embodiment of a procedure of a developing process in the resist processing method of the present invention. FIG. 5 is a cross-sectional view illustrating an example of an embodiment of a pattern forming process on a semiconductor wafer using the resist processing apparatus of the present invention. 6 to 9 are conceptual diagrams of a film distribution showing an example of a distribution state of the thickness and the resist dimension of the resist film formed by the resist processing apparatus of the present invention.

The resist processing apparatus according to the present embodiment shown in FIG. 1 performs resist processing such as resist coating, developing and baking on a processing substrate in a resist processing step of a semiconductor manufacturing process.

Therefore, the processing substrate described in the present embodiment is the semiconductor wafer 1.

The configuration of the resist processing apparatus according to the present embodiment will be described with reference to FIGS. 1 and 2. A resist coating section 6, which is a resist processing section for performing resist coating (resist processing) on the semiconductor wafer 1, and a semiconductor A developing unit 7 that is a resist processing unit that develops (resist processing) the resist film 2 formed on the wafer 1 after performing an exposure process, and a wafer temperature control unit 8 that is a wafer temperature processing unit that controls the temperature of the semiconductor wafer 1. A bake processing unit 9 that is a wafer temperature processing unit that performs a bake process on the semiconductor wafer 1 and a wafer temperature control unit 8 and a bake processing unit 9 that are the wafer temperature processing units and support the semiconductor wafer 1. A support plate 3 (substrate support member); and a plurality of temperature control elements 4 provided for each of a plurality of regions of the support plate 3 and heating or cooling each region. Temperature control unit 5 for controlling separately each of the plurality of regions of heating or cooling of the temperature control element 4
A resist application pretreatment section 10 for applying an adhesion enhancer before applying the resist, and a transfer arm 11 for holding the semiconductor wafer 1 and carrying the semiconductor wafer 1 into and out of each of the processing sections. When the wafer 1 is subjected to the resist processing, the temperature of the semiconductor wafer 1 can be controlled for each of the plurality of regions by the wafer temperature processing unit before and / or after the resist processing. .

As shown in FIG. 2, the support plate 3 in the resist processing apparatus of the present embodiment has a temperature control element 4 for each of a plurality of concentric regions with respect to the center of the semiconductor wafer 1 with respect to the center. Is installed.

That is, on the back surface 3b of the support plate 3, the back surface 1b of the semiconductor wafer 1 is divided into a plurality of concentric regions, and the temperature control elements 4 are provided at respective locations corresponding to the divided regions. ing.

This is because, when the resist film 2 is formed on the semiconductor wafer 1, the film thickness distribution and the resist size 2a (FIG. 5)
In many cases, the distribution of the semiconductor wafer 1 is concentrically distributed with respect to the center of the semiconductor wafer 1, and accordingly, the temperature of the semiconductor wafer 1 is controlled for each of the concentrically divided regions with respect to the center.

Thus, when heating or cooling the semiconductor wafer 1 on the support plate 3, the semiconductor wafer 1 is subjected to temperature control for each of the plurality of concentric regions in accordance with the location of the plurality of temperature control elements 4. It can be performed.

On the mounting surface 3a of the support plate 3,
3 or 4 small projections 3c supporting the semiconductor wafer 1
Are provided at about the same point, and by the small projections 3c,
Since only a very small area of the back surface 1b of the semiconductor wafer 1 is supported, the semiconductor wafer 1 can be supported by the support plate 3 in a substantially non-contact manner.

Further, the surface of the support plate 3 is desirably coated with a fluororesin to prevent foreign substances (especially metallic foreign substances) from adhering when coming into contact with the semiconductor wafer 1. Plate 3
Another supporting member made of the fluororesin or the like is provided on the front surface side, and the semiconductor wafer 1 may be supported on the mounting surface 3a of the supporting member.

Here, the temperature control element 4 provided in the resist processing apparatus of the present embodiment is an element that can be heated or cooled, for example, a Peltier element.

Each of the temperature control elements 4 is electrically connected to a temperature control unit 5, whereby the temperature control unit 5 receives signals from a temperature sensor (not shown) attached to the support plate 3. It manages the temperature of each temperature control element 4 based on this and controls the temperature freely.

Semiconductor wafer 1 in wafer temperature control section 8 and bake processing section 9 of the resist processing apparatus of the present embodiment
In the temperature control described above, an arbitrary region in the plane of the semiconductor wafer 1
It is possible to cause a temperature difference of about 0.1 to 20 ° C.

In the wafer temperature control section 8 and the bake processing section 9, the support plate 3 has a cover 1 around its periphery.
2 and the inside of the cover 12 becomes a processing chamber 13 for the semiconductor wafer 1.

The support plate 3 installed in the wafer temperature control section 8 of this embodiment is a cooling plate, and the semiconductor wafer 1 is provided on the resist coating section 6 or the developing section 7.
Is often used for controlling (cooling) the temperature at the time of carrying in to a target temperature near room temperature.

Therefore, the temperature control element 4 provided on the support plate 3 of the wafer temperature control section 8 of the present embodiment is a heating element.

The support plate 3 installed in the baking section 9 of the present embodiment is a hot plate, and is used for baking before and after resist application and baking before development. This is used to control the temperature of the device to a predetermined set temperature.

Therefore, the temperature control element 4 provided on the support plate 3 of the bake processing unit 9 of the present embodiment is a heating element.

Further, the resist coating pre-processing section 10 is provided with an HM
Also called a DS (hexamethylene disilazane) unit, in order to improve the adhesion between the resist film 2 and the semiconductor wafer 1 (or a predetermined film formed on the semiconductor wafer 1), the main surface 1a of the semiconductor wafer 1 (or A temperature control element 4 divided into a plurality of regions is provided on the substrate supporting member of the resist coating pretreatment section 10 of the present embodiment. However, a heating element for heating the entire substrate supporting member is provided.

However, it is needless to say that the same processing chamber 13 provided in the wafer temperature control section 8 may be provided in the resist coating pre-processing section 10 of the present embodiment.

The resist coating unit 6 is provided with a spinner, a nozzle, and the like (not shown) so that various coating conditions (for example, a resist temperature before coating, a type of a resist solution, a coating time, and a rotation speed of the spinner, etc.) are set. The semiconductor wafer 1 is placed on the spinner based on the above, and a predetermined resist solution is applied thereto from the nozzle to form a resist film 2 having a predetermined thickness on the semiconductor wafer 1.

Further, the developing section 7 includes a resist coating section 6
A spinner and a nozzle, not shown, are installed in the same way as
The semiconductor wafer 1 is placed on the spinner based on various developing conditions (for example, the temperature of the developing solution before development, the type of the developing solution, the developing time, the rotation speed of the spinner, and the like), and a predetermined number of nozzles are set therefrom by the nozzle. The desired development is performed by applying a developer.

Next, the resist processing method of the present embodiment will be described.

In this embodiment, as an example, 1
Taking a 6M DRAM (Dynamic Random Access Memory) as an example, a description will be given of an example of a resist process performed when manufacturing the DRAM along a basic pattern forming process as shown in FIG.

However, the resist processing is performed at 16M D
The present invention is not limited to the case of manufacturing a RAM.

First, as shown in FIG. 5A, an aluminum film 21 for forming a wiring is formed on the main surface 1a of a semiconductor wafer 1 as a base processing substrate by vapor deposition or the like.

Subsequently, a resist coating, which is one of the resist processes, is performed.

In this embodiment, the semiconductor wafer 1
As an example, a case in which a positive resist film 2 having a thickness of 1 μm is formed on the aluminum film 21 will be described (however, a negative resist film 2 may be formed).

At this time, first, the aluminum film 21 is placed in the pre-resist coating section 10 of the resist processing apparatus shown in FIG.
The semiconductor wafer 1 on which is formed is carried in, and as shown in step S1 in FIG. 3, HMDS processing which is a pre-processing of resist coating is performed.

That is, the resist film 2 and the semiconductor wafer 1
An adhesion enhancer is applied to the aluminum film 21 of the semiconductor wafer 1 in order to improve the adhesion with the upper aluminum film 21.

Thereafter, the semiconductor wafer 1 is taken out of the resist coating pre-processing section 10 by the transfer arm 11 and then loaded into the wafer temperature control section 8, where the semiconductor wafer 1 is loaded as shown in step S2 of FIG. Then, a pre-application temperature control process is performed.

The wafer temperature control section 8 is provided with a processing chamber 13 as shown in FIG.

Here, the purpose of the temperature control processing of the semiconductor wafer 1 performed by the wafer temperature control section 8 will be described.

First, in the resist coating in step S3 shown in FIG. 3, the temperature of the support plate 3 is reduced to the mounting surface 3a.
When the resist film 2 is stretched, the resist film 2 obtains heat from the semiconductor wafer 1 and is stretched toward the outer peripheral portion of the semiconductor wafer 1 when the resist film 2 is stretched. The temperature distribution becomes higher.

In this case, the resist film 2 has a film thickness distribution as shown in FIG. That is, the outer peripheral portion is thicker than the central portion.

Therefore, in order to prevent this, the temperature of the outer peripheral portion of the semiconductor wafer 1 is set lower than that of the central portion in advance by using the support plate 3 shown in FIG.

As a result, the increase in the viscosity of the outer peripheral portion of the semiconductor wafer 1 can be suppressed, and as a result, a uniform film thickness distribution as shown in FIG. 7 can be obtained.

Conversely, even when the viscosity does not change when the resist film 2 is stretched and the film thickness distribution as shown in FIG. By setting the temperature of the outer peripheral portion of the semiconductor wafer 1 higher than that of the central portion in advance by using the support plate 3 shown in the drawing, the viscosity can be gradually increased, and the uniform film thickness distribution as shown in FIG. Obtainable.

Further, even when the change in viscosity and the change in centrifugal force are mixed and the film thickness distribution shown in FIG. 9 is obtained,
By optimizing the temperature of the plurality of temperature control elements 4,
A uniform film thickness distribution as shown in FIG. 7 can be obtained.

As a result, several types of resist solutions using solvents having different volatilization rates can be used while controlling the film thickness with high accuracy in the same wafer temperature control section 8 (resist processing section). .

Next, a specific method for adjusting the temperature of the semiconductor wafer 1 in the wafer temperature adjusting section 8 will be described.

First, the semiconductor wafer 1 having the aluminum film 21 formed on the main surface 1a is carried into the wafer temperature control section 8,
The semiconductor wafer 1 is placed on the support plate 3 (substrate support member) installed in the processing chamber 13 of the wafer temperature control unit 8.

After that, the temperature of the support plate 3 is controlled for each of a plurality of regions concentrically divided with respect to the center of the support plate 3, whereby the semiconductor wafer 1 supported by the support plate 3 is controlled with respect to the center. Temperature control is performed for each of a plurality of concentrically divided regions.

Here, the temperature of temperature control element 4 provided at a location corresponding to the outer periphery of semiconductor wafer 1 is lower than the temperature of temperature control element 4 provided at a location corresponding to the center of semiconductor wafer 1. As a result, the temperature of the semiconductor wafer 1 is controlled such that the temperature of the outer peripheral portion is lower by about 1 to 2 ° C. than the central portion of the semiconductor wafer 1.

The atmosphere in the processing chamber 13 is, for example,
In addition to the N ₂ atmosphere, the temperature control here is
The support plate 3 is a cooling plate, and is mainly for cooling the semiconductor wafer 1.

Thereafter, the semiconductor wafer 1 is taken out of the wafer temperature control section 8 by the transfer arm 11, and subsequently, the semiconductor wafer 1 is loaded into the resist coating section 6 (resist processing section). A resist coating (resist process) as shown is performed.

At this time, since the temperature of the semiconductor wafer 1 is controlled so that the temperature of the outer peripheral portion is lower than that of the central portion by about 1 to 2 ° C., the resist film 2 has a uniform thickness as shown in FIG. It can be formed by distribution.

According to the present embodiment, FIG.
As shown in (1), a resist film 2 having a thickness of 1 μm can be formed on the aluminum film 21 with a uniform thickness (the resist can be applied to a uniform thickness).

Thereafter, the semiconductor wafer 1 is taken out of the resist coating section 6 by the transfer arm 11, and subsequently loaded into the bake processing section 9 (wafer temperature processing section). As shown, a post-application bake is performed.

Here, the purpose of the bake processing of the semiconductor wafer 1 performed by the bake processing section 9 will be described.

First, for example, the in-plane resist size 2a (FIG.
When the dimension distribution of (d) is as shown in FIG. 6, a temperature difference is provided between the central portion and the outer peripheral portion of the semiconductor wafer 1 in the post-coating bake in step S4 shown in FIG. Change the sensitivity at the outer periphery, or
In the pre-development temperature control process in step S6 before the development (step S7) shown in FIG. 4, the developing speed is changed in the outer peripheral portion by changing the temperature of the outer peripheral portion of the semiconductor wafer 1. As a result, FIG.
A uniform size distribution as shown in FIG.

Further, for example, in the case where the size distribution of the resist dimension 2a is uniform as shown in FIG. 7, but the completed dimension after development is formed as shown in FIG. However, it is also possible to dare to make the size distribution of the resist size 2a as shown in FIG. 6 and adjust the completed size as shown in FIG.

Next, a specific method of baking after the application of the resist film 2 shown in step S4 of FIG. 3 will be described.

First, the semiconductor wafer 1 in which the resist film 2 is formed on the aluminum film 21 shown in FIG.
The support plate 3 is carried into the bake processing section 9 (wafer temperature processing section) and installed in the processing chamber 13 of the bake processing section 9.
The semiconductor wafer 1 is placed on the (substrate support member).

Thereafter, the temperature of the support plate 3 is controlled for each of a plurality of regions concentrically divided with respect to the center of the support plate 3, whereby the semiconductor wafer 1 supported by the support plate 3 is controlled with respect to the center. Temperature control is performed for each of a plurality of concentrically divided regions.

Here, the temperature of temperature control element 4 provided at a location corresponding to the outer peripheral portion of semiconductor wafer 1 is lower than the temperature of temperature control element 4 provided at a location corresponding to the center of semiconductor wafer 1. As a result, the temperature of the semiconductor wafer 1 is controlled such that the temperature of the outer peripheral portion is lower by about 1 to 2 ° C. than the central portion of the semiconductor wafer 1.

The temperature control here is a heating process for the semiconductor wafer 1 in which the support plate 3 is a hot plate. By this heat treatment (bake treatment), the resist film 2 can be solidified.

After that, the semiconductor wafer 1 is taken out of the bake processing unit 9 by the transfer arm 11,
It is carried out of the resist processing apparatus shown in FIG.

Subsequently, the semiconductor wafer 1 is moved to the state shown in FIG.
Exposure as shown in FIG.

That is, the glass mask 2 on which a desired mask pattern is formed by the light shielding film 22 such as a chromium film.
3 is irradiated with ultraviolet rays 24 to expose the mask pattern to the resist film 2 formed on the semiconductor wafer 1.

After the completion of the exposure, the developing process shown in FIG. 4 is performed.

First, the semiconductor wafer 1 is carried again into the resist processing apparatus shown in FIG. 1, and the pre-development bake is performed in step S5 in FIG.

The pre-development bake is the same as the post-application bake shown in step S4 of FIG.

That is, here, the temperature of the temperature control element 4 provided at a location corresponding to the outer peripheral portion of the semiconductor wafer 1 is the same as the temperature of the temperature control element 4 provided at the location corresponding to the center of the semiconductor wafer 1. The temperature is controlled so as to be lower, and as a result, the temperature of the outer peripheral portion of the semiconductor wafer 1 is 1
The temperature of the semiconductor wafer 1 is controlled so as to lower by about 2 ° C.

The atmosphere in the processing chamber 13 is, for example,
Along with the atmosphere, and the like of N ₂ atmosphere and dry air,
The temperature control here is a heating process of the semiconductor wafer 1 in which the support plate 3 is a hot plate.

Thereafter, the baked semiconductor wafer 1 is taken out of the baking section 9 by the transfer arm 11, and the semiconductor wafer 1 is carried into the wafer temperature control section 8 (resist processing section). Processing room 13
The semiconductor wafer 1 is placed on a support plate 3 (substrate support member) installed therein.

Subsequently, the temperature of the support plate 3 is controlled for each of a plurality of regions concentrically divided with respect to the center of the support plate 3, whereby the semiconductor wafer 1 supported by the support plate 3 is moved to the center. The temperature is controlled for each of a plurality of regions concentrically divided with respect to.

Here, the temperature of temperature control element 4 provided at a location corresponding to the outer peripheral portion of semiconductor wafer 1 is lower than the temperature of temperature control element 4 provided at a location corresponding to the center of semiconductor wafer 1. As a result, the temperature of the semiconductor wafer 1 is controlled such that the temperature of the outer peripheral portion is lower by about 1 to 2 ° C. than the central portion of the semiconductor wafer 1.

In the temperature control here, the support plate 3 is a cooling plate and the semiconductor wafer 1
This is the cooling process.

Thereafter, the semiconductor wafer 1 is taken out of the wafer temperature control section 8 by the transfer arm 11, and subsequently the semiconductor wafer 1 is loaded into the developing section 7 (resist processing section), where it is shown in step S7 of FIG. Development (resist processing)
I do.

At this time, since the temperature of the semiconductor wafer 1 is controlled so that the temperature of the outer peripheral portion is lower by about 1 to 2 ° C. than the central portion, the developing speed is set to be faster in the central portion than in the outer peripheral portion of the semiconductor wafer 1. Can be done.

As a result, the development as shown in FIG. 5D is performed on the surface of the semiconductor wafer 1, and as a result, the size distribution of the resist size 2a can be made uniform as shown in FIG.

Thereafter, the developing unit 7 is moved by the transfer arm 11.
Then, the semiconductor wafer 1 is taken out from the apparatus, and then the semiconductor wafer 1 is carried into the bake processing unit 9, where the post-development bake is performed and the developed resist film 2 is solidified as shown in step S8 of FIG.

Further, the semiconductor wafer 1 is taken out of the bake processing unit 9 by the transfer arm 11 and subsequently carried out of the resist processing apparatus shown in FIG.

Thereafter, the process proceeds to an etching step, and as shown in FIG.
A predetermined region of the aluminum film 21 of the semiconductor wafer 1 after the development is etched.

Further, as shown in FIG. 5F, the unnecessary resist film 2 on the aluminum film 21 is removed by a resist removing device (not shown).

Thus, a wiring pattern of a desired shape can be formed by the aluminum film 21.

According to the resist processing method and apparatus and the resist coating method of the present embodiment, the following effects can be obtained.

That is, a plurality of temperature control elements 4 provided for each of a plurality of concentric regions of the support plate 3, and a temperature control section for separately controlling heating or cooling of the temperature control elements 4 for each of the plurality of regions. 5 is provided in the resist processing apparatus shown in FIG. 1 so that when the resist processing is performed, before or after the resist processing, the support plate 3
The temperature of the semiconductor wafer 1 supported by the semiconductor wafer 1 can be controlled for each of a plurality of concentric regions from the center.

As a result, a temperature difference can be provided for each concentric region in the plane of the semiconductor wafer 1, and as a result, when the resist is applied to the semiconductor wafer 1 (resist processing), the resist film is formed. 2 can be controlled for each concentric region.

As a result, in the semiconductor wafer 1, it is possible to prevent the thickness of the resist film 2 and the distribution of the resist dimension 2a from being concentrically distributed and fluctuating.

The film thickness distribution of the resist film 2 is determined by the change in viscosity of the resist film 2 (temperature of the resist solution and amount of solvent volatilized).
And the centrifugal force (spinner rotation speed, radius, and resist weight).

Therefore, among these parameters,
By providing a temperature difference in the plane of the semiconductor wafer 1,
It is possible to control the thickness of an arbitrary region in the plane of the semiconductor wafer 1.

Further, when the development (resist processing) is performed, the sensitivity distribution or the development speed distribution can be changed, whereby the size distribution of the resist dimension 2a can be controlled.

The dimension distribution of the resist dimension 2a varies depending on the pre-application bake temperature, time, pre-development bake temperature, time, developer temperature, development time, and temperature of the semiconductor wafer 1 during development.

Therefore, as described above, by providing a temperature difference in the plane of the semiconductor wafer 1 among these parameters, it is possible to control the thickness of an arbitrary region in the plane of the semiconductor wafer 1.

As a comparative example, the difference between the maximum and minimum in-plane film thicknesses of the semiconductor wafer 1 in the two types of resist liquids is one that is 6 nm and the other is only adjustable up to 10 nm. By using the resist processing apparatus of the present embodiment, both can be driven to 2 nm.

That is, it is possible to reduce the variation in the thickness of the resist film 2 with respect to the two types of resist solutions, and to control the variation in the thickness of the two to be substantially the same.

Further, the difference between the maximum and minimum resist dimensions 2a in the plane of the semiconductor wafer 1 is 50 nm,
The variation in the resist size 2a can be reduced by reducing the size to about
If the difference between the maximum and the minimum of the pattern size after etching becomes 50 nm, the resist size 2 is deliberately reduced by a distribution that cancels out the 50 nm after etching.
It is possible to cause a difference of 40 nm in a and finally control the difference to be 10 nm.

Further, since the thickness distribution of the resist film 2 and the size distribution of the resist dimension 2a in the plane of the semiconductor wafer 1 can be controlled, the dimension distribution of the resist dimension 2a of the completed semiconductor wafer 1 can be controlled.

Furthermore, since the size distribution of the resist size 2a of the finished product of the semiconductor wafer 1 can be controlled, the performance and yield of the manufactured semiconductor device can be improved (semiconductor chips may be used).

Since the resist processing method of this embodiment controls the temperature in the plane of the semiconductor wafer 1, the resist processing method is applied to the large-diameter type semiconductor wafer 1 (for example, an 8-inch semiconductor wafer 1). It is more effective when performing processing.

That is, when a large-diameter semiconductor wafer 1 of about 8 inches is used and the resist processing of this embodiment is applied to the resist processing for forming a semiconductor integrated circuit thereon, a greater effect is obtained. be able to.

The invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the embodiments of the invention, and does not depart from the gist of the invention. It is needless to say that various changes can be made.

For example, in the above-described embodiment, the case where a plurality of temperature control elements 4 are provided in each area divided concentrically with respect to the center of the support plate 3 has been described. Support plate 3 of another embodiment
As described above, the temperature control element 4 may be provided for each of a plurality of grid-like regions of the support plate 3.

In this method, the temperature control elements 4 are arranged in a finely divided grid pattern to finely divide the region to be temperature-controlled. For example, the thickness of the resist film 2 in the plane of the semiconductor wafer 1 or the resist Even if the dimension 2a is not concentrically distributed, every area (arbitrary location)
Temperature control can be performed separately.

In this case, means for positioning the semiconductor wafer 1 when the semiconductor wafer 1 is placed on the support plate 3 is provided in the wafer temperature processing section such as the wafer temperature control section 8 or the bake processing section 9. 1 is preferably supported by the support plate 3 with its reference direction positioned by the positioning means.

Therefore, as the positioning means, an orientation flat or a notch of the semiconductor wafer 1 is used, and here, a non-contact type positioning means having a light source 14 for emitting light and an optical sensor 15 for detecting the light source 14 is used. Preferably, it is used.

Therefore, by irradiating the light from the light source 14 onto the entire outer peripheral portion of the semiconductor wafer 1 and detecting the light by the optical sensor 15, the support plate 3 and the semiconductor wafer 1 can be positioned.

However, regarding the positioning of the semiconductor wafer 1, even if the positioning means is not provided, the outer peripheral portion of the support plate 3 and the orientation flat or the notch of the semiconductor wafer 1 are aligned and positioned. Good.

Thus, when controlling the temperature of the support plate 3, even if the thickness of the resist film 2 and the resist dimensions 2a in the plane of the semiconductor wafer 1 are not concentrically distributed, the support plate 3 The temperature of the support plate 3 can be controlled for each of a plurality of regions divided into three lattices.

A temperature control element 4 is provided on the support plate 3 for each of a plurality of grid-like regions, and the temperature of the support plate 3 is controlled for each of the plurality of grid-like regions, thereby obtaining the semiconductor wafer 1. The thickness distribution of the resist film 2 and the resist size 2a corresponding to the semiconductor chip to be formed
Can be controlled with high precision.

Since the semiconductor wafer 1 is supported by the support plate 3 with its reference direction being positioned by the positioning means such as the optical sensor 15, the temperature setting for heating or cooling the semiconductor wafer 1 can be set. It can be performed based on the reference direction.

As a result, it is possible to prevent the etching rate from changing along the orientation flat or the like in the etching processing after the resist processing.

As a result, the thickness distribution of the resist film 2 and the size distribution of the resist dimension 2a in the completed product of the semiconductor wafer 1 can be controlled with high accuracy.

In the embodiment (see FIG. 2) and the other embodiment (see FIG. 10), the support plate 3 is of an integral type. Like the support plate 3 of the embodiment, the support plate 3 is divided into a plurality of concentric or lattice-shaped block members 3d, and a temperature control element 4 is provided for each of the divided block members 3d. It may be.

Here, the support plate 3 shown in FIG.
This is a case where the semiconductor wafer 1 is divided into a plurality of block members 3d concentrically with respect to the center of the semiconductor wafer 1, and
The support plate 3 shown in FIG. 12 is a case where the support plate 3 is divided into a plurality of block members 3d in a lattice shape. In both cases, the temperature control element 4 is provided for each of the plurality of divided block members 3d.

Further, on the support plate 3 shown in FIG. 12, a light source 14 and an optical sensor 15 as positioning means shown in FIG. 10 are provided.

Thus, the support plate 3 is divided into a plurality of block members 3d, and the temperature control elements 4 are provided for each of the plurality of divided block members 3d. The temperature interference between the elements 4 or the load applied by the temperature control elements 4 can be reduced.

Further, in the support plate 3 shown in FIG. 12, the temperature interference between the temperature control elements 4 can be reduced, and the support plate 3 is divided not only into concentric circles but also into a plurality of other regions (arbitrary locations). That is, the temperature of the semiconductor wafer 1 can be controlled.

When dividing the support plate 3 into a plurality of block members 3d, a gap may be formed between the block members 3d formed by the division, or a heat insulating material may be embedded in the gap. May be.

Further, the temperature control element 4
The shape of the divided area in which to install or the block member 3d when the support plate 3 is divided into a plurality of block members 3d
Is not limited to the concentric shape or the lattice shape described in the above embodiment and the other embodiments, and may be other shapes.

Although the resist processing apparatus described in the above embodiment has a resist coating section 6 and a developing section 7 as a resist processing section, only one of the resist processing apparatuses is used. It may be provided.

That is, when only the resist coating section 6 is provided as the resist processing section, the resist processing apparatus is a resist coating apparatus, and when only the developing section 7 is provided as the resist processing section, The resist processing device is a developing device.

In either case of the resist coating apparatus or the developing apparatus, at least one of the wafer temperature control section 8 and the bake processing section 9 must be provided as a wafer temperature processing section.

Further, in the above-described embodiment and the other embodiments, the case where the processing substrate is the semiconductor wafer 1 has been described. However, the processing substrate is a thin film transistor (TFT).
In such a case, the resist processing method and apparatus described in the above embodiment can be applied to the method of manufacturing the liquid crystal substrate.

[0136]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1). When performing the resist processing on the processing substrate, before or after the resist processing, by controlling the temperature of the processing substrate supported by the substrate supporting member for each of a plurality of regions, a temperature difference may be generated in the plane of the processing substrate. Can be made. As a result, when resist processing is performed on the processing substrate, the thickness distribution of the resist film and the dimension distribution of the resist dimensions can be controlled.

(2). When the processing substrate is a semiconductor wafer, the temperature of the semiconductor wafer supported by the substrate support member in the wafer temperature processing unit can be controlled for each of a plurality of regions, whereby the temperature difference within the surface of the semiconductor wafer can be controlled. Can be provided. Therefore, when the resist is applied to the semiconductor wafer, the film thickness distribution of the resist film can be controlled, and as a result, the variation in the film thickness in the plane of the semiconductor wafer can be reduced. Further, when the development is performed, the photosensitive distribution or the developing speed distribution can be changed, whereby the dimensional distribution of the resist dimensions can be controlled. As a result, it is possible to reduce variations in resist dimensions in the plane of the semiconductor wafer.

(3). By controlling the thickness distribution of the resist film and the size distribution of the resist dimensions in the plane of the semiconductor wafer, the dimension distribution of the resist dimensions of the finished product of the semiconductor wafer can be controlled.

(4). A temperature control element is installed on each of a plurality of lattice-like regions on the substrate support member, and the temperature of the substrate support member is controlled on each of the plurality of lattice-like regions, so that the semiconductor wafer can be finely divided into arbitrary portions. Can be controlled, and the thickness distribution of the resist film and the size distribution of the resist dimensions can be controlled with high precision in accordance with the semiconductor chips formed on the semiconductor wafer.

(5). The substrate support member is divided into a plurality of block members, and by controlling the temperature for each of the plurality of block members, it is possible to reduce the temperature interference between adjacent temperature control elements having different temperature settings or the load applied by the temperature control elements. .

(6). Since the semiconductor wafer is supported by the substrate support member with its reference direction being positioned by the positioning means, the temperature setting for heating or cooling the semiconductor wafer can be performed based on the reference direction. As a result, it is possible to prevent the etching rate from changing along the orientation flat or the like in the etching processing after the resist processing. As a result, the thickness of the resist film and the distribution of the resist dimensions in the finished product of the semiconductor wafer can be controlled with high precision.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an example of an embodiment of a structure of a resist processing apparatus according to the present invention.

2A and 2B are diagrams showing an example of a structure of a substrate supporting member provided in a wafer temperature processing unit of the resist processing apparatus shown in FIG. 1, wherein FIG. 2A is a cross-sectional view, and FIG. ) Is a bottom view.

FIG. 3 is a flowchart showing an example of an embodiment of a procedure of resist application in the resist processing method of the present invention.

FIG. 4 is a flowchart showing an example of an embodiment of a developing procedure in the resist processing method of the present invention.

FIGS. 5 (a), (b), (c), (d), (e), and (f) show an example of an embodiment of a pattern forming process on a semiconductor wafer using the resist processing apparatus of the present invention. FIG.

FIG. 6 is a conceptual diagram of a film distribution showing an example of a distribution state of a film thickness and a resist dimension of a resist film formed by the resist processing apparatus of the present invention.

FIG. 7 is a conceptual diagram of a film distribution showing an example of a distribution state of a film thickness and a resist dimension of a resist film formed by the resist processing apparatus of the present invention.

FIG. 8 is a conceptual diagram of a film distribution showing an example of a distribution state of a film thickness and a resist dimension of a resist film formed by the resist processing apparatus of the present invention.

FIG. 9 is a conceptual diagram of a film distribution showing an example of a distribution state of a film thickness and a resist dimension of a resist film formed by the resist processing apparatus of the present invention.

FIGS. 10A and 10B are diagrams showing a structure of a substrate support member provided in a wafer temperature processing unit of a resist processing apparatus according to another embodiment of the present invention, and FIG. Figure,
(B) is a bottom view.

FIGS. 11A and 11B are diagrams showing a structure of a substrate support member provided in a wafer temperature processing unit of a resist processing apparatus according to another embodiment of the present invention, and FIG. Figure,
(B) is a bottom view.

FIGS. 12A and 12B are diagrams showing a structure of a substrate support member provided in a wafer temperature processing unit of a resist processing apparatus according to another embodiment of the present invention, and FIG. Figure,
(B) is a bottom view.

[Description of Signs] 1 Semiconductor wafer (processing substrate) 1a Main surface 1b Back surface 2 Resist film 2a Resist dimensions 3 Support plate (substrate support member) 3a Mounting surface 3b Back surface 3c Small protrusion 3d Block member 4 Temperature control element 5 Temperature control Unit 6 Resist coating unit (resist processing unit) 7 Developing unit (resist processing unit) 8 Wafer temperature control unit (wafer temperature processing unit) 9 Bake processing unit (wafer temperature processing unit) 10 Pre-resist coating unit 11 Transfer arm 12 Cover Reference Signs List 13 processing chamber 14 light source (positioning means) 15 optical sensor (positioning means) 21 aluminum film 22 light shielding film 23 glass mask 24 ultraviolet light

Claims (9)

[Claims] A step of placing a processing substrate on a substrate supporting member installed in a processing chamber; and controlling the temperature of the substrate supporting member for each of a plurality of regions, thereby supporting the substrate supported by the substrate supporting member. Controlling the temperature of the processing substrate for each of the plurality of regions; and performing a resist process on the processing substrate, wherein the temperature of the processing substrate is controlled before or after the resist processing. A resist processing method comprising: 2. A step of mounting a semiconductor wafer on a substrate support member installed in a processing chamber, and controlling the temperature of the substrate support member for each of a plurality of regions, thereby supporting the semiconductor wafer supported by the substrate support member. Controlling the temperature of the semiconductor wafer for each of the plurality of regions; and performing a resist process on the semiconductor wafer, wherein the temperature of the semiconductor wafer is controlled before and / or after the resist process. A resist processing method characterized by the above-mentioned. 3. The resist processing method according to claim 1, wherein when controlling the temperature of the substrate supporting member,
A resist processing method, wherein a temperature of the substrate support member is controlled for each of a plurality of concentrically divided regions of the substrate support member. 4. The resist processing method according to claim 1, wherein when controlling the temperature of the substrate supporting member,
A resist processing method, wherein the temperature of the substrate supporting member is controlled for each of a plurality of regions of the substrate supporting member divided into a lattice. 5. A resist processing section for performing a resist processing on a semiconductor wafer, a wafer temperature processing section for controlling a temperature of the semiconductor wafer, and a substrate supporting member installed in the wafer temperature processing section and supporting the semiconductor wafer. And a plurality of temperature control elements provided for each of a plurality of regions of the substrate support member and heating or cooling each of the regions, and separately controlling the heating or cooling of the temperature control element for each of the plurality of regions. A temperature control unit that performs a resist process on the semiconductor wafer in the resist processing unit, and sets a plurality of temperatures of the semiconductor wafer in the wafer temperature processing unit before and / or after the resist process. A resist processing apparatus capable of controlling each of the regions. 6. A resist processing apparatus according to claim 5, wherein said temperature control element is provided on said substrate support member for each of a plurality of concentric or lattice regions. apparatus. 7. The resist processing apparatus according to claim 5, wherein said substrate support member is divided into a plurality of block members in a concentric shape or a lattice shape, and said substrate support member is divided for each of said plurality of divided block members. A resist processing apparatus comprising a temperature control element. 8. The resist processing apparatus according to claim 5, wherein a positioning means for positioning the semiconductor wafer when mounting the semiconductor wafer on the substrate support member is provided in the wafer temperature processing unit. Wherein the semiconductor wafer is supported by the substrate support member with its reference direction being positioned by the positioning means. 9. A step of mounting a semiconductor wafer on a substrate supporting member installed in a processing chamber, and controlling the temperature of the substrate supporting member for each of a plurality of regions to thereby support the semiconductor wafer supported by the substrate supporting member. A step of controlling the temperature of the semiconductor wafer for each of the plurality of regions; and a step of applying a resist to the semiconductor wafer, wherein the temperature of the semiconductor wafer is controlled before or after applying the resist. A resist coating method characterized by the above-mentioned.