JP2005123651A - Resist film processing apparatus and method of forming resist pattern - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent redeposition of material vaporized out of a processed substrate in heat-treating without changing the optimum temperature condition. <P>SOLUTION: A resist film processing apparatus includes a resist forming means 105 for forming a chemically amplified resist film on the processed substrate. Exposure means 102 radiates energy beam on the chemical amplification type resist film to form an exposed region having a latent image pattern.Rotation correcting means ARM rotationally corrects the direction of the processed substrate. Heat-treating means 104 heats the chemically amplified resist film as flowing air in one direction along the processed substrate. Developing means 106 develops the chemically amplified resist film. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a substrate processing apparatus and processing method, for example, a coating film processing apparatus, a coating film heating apparatus, a heat processing method using the heating apparatus, and a resist pattern forming method related to lithography.

  In semiconductor device manufacturing, a resist pattern is used for element region formation, electrode wiring processing, and the like. First, after forming a resist coating film on a semiconductor wafer, the resist pattern is subjected to a heat treatment called pre-baking for volatilizing the solvent in the resist. Next, a predetermined pattern is transferred to the resist film by exposure.

  In recent years, with the miniaturization of semiconductor elements, high resolution is required in the linking process. In response to this requirement, the wavelength of exposure light to be used is being shortened. In optical lithography, a KrF excimer laser (wavelength: 248 nm) has been widely used as an exposure light source.

  On the other hand, as a photosensitive resin (photoresist) material to which a pattern is transferred, a photoresist called a chemically amplified resist has been devised and put into practical use as the wavelength of exposure light becomes shorter. The chemically amplified resist contains therein an acid generator that generates an acid upon exposure. The acid generated by exposure decomposes the resin (positive type) or crosslinks (negative type). In the subsequent development process, the property that the solubility in the developer is changed is utilized.

  This chemically amplified resist has an advantage of excellent resolution, but is sensitive to the environment. That is, it reacts with a basic substance in the atmosphere, and the acid is deactivated to cause deterioration of the pattern shape and resolution. Environmental control is performed to prevent this deterioration. Environment control is generally performed by providing a chemical filter in a coater / developer that performs processing such as resist coating and development.

  On the other hand, many of these chemically amplified resists require a heat treatment step called PEB (Post Exposure Bake) after the exposure step. PEB is performed to diffuse the acid generated in the exposure process. After the PEB processing step, the chemically amplified resist is exposed to a developing solution to form a desired resist pattern.

  It is known that the chemically amplified resist disappears when the acid evaporates in the PEB treatment, in addition to the acid deactivation. Conventionally, several methods have been proposed as a method for reducing disappearance due to acid evaporation in PEB treatment. For example, a method of reducing acid evaporation by increasing the pre-baking temperature for the purpose of volatilizing the solvent after applying the resist, and lowering the PEB temperature. ("Effect of acid evaporation in Chemically Amplified resists on insoluble layer formation" Journal of Photopolymer Science and Technology Vol. 8, Number 4 (1995) P.561-570: hereinafter referred to as well-known example 1), or PEB treatment at normal atmospheric pressure And a method of reducing acid evaporation by performing the reaction under a higher pressure (Japanese Patent Laid-Open No. 11-38644, hereinafter referred to as known example 2).

  According to the known example 1, the amount of acid evaporation during PEB can be reduced. However, since the pre-bake process and the PEB process are performed under conditions greatly deviating from the optimized temperature condition (normal condition), the exposure amount and focus tolerance (margin) performance inherent in the resist cannot be sufficiently obtained.

  Further, in the PEB process, for example, as shown in FIG. 65, a heating device that can prevent gas and fine particles generated during heating from adhering to the inside of the chamber to become a generation source of particles is required. Such a heating apparatus has an air inlet port 6501 provided on one side surface of the chamber 6500 and an exhaust port 6502 provided on the other side surface facing the air inlet port 6501. A gas 6504 is caused to flow between the air inlet port 6501 and the exhaust port 6502 along the upper surface of the semiconductor wafer W on the soaking plate 6503. Thereby, an air flow is generated in the chamber.

  However, as shown in FIG. 66, the acid evaporated at the time of PEB is carried to the downstream side by the air flow as indicated by the arrow in the figure, and is reattached on the wafer. Therefore, the acid concentration on the resist surface is different between the chip located most upstream with respect to the airflow and the chip located downstream thereof. For this reason, the resist dimensions in the wafer surface after the development process vary.

  Moreover, in the said well-known example 2, although evaporation of an acid can be reduced, no countermeasure is taken about the reattachment of the evaporated acid. Since the evaporated acid is redeposited on the semiconductor wafer, it is difficult to eliminate the resist size fluctuation in the wafer surface after the development processing.

Prior art document information related to the invention of this application includes the following.
Japanese Patent Laid-Open No. 11-38644 Effect of acid evaporation in Chemically Amplified resists on insoluble layer formation, `` Journal of Photopolymer Science and Technology '', Vol. 8, Number4 (1995), p.561-570

  The present invention has been made to solve the above-mentioned problems, and a first object is to reattach the transpiration substance evaporated from the substrate to be processed during the heat treatment without changing the optimum temperature condition. It is an object of the present invention to provide a substrate processing apparatus and a substrate processing method capable of preventing the above.

  A second object of the present invention is to provide a substrate processing apparatus and a substrate processing method capable of further reducing the evaporated substance evaporated from the substrate to be processed.

  A third object of the present invention is to provide a substrate processing method capable of improving the uniformity of resist dimensions within the surface of the substrate to be processed.

  A resist film processing apparatus according to a first aspect of the present invention comprises: a resist forming means for forming a chemically amplified resist film on a substrate to be processed; and a latent image pattern formed by irradiating the chemically amplified resist film with energy rays. An exposure unit that forms an exposure area, a rotation correction unit that rotates the orientation of the substrate to be processed, and a heating process that heats the chemically amplified resist film while flowing an air flow in one direction along the substrate to be processed And a developing means for developing the chemically amplified resist film.

  A resist pattern forming method according to a second aspect of the present invention includes a step of forming a chemically amplified resist film on a substrate to be processed, and an exposure having a latent image pattern by irradiating the chemically amplified resist film with energy rays. In the substrate processing method in which the step of exposing to form a region, the step of heating the chemically amplified resist film, and the step of developing the chemically amplified resist film are performed in this order, the heating step The heating step according to the change in effective energy amount caused by the change in the balance between the amount of the evaporated material evaporating from the chemically amplified resist film and the amount of the evaporated material reattached at the time The amount of energy applied to the exposure area is corrected before the exposure.

  According to a third aspect of the present invention, there is provided a resist pattern forming method comprising: a step of forming a chemically amplified resist film on a substrate to be processed; and an ultraviolet ray, a far ultraviolet ray, a vacuum ultraviolet ray, an electron beam, X, Exposing to form an exposure region having a latent image pattern by irradiating an energy ray selected from the group consisting of a line; heating the chemically amplified resist film in the presence of air current; and In the substrate processing method in which the step of developing the amplification resist film and the step of developing are performed in this order, the amount of the evaporant that evaporates from the chemically amplified resist film during the heating step, and the evaporant reattaches. The amount of energy applied to the exposure area is corrected prior to the heating step in response to an effective change in the first energy amount caused by a change in balance with the amount. It is characterized in.

  A resist pattern forming method according to a fourth aspect of the present invention includes a step of forming a chemically amplified resist film on a substrate to be processed, and an exposure having a latent image pattern by irradiating the chemically amplified resist film with energy rays. In the resist pattern forming method, the step of exposing to form a region, the step of heating the chemically amplified resist film, and the step of developing the chemically amplified resist film are performed in this order. The heating is performed in accordance with a change in effective energy amount caused by a change in the balance between the amount of the evaporant evaporated from the chemically amplified resist film and the amount of the evaporant reattached during the process. The amount of energy supplied to the exposure area is corrected during the process.

  According to a fifth aspect of the present invention, there is provided a resist pattern forming method comprising: a step of forming a chemically amplified resist film on a substrate to be processed; and an ultraviolet ray, far ultraviolet ray, vacuum ultraviolet ray, electron beam, X, Exposing to form an exposure region having a latent image pattern by irradiating an energy ray selected from the group consisting of a line; heating the chemically amplified resist film in the presence of an air stream; and In the resist pattern forming method, wherein the step of developing the amplification resist film and the step of developing in this order are performed, the amount of the evaporant evaporated from the chemically amplified resist film during the heating step, and the deposit reattach The amount of energy supplied to the exposure area is corrected during the heating step according to the change in the effective first energy amount caused by the change in the balance with the amount to be applied. Characterized in that it is.

  A resist pattern forming method according to a sixth aspect of the present invention includes a step of forming a chemically amplified resist film on a substrate to be processed, and a latent image pattern by irradiating the chemically amplified resist film with energy rays. A step of exposing to form an exposure region, a step of heating the chemically amplified resist film in the presence of an air flow, and supplying a developer to the chemically amplified resist film with a chemical solution supply nozzle, thereby forming a desired resist. And a developing process for forming a pattern in this order. In the resist pattern forming method, the amount of evaporates evaporated from the chemically amplified resist film during the heating process, and the evaporates are recycled. From the distribution of the effective energy amount caused by the change in the balance with the amount of adhesion and the resist pattern dimension variation caused by the distribution That in accordance with the selected value from a group, and adjusting the development rate of the resist pattern in the treated substrate during the process of the development.

  ADVANTAGE OF THE INVENTION According to this invention, the substrate processing apparatus and the processing method which can heat-process a to-be-processed substrate on optimal temperature conditions in the case of heat processing can be provided. In addition, it is possible to suppress the evaporation material evaporated from the substrate to be processed from reattaching to the substrate to be processed.

  In addition, it is possible to sufficiently bring out the exposure performance and focus margin (margin) performance of the resist and improve the uniformity of the resist dimension within the surface of the substrate to be processed.

  Therefore, it is possible to improve the reliability and manufacturing yield of devices produced through subsequent processes.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

  FIG. 1 illustrates a plan view of a substrate processing apparatus used in each embodiment of the present invention. The substrate processing apparatus includes a coating and developing apparatus (coater / developer) 101 and an exposure apparatus 102. The coating and developing apparatus 101 includes a wafer station 103, a heating device (heater) 104, a coater 105, a developing unit 106, and an interface 107. Arrangement of each part is illustration and is not limited to this.

(First embodiment)
A heating apparatus and a substrate processing method using the same according to the first embodiment of the present invention (hereinafter, the substrate processing method includes a resist pattern forming method) will be described with reference to FIG.

  FIG. 2 is a cross-sectional view schematically showing the heating apparatus according to the first embodiment.

  This heating device has a housing 201. The housing 201 has a heating means. The heating means includes a soaking plate 202 and a heater 203. A substrate to be processed, for example, a semiconductor wafer W (hereinafter simply referred to as a wafer) is placed on the upper surface of the soaking plate 202. The heater 203 is divided into a plurality of parts and arranged on the back surface of the soaking plate 202. Each heater 203 is independently controlled by a control unit (not shown) so as to have a uniform set temperature within the wafer W surface.

  The soaking plate 202 is supported by a frame 205 via a heat insulating material 204. The wafer W to be heat-processed has a spacing of 0.1 mm on the soaking plate 202 by a proximity gap 206. The wafer W is heated for a predetermined time.

  An aluminum top plate 207 is installed above the soaking plate 202. The heat equalizing plate 202, the casing 201, and the top plate 207 constitute a chamber 208. In the chamber 208, a porous ceramic plate 209 is disposed above the soaking plate 202 so as to face the soaking plate 202. The porous ceramic plate 209 functions as a partition member and has a large number of holes. As the porous ceramic plate 209, a material having a raw material of SiC, a pore diameter of 50 μm, and a porosity of 40% is used.

  The porous ceramic plate 209 divides the space 210 in the chamber 208 into a first space 211 and a second space 212 in the vertical direction. The first space 211 includes the heat equalizing plate 202 on which the wafer W is placed. The soaking plate 202 is not included in the second space 212.

  The porous ceramic plate 209 is supported by a plurality of support pins 213. The support pins 213 are lifted and lowered by a lifting mechanism 214 installed below the soaking plate 202. Accordingly, the porous ceramic plate 209 moves up and down. By moving the porous ceramic plate 209 up and down, the interval between the porous ceramic plate 209 and the wafer W placed on the soaking plate 202 is adjusted. The porous ceramic plate 209 is configured so that it can be easily attached and detached from the heating device, and can be cleaned as needed.

  An air inlet 215 is provided on one side surface of the second space 212 of the chamber 208. An exhaust port 216 connected to the exhaust means 220 is provided on the other side surface facing the air introduction port 215. An airflow 217 is formed in one direction from the air inlet 215 to the exhaust outlet 216.

  The volume of air in the first space 211 is expanded by heating. The expanded air is sucked perpendicularly to the porous ceramic plate 209 by the air flow 217 in the second space 212. This air is then taken into the second space 212 through the holes of the porous ceramic 209. That is, an air flow 218 in a direction substantially perpendicular to the wafer W is formed in the first space portion 211.

  Next, PEB processing and resist pattern formation using the heating apparatus will be described.

  First, a coating film serving as an antireflection film is formed on the wafer W by a spin coating method. Next, baking is performed under the conditions of 190 ° C. and 60 seconds to form an antireflection film having a thickness of 60 nm.

  After the positive chemically amplified resist is applied on the wafer W, a heat treatment called pre-baking is performed under conditions of 140 ° C. and 90 seconds. Pre-baking is performed to volatilize the solvent in the resist. Thus, a resist film having a thickness of 400 nm is formed on the antireflection film. The chemically amplified resist is composed of a phenolic resin as a base polymer and a mixed solvent of ethyl lactate and ethyl 3-ethoxypropionate. The same chemically amplified resist is used in the following embodiments.

  After the pre-baking, the wafer W is cooled to room temperature. The wafer W is transferred to an exposure apparatus using a KrF excimer laser (far infrared laser) having a wavelength of 248 nm as a light source, and reduced projection exposure is performed via an exposure mask.

  FIG. 3 is an enlarged view showing a pattern obtained when the exposure mask used in the present embodiment is transferred to the wafer W in the exposure apparatus. In the figure, one exposure region 320 (hereinafter simply referred to as an exposure chip) has a left half line pattern region 321 and a flat exposure region 322 where no resist remains.

  FIG. 4 is an enlarged view showing the line pattern region 321. In the figure, 401 is a line portion, and 402 is a space portion. As shown in FIG. 4, the line pattern region 321 has a line dimension = 170 nm, a space dimension = 90 nm, and a repeated pattern arranged at a pitch = 260 nm.

  As shown in FIG. 5, the exposure chip 320 is transferred onto the wafer W in an arrangement of 11 × 13 horizontally and a latent image is formed.

  Next, after the exposure, the wafer W is transferred to the heating device of the present embodiment, and placed on the soaking plate 202 with an interval of 0.1 mm. Next, a unidirectional airflow 217 is allowed to flow through the second space 212 and PEB treatment is performed at 140 ° C. for 90 seconds.

  Next, after performing the PEB process, the wafer W is cooled to room temperature. The wafer W is transferred to a developing unit and subjected to an alkali developing process for 60 seconds. After the development process is completed, a rinse process using pure water and a spin drying process are performed to form a resist pattern.

  Hereinafter, a comparison between the in-plane distribution of the resist pattern dimensions obtained by using the heating apparatus of this embodiment and the result of PEB treatment by the conventional heating apparatus shown in FIG. 65 will be described.

  FIG. 67 shows the in-plane distribution of the quality of the pattern transfer result obtained using the conventional heating device.

  The exposure chip indicated by the hatched pattern in the figure is determined to be NG when the developed resist pattern is observed from above with a SEM (Scanning Electron Microscope). That is, the resist pattern was not resolved. As shown in FIG. 67, the exposure chip located on the most upstream side with respect to the airflow during the PEB process was NG. This is because the amount of exposure differs depending on the chip as shown below. That is, in the conventional heating apparatus, during PEB processing, an air flow 6504 containing acid evaporated from the resist film flows from the left end to the right end as shown by the arrows in FIG. As a result, the acid evaporated from the exposure chip located at the uppermost stream of the air stream is carried downstream by this air stream and reattaches to the exposure chip surface on the downstream side. Therefore, the balance of the amount of acid is (generated acid)-(evaporated acid) + (reattached acid). However, the tip located most upstream with respect to the airflow does not have the (reattached acid), so that the effective exposure amount is reduced compared to the tip located downstream. For this reason, even if the same energy (exposure irradiation amount and PEB heating amount) is given to each exposure chip 6705, a difference occurs in the line size of the resist pattern formed after development. That is, when a positive resist is used, the exposure chip located at the most upstream is large.

  FIG. 6 is a diagram showing the in-plane distribution of quality of the pattern transfer result obtained using the heating apparatus according to the present embodiment. As shown in FIG. 6, an exposure chip determined as NG is not observed, and a good pattern transfer result is obtained.

  In the present embodiment, a porous ceramic plate having a pore diameter of 50 μm and a porosity of 40% is used for the following reason. FIG. 8A shows the relationship between the porosity of a porous ceramic plate having a pore diameter of 50 μm and the amount of redeposition of evaporated acid (standardized with a value when the porosity is 0). As can be seen from the figure, since the effect of suppressing the reattachment amount is saturated at a porosity of 40%, the porosity of the porous ceramic plate using 40% is used.

  According to the present embodiment, in the PEB processing step, the air current containing the evaporated acid in the first space is sucked in the substantially vertical direction with respect to the wafer W by the air current in the second space in the chamber. . The sucked airflow is taken into the second space through the holes of the porous ceramic plate. For this reason, the evaporated acid does not reattach to the downstream side. Therefore, in the wafer W surface, the acid concentration on the resist surface is substantially uniform between exposure shots. Therefore, there is no variation in the effective exposure amount, and the uniformity of resist dimensions within the wafer W surface can be improved. In addition, in the PEB processing step, PEB processing can be performed under optimum temperature conditions, and the exposure amount and focus tolerance (margin) performance inherent in the resist can be sufficiently derived.

(Second Embodiment)
A heating apparatus and a substrate processing method using the same according to the second embodiment of the present invention will be described with reference to FIG. The second embodiment is different from the first embodiment in heating means.

  FIG. 7 is a cross-sectional view schematically showing a heating apparatus according to the second embodiment. The description of the same part as the first embodiment is omitted, and only a different part will be described.

  A heat source 730 for heating the soaking plate 202 is installed on the back surface of the soaking plate 202. The soaking plate 202 and the heat source 730 constitute a heating means.

  The heat source 730 includes a halogen lamp 731 and a light guide 732. The light guide 732 includes a prismatic block. The light emitted from the halogen lamp 731 enters the light guide 732. The incident light travels while repeating almost total reflection at the side surface of the light guide, and reaches the heat equalizing plate 702.

  The soaking plate 202 is heated by absorbing light from the light guide 732. The output of the halogen lamp 731 is controlled by the temperature of a thermocouple (not shown) embedded in the soaking plate 202 and adjusted to a desired temperature (140 ° C.). In this embodiment, a porous ceramic plate 209 having a pore diameter of 100 μm and a porosity of 50% is used.

  Next, PEB processing and resist pattern formation using the heating apparatus will be described.

  First, a coating film serving as an antireflection film is formed on the wafer W by a spin coating method. Next, baking is performed under the conditions of 190 ° C. and 60 seconds to form an antireflection film having a thickness of 60 nm.

  After a positive chemically amplified resist is applied on the wafer W, pre-baking is performed at 140 ° C. for 90 seconds. Thus, a resist film having a thickness of 400 nm is formed on the antireflection film.

  After the pre-baking, the wafer W is cooled to room temperature. The wafer W is transferred to an exposure apparatus using a KrF excimer laser with a wavelength of 248 nm as a light source, and reduced projection exposure is performed through an exposure mask.

  As shown in FIG. 5, an exposure chip including a 150 nm line and space pattern is transferred onto a wafer W in an arrangement of 11 × 13 horizontally through an exposure mask to form a latent image.

  Next, after the exposure, the wafer W is transferred to the heating device of the present embodiment and placed on the soaking plate 202. Next, a unidirectional airflow 217 is allowed to flow through the second space 212 and PEB treatment is performed at 140 ° C. for 90 seconds. After the PEB process, the same process as in the first embodiment is performed to form a resist pattern.

  In the second embodiment, the result of measuring the resist line dimension after development in the wafer W plane is as follows. That is, the in-plane dimension variation of the 150 nm line and space pattern was significantly reduced to 4.3 nm, compared to 9.7 nm (3σ) when PEB was processed by a conventional heating apparatus.

  In the first and second embodiments, the line pattern and the line and space pattern have been described. However, the present invention is not limited to these patterns, and the same effect can be obtained with other patterns such as a hole pattern.

  In the first and second embodiments, examples of numerical values of the pore diameter and the porosity of the porous ceramic plate have been described, but the present invention is not limited to these numerical values. For example, it is desirable to obtain the optimum porosity from the relationship between the porosity as shown in FIG.

(Third embodiment)
A heating apparatus according to the third embodiment of the present invention and a substrate processing method using the same will be described with reference to FIG. Description of the same parts as those of the first embodiment is omitted, and only different parts will be described. In the third embodiment, the evaporant is adsorbed using an adsorbing member.

  FIG. 9 is a cross-sectional view schematically showing a heating apparatus according to the third embodiment.

  In the chamber 208, an adsorbing member 940 is installed above the heat equalizing plate 202 so as to face and oppose it. The distance between the adsorption member 940 and the soaking plate 202 is 0.5 mm. The adsorption member 940 is supported by a plurality of support pins 213.

  As the adsorption member 940, a surface-polished single crystal silicon plate is used. Or you may use what comprised oxides, such as ceramics, an alumina, quartz, or nitride itself. Moreover, you may use what coat | covered the oxide film or the nitride film on the surface of these members.

  The evaporated substance evaporated from the wafer W during the heat treatment is adsorbed on the surface of the adsorbing member 940 installed in the vicinity of the wafer W.

  Next, PEB processing and resist pattern formation using the heating apparatus will be described.

  The process up to exposure is the same as in the first embodiment. By exposure, exposure chips similar to those in the first embodiment are transferred onto the wafer W in an arrangement of 11 × 13 horizontally, and a latent image is formed.

  After the exposure, the wafer W is transferred to the heating device of the present embodiment and placed on the soaking plate 202 with an interval of 0.1 mm. Next, PEB treatment is performed under conditions of 140 ° C. and 90 seconds. After the PEB process, the same process as in the first embodiment is performed to form a resist pattern.

  The in-plane distribution of the quality of the pattern transfer result obtained by using the heating apparatus according to this embodiment is as shown in FIG. That is, an exposure chip determined as NG is not observed in the surface of the wafer W, and a good pattern transfer result is obtained.

  In the present embodiment, the distance (gap) between the adsorption member and the soaking plate is set to 0.5 mm. This is due to the following reason. FIG. 8B is a diagram showing the relationship between the gap d between the adsorbing member and the soaking plate, and the spread distance of the evaporated and reattached acid (standardized with a value when the cap is 7.5 mm). As the gap is made smaller, the distance over which the acid spreads becomes smaller, but conversely, the gap needs to be controlled with high accuracy (the evaporation distance varies within the wafer W surface). Considering this point, the gap is set to 0.5 mm which is relatively easy to control.

  Thus, according to the present embodiment, the acid evaporated from the resist film is adsorbed by the adsorption member 940 in the PEB processing step, and thus the evaporated acid does not reattach to the wafer W. Therefore, there is no variation in effective exposure amount caused by re-deposition of evaporated acid on the wafer W within the wafer W surface, and the uniformity of resist dimensions within the wafer W surface can be improved. In addition, since PEB processing can be performed under optimum temperature conditions in the PEB processing step, the exposure amount and focus tolerance (margin) performance inherent in the resist can be sufficiently derived.

(Fourth embodiment)
A heating apparatus and a substrate processing method using the same according to the fourth embodiment of the present invention will be described with reference to FIG. Description of the same parts as those in the second and third embodiments is omitted, and only different parts will be described. The fourth embodiment differs from the third embodiment in heating means.

  FIG. 10 is a cross-sectional view schematically showing a heating apparatus according to the fourth embodiment.

  In the chamber 208, an adsorbing member 940 is installed above the heat equalizing plate 202 so as to face and oppose it. The distance between the adsorption member 940 and the soaking plate 202 is 0.5 mm.

  The evaporated substance evaporated from the wafer W during the heat treatment is adsorbed on the surface of the adsorbing member 940 installed in the vicinity of the wafer W.

  Next, PEB processing and resist pattern formation using the heating apparatus will be described.

  The process up to exposure is the same as in the second embodiment. By exposure, as shown in FIG. 5, an exposure chip including a 130 nm line-and-space pattern is transferred onto the wafer W in an arrangement of 11 × 13 horizontally, and a latent image is formed.

  Next, after exposure, the wafer W is transferred to the heating apparatus of this embodiment, placed on the soaking plate 202, and subjected to PEB processing at 140 ° C. for 90 seconds. After the PEB process, the same process as in the first embodiment is performed to form a resist pattern.

  In the fourth embodiment, the result of measuring the resist line dimension after development in the wafer W plane is as follows. In other words, the in-plane dimension variation of the 130 nm line and space pattern was significantly reduced to 4.1 nm as compared to 9.5 nm (3σ) when PEB was processed by a conventional heating apparatus.

  In the third and fourth embodiments, a heater can be further provided on the back surface of the single crystal silicon plate as the adsorption member. After the wafer W is taken out of the heating device by this heater, the single crystal silicon plate is heated by the heater. By this heating, the adsorbed acid may be desorbed and the surface of the single crystal silicon plate may be cleaned. In this case, it is preferable to install an intake hole and an exhaust hole on the side surface of the chamber and exhaust the desorbed acid.

(Fifth embodiment)
A heating apparatus and a substrate processing method using the same according to the fifth embodiment of the present invention will be described with reference to FIG. Description of the same parts as those of the first embodiment is omitted, and only different parts will be described. In the fifth embodiment, the heating device is applied to a heat treatment process before radiating energy rays, more specifically, to a pre-bake process after a resist coating process.

  FIG. 11 is a cross-sectional view schematically showing a heat treatment apparatus according to the fifth embodiment.

  In this embodiment, the proximity gap between the soaking plate 202 and the wafer W is 0.5 mm.

  The heat equalizing plate 202, the housing 201, and the top plate 207 constitute a chamber 208. In the chamber 208, a proximity plate 1107 is installed above and in close proximity to the hot plate 202. The distance between the proximity plate 1107 and the soaking plate 202 is 2.0 mm.

  A heater 1109 for heating the proximity plate is installed concentrically on the proximity plate 1107. The heater 1109 is controlled by a temperature sensor and a temperature control unit (not shown). By controlling the heater 1109, the temperature of the proximity plate 1107 is controlled. The surface of the proximity plate 1107 facing the wafer W is mirror-polished.

  The proximity plate 1107 is made of aluminum. Or you may use the thing which is easy to process and is excellent in thermal conductivity, for example, the product made from SUS. Further, a heat radiating portion (not shown) for promoting heat radiation can be provided on the surface of the proximity plate 1107. The heat dissipating part enables more accurate temperature control.

  A substrate processing method using the heating apparatus will be described. First, a liquid film made of a resist solid component and a solvent is formed on the wafer W. For this liquid film formation, meniscus cuff application utilizing capillary action disclosed in JP-A-7-163929 is used. Or you may produce by the method of apply | coating by reciprocatingly moving the ultra-fine sludge disclosed by Unexamined-Japanese-Patent No. 2000-188251 on a to-be-processed substrate. The embodiment of the present invention does not depend on the coating method, and any method can be applied as long as the method forms a solid film from a liquid film state. It can also be applied to solid film formation other than resist film formation.

  The wafer W is transferred to the heat treatment apparatus of this embodiment. Heating is performed while controlling the temperature of the soaking plate 202 so that the wafer W becomes 140 ° C. In the present embodiment, temperature control is performed so that the temperature of the proximity plate 1107 becomes, for example, 100 ° C. After the heat treatment for 180 seconds, the wafer W is transferred to a cooling device and cooled to near room temperature. Thereby, a 300-nm-thick resist solid film is formed.

  In this way, by heating the proximity plate 1107, the solvent as an evaporant is not liquefied (condensed) by the proximity plate.

  In general, when an evaporating substance is condensed on the proximity plate, the heat treatment apparatus becomes dirty. Alternatively, the falling droplets dissolve the solid film, and as a result, problems such as deterioration of the film thickness distribution occur. By using the heat treatment apparatus described in this embodiment, these problems can be avoided and a solid film having excellent film thickness uniformity can be formed.

  In the present embodiment, control is performed so that the temperature of the proximity plate becomes 100 ° C., but the present invention is not limited to this. It is important to set the temperature so that the evaporate does not liquefy depending on the liquid film to be heated.

  In addition, an exhaust unit may be provided in the heat treatment apparatus, and exhaust may be performed during the heat treatment within a range that does not adversely affect the film thickness distribution of the formed solid film.

(Sixth embodiment)
Next, a heating apparatus and a substrate processing method using the same according to the sixth embodiment of the present invention will be described with reference to FIGS. Description of the same parts as those of the first embodiment is omitted, and only different parts will be described. In the sixth embodiment, a plate member provided with cooling means on the top plate of the chamber is used.

  FIG. 12 is a cross-sectional view schematically showing a heat treatment apparatus according to the sixth embodiment of the present invention.

  An aluminum plate member 1207 is installed above the soaking plate 202. The soaking plate 202, the casing 201, and the plate member 1207 constitute a chamber 208.

  In the chamber 208, the plate member 1207 is installed above the heat equalizing plate 202 so as to face it. The distance between the plate member 1207 and the soaking plate 202 is 0.8 mm.

  Hereinafter, the details of the plate member 1207 will be described with reference to FIG. FIG. 13 schematically shows a top view of the plate member 1207. A water pipe 1209 is installed inside the plate member 1207. The circulating cooling water flows in the plate member 1207 from the IN side to OUT. The plate member 1207 is temperature-controlled by a thermocouple (not shown) installed on the plate member 1207 so that the temperature is always near room temperature. The surface of the plate member 1207 facing the wafer W is mirror-polished.

  The plate member 1207 is made of aluminum. Or you may use the thing which is easy to process and is excellent in thermal conductivity, for example, the product made from SUS.

  Next, the PEB process using the heating device will be described.

  Similarly to the first embodiment, an antireflection film having a film thickness of 85 nm is formed on the wafer W. Next, after a positive chemically amplified resist is applied on the wafer W, a pre-bake process is performed at 100 ° C. for 90 seconds. As a result, a resist film having a thickness of 300 nm is formed on the antireflection film.

  After pre-baking, the wafer W is cooled to room temperature. The wafer W is transferred to an exposure apparatus that uses an ArF excimer laser with a wavelength of 193 nm as a light source. Here, an exposure region including a 110 nm line and space pattern is transferred onto the wafer W in a 13 × 15 arrangement via the exposure mask to form a latent image.

  After the exposure, the wafer W is transferred to the heat treatment apparatus of this embodiment, and is placed on the soaking plate 202 with an interval of 0.1 mm. The evaporated material evaporated from the wafer W during the heat treatment is adsorbed on the surface of the plate member 1207. Next, PEB treatment is performed under conditions of 110 ° C. and 90 seconds. After the PEB process, the same process as in the first embodiment is performed to form a resist pattern.

  As a result of measuring the resist line dimension after development in the wafer plane, the in-plane dimension variation of the 110 nm line-and-space pattern was reduced by about half compared to the case of using a conventional PEB processing apparatus.

  Thus, according to the present embodiment, the acid evaporated from the resist film is adsorbed to the plate member 1207 in the PEB processing step, so that the evaporated acid does not reattach to the wafer W. Accordingly, there is no variation in the effective exposure amount caused by the re-deposition of the evaporated acid on the wafer W in the wafer W surface, and the uniformity of resist dimensions in the wafer surface can be improved.

(Seventh embodiment)
A heating apparatus and a substrate processing method using the same according to a seventh embodiment of the present invention will be described with reference to FIG. Description of the same parts as those of the first embodiment is omitted, and only different parts will be described. In the seventh embodiment, heat treatment is performed in the presence of an electric field.

  FIG. 14 is a cross-sectional view schematically showing a heating apparatus according to the seventh embodiment.

  In the chamber 208, an electrode member 1450 is installed above the soaking plate 202 so as to face and oppose it. The distance between the soaking plate 202 and the electrode member 1450 is 3.0 mm. The electrode member 1450 is supported by a plurality of support pins 214.

  SUS is used as the electrode member 1450. Alternatively, any metal or semiconductor may be used as long as it is acid-resistant and conductive. Further, the electrode member 1450 may have a surface facing the wafer W covered with an insulating film such as an oxide film or a nitride film.

  A voltage is applied between the soaking plate 202 and the electrode member 1450 by the power source P. By this application, an electric field in the vertical direction (vertical direction on the paper surface) is generated between the soaking plate 202 and the electrode member 1450 during the heat treatment.

  In this embodiment, the soaking plate 202 is applied to the ground potential, and a negative potential is applied to the electrode member 1450. However, this potential relationship may be such that the electrode member 1450 is at a low potential with respect to the soaking plate 202.

  Due to the generated electric field, a positively charged evaporated substance evaporated from the wafer W, such as an acid, moves in the vertical direction. Next, the evaporated substance is adsorbed on the surface of the electrode member 1450. Therefore, the acid evaporated from the resist does not reattach to the wafer W.

  Next, PEB processing and resist pattern formation using the heating apparatus will be described.

  The process up to exposure is the same as in the first embodiment. As a result of the exposure, as shown in FIG. 5, an exposure chip including a 130 nm line and space pattern is transferred onto the wafer W in an arrangement of 11 × 13 vertically, thereby forming a latent image.

  After the exposure, the wafer W is transferred to the heating apparatus of this embodiment and placed on the soaking plate 202. The PEB process is performed at 140 ° C. for 90 seconds in a state where a ground potential is applied to the soaking plate 202 and a negative potential is applied to the electrode member 1450. After the PEB process, the same process as in the first embodiment is performed to form a resist pattern.

  In the seventh embodiment, the result of measuring the resist line dimension after development in the wafer W plane is as follows. That is, the in-plane dimension variation of the 140 nm line and space pattern was significantly reduced to 3.8 nm, compared to 8.4 nm (3σ) when PEB was processed by a conventional heating apparatus.

(Eighth embodiment)
A heating apparatus and a substrate processing method using the same according to an eighth embodiment of the present invention will be described with reference to FIG. Description of the same parts as those in the second and seventh embodiments is omitted, and only different parts will be described. The eighth embodiment differs from the seventh embodiment in heating means.

  FIG. 15 is a cross-sectional view schematically showing a heating apparatus according to the eighth embodiment.

  As with the seventh embodiment, the power source P applies the soaking plate 202 to the ground potential and applies a negative potential to the electrode member 1450. As a result, an electric field similar to that in the seventh embodiment is generated.

  Due to the generated electric field, a positively charged evaporated substance evaporated from the wafer W, such as an acid, moves in the vertical direction. The evaporated material is adsorbed on the electrode member 1450. Therefore, the acid evaporated from the resist does not reattach to the wafer W.

  Using this heating device, the same processing as in the seventh embodiment is performed. That is, an antireflection film and a chemically amplified resist film are formed on the wafer W. An exposure chip including a 130 nm line and space pattern is transferred through an exposure mask to form a latent image. As a result of the PEB treatment of the wafer W obtained in this way, the in-plane dimension variation of the 160 nm line and space pattern was as follows. That is, it was significantly reduced to 3.4 nm as compared to 8.0 nm (3σ) when the heat treatment was performed with a conventional heating apparatus.

(Ninth embodiment)
A heating apparatus and a substrate processing method using the same according to the ninth embodiment of the present invention will be described with reference to FIG. Description of the same parts as those in the first and seventh embodiments is omitted, and only different parts will be described. The ninth embodiment differs from the seventh embodiment in the direction of the electric field.

  FIG. 16 is a cross-sectional view schematically showing a heating apparatus according to the ninth embodiment.

  In this embodiment, contrary to the seventh and eighth embodiments, a ground potential is applied to the soaking plate 202 and a positive potential is applied to the electrode member 1450. However, this potential relationship may be such that the electrode member 1450 is at a high potential with respect to the soaking plate 202.

  Since the evaporation substance evaporating from the wafer W, for example, acid is positively charged, the high potential applied to the electrode member 1450 suppresses evaporation of the acid from the resist.

  In the heating apparatus according to the ninth embodiment, the intensity of the electric field can be arbitrarily changed by easily changing the applied voltage between the soaking plate and the electrode member, and the suppression of the evaporated acid can be easily controlled. . Therefore, in the PEB process using the heating apparatus of this embodiment, the acid to be evaporated can be easily controlled, so that the uniformity of resist dimensions can be easily controlled.

(Tenth embodiment)
A heating apparatus and a substrate processing method using the same according to the tenth embodiment of the present invention will be described with reference to FIG. Description of the same parts as those in the second and eighth embodiments is omitted, and only different parts will be described. The tenth embodiment differs from the ninth embodiment in heating means.

  FIG. 17 is a cross-sectional view schematically showing a heating apparatus according to the tenth embodiment.

  In this embodiment, contrary to the seventh and eighth embodiments, a ground potential is applied to the soaking plate 202 and a positive potential is applied to the electrode member 1450. However, this potential relationship may be such that the electrode member 1450 is at a high potential with respect to the soaking plate 202.

  Therefore, the evaporation substance evaporating from the wafer W, for example, the acid is positively charged, and the high potential applied to the electrode member 1450 suppresses the evaporation of the acid from the resist.

  In the heating apparatus according to the tenth embodiment, by easily changing the applied voltage between the soaking plate and the electrode member, the strength of the electric field can be arbitrarily changed, and the suppression of the evaporated acid can be easily controlled. . Therefore, in the PEB process using the heating apparatus of this embodiment, the acid to be evaporated can be easily controlled, so that the uniformity of resist dimensions can be easily controlled.

  In the seventh to tenth embodiments, after the heat treatment is completed, the wafer is taken out of the heating device, and then the positive electrode is applied with a positive potential to desorb the adsorbed acid, thereby cleaning the surface of the electrode member. May be performed. In this case, it is preferable to install an intake hole and an exhaust hole on the side surface of the chamber and exhaust the desorbed acid.

  In the first to fourth and seventh to tenth embodiments, the case where the heating device is applied to the PEB treatment process has been described. However, it is needless to say that the present invention can also be applied to other processes in resist pattern formation, for example, a heat treatment process after forming a coating film. Thereby, the same effect as the sixth embodiment can be obtained.

(Eleventh embodiment)
A substrate processing method according to an eleventh embodiment of the present invention will be described with reference to the drawings. In the eleventh embodiment, in the exposure step, the exposure amount condition for each exposure chip is set according to each exposure chip. The exposure conditions are closely related to the PEB treatment process performed after the exposure process. The PEB treatment process is performed by, for example, a conventional heating apparatus shown in FIG.

  The process up to pre-baking is the same as in the first embodiment. Next, in the same manner as in the first embodiment, by exposure, exposure chips including a 150 nm line and space pattern are transferred onto the wafer W in an arrangement of 11 × 13 horizontally to form a latent image. The exposure conditions are set as follows.

  The positional relationship between each exposure chip 1801 in the PEB processing step and the direction of the airflow 1802 during the PEB processing is as shown in FIG.

  In FIG. 18, the exposure chip 1801 of the wafer W has the most upstream exposure chip 1801 </ b> A positioned on the most upstream side with respect to the airflow 1802 during the PEB process and the downstream exposure chip positioned on the downstream side with respect to the other airflow 1802. Classification into 1801B. The reason why exposure chips are classified in this manner is that the exposure amount on the upstream side is lower than the exposure amount on the downstream side for the reason described above. Reference numeral 1803 denotes a notch.

  In the present embodiment, in the exposure process, the effective exposure amount is adjusted to be equal between the most upstream exposure chip 1801A and the downstream exposure chip 1801B. That is, the exposure amount when transferring to the uppermost exposure chip 1801A is set larger than the exposure amount of the downstream exposure chip 1801B by the following setting method.

  FIG. 19 is a diagram showing the relationship between the exposure amount and the dimension of a resist line formed through a lithography process. In FIG. 19, the solid line indicates the downstream exposure chip, and the broken line indicates the most upstream exposure chip.

From Figure 19, where the resist line dimension was determined exposure conditions as the desired 150nm, 18.55mJ / cm ² at the most upstream exposure chips 1801A, a 18.36mJ / cm ² at a downstream exposure chips 1801B.

  Thus, by obtaining the relationship between the exposure amount and the finished resist line dimension in advance, the optimum exposure amount condition for each of the exposure chips 1801 can be determined.

  Therefore, the uppermost exposure chip 1801A and the downstream exposure chip 1801B are exposed under different exposure amount conditions. After this exposure process, rotation correction is performed so that the notch 1803 of the wafer W is always in the same direction, for example, the lower side, during the exposure process and the PEB processing process. Thereafter, the wafer W is transferred to the heating device described above, and PEB processing is performed under the conditions of 140 ° C. and 90 seconds. After the PEB process, the same process as in the first embodiment is performed to form a resist pattern.

  The results of measuring the resist line dimensions after development in the wafer W plane were as follows. That is, the in-plane dimension variation of the 150 nm line and space pattern was significantly reduced to 5.4 nm compared to 11.6 nm (3σ) when the exposure amount condition was not corrected.

  In the present embodiment, the case where one PEB heating apparatus is used has been described, but a plurality of wafers W can be continuously processed using a plurality of PEB heating apparatuses. At this time, it is necessary to rotate the wafer W in accordance with which PEB heating apparatus is to be transported in the previous stage of PEB processing. The necessity will be described below.

  FIG. 20 is a diagram schematically showing a heating unit group in the coater / developer and an arm ARM for transferring the wafer W, and a state in which the wafer W is transferred to the HP 1-1.

  In FIG. 20, the heating unit group includes two towers (TW1, TW2) having a structure in which a plurality of racks are stacked. The PEB units are located at HP1-1 of TW1 and HP2-1 of TW2. The other heating unit is used, for example, for pre-baking performed immediately after heat treatment of the antireflection film or resist application.

  FIG. 21 is a view of the state in which the wafer W is transferred to the HP 1-1 as viewed from above. As shown in FIG. 21, the position of the notch 1803 of the wafer W is located on the left side. The most upstream exposure chip 1801A is normally positioned upstream of the airflow 1802.

  Next, a state in which the wafer W is transferred to the HP 2-1 will be described with reference to FIGS. As shown in FIG. 22, since the relative positional relationship between the notch 1803 of the wafer W and the arm ARM does not change, the position of the notch 1803 of the wafer W is transferred in FIG. 22 when the wafer W is transferred to the HP 2-1. On the right. As a result, the most upstream exposure chip 1801A is positioned downstream of the airflow 1802. That is, the positional relationship of the most upstream exposure chip with respect to the airflow 1802 is rotated 180 degrees between the case where it is conveyed to HP1-1 and the case where it is conveyed to HP2-1. Therefore, as shown in FIG. 24, when the wafer W is transferred to the HP 2-1, it is necessary to transfer the wafer W after performing rotation correction at a stage before the transfer.

  In this way, when a plurality of PEB heating apparatuses having the same apparatus structure are used and a plurality of wafers W are continuously processed, the wafers are transferred depending on which PEB unit is transferred to the PEB heating apparatus before being put into the PEB heating apparatus. It is necessary to correct the rotation of W.

  Although it is conceivable that the uppermost exposure chip and the downstream exposure chip are set and exposed for each wafer W without correcting the rotation of the wafer W, the process becomes complicated and is not practical.

  In the present embodiment, the 150 nm line and space pattern has been described. However, the present invention is not limited to this and can be applied to other patterns such as a hole pattern.

(Twelfth embodiment)
A substrate processing method according to the twelfth embodiment of the present invention will be described with reference to the drawings. In the twelfth embodiment, the heating temperature during PEB processing is adjusted according to the exposure chip.

  The process up to pre-baking is the same as in the first embodiment. Next, by exposure, an exposure chip including an isolated line pattern of 140 nm is transferred onto the wafer W in an arrangement of 11 × 13 horizontally, and a latent image is formed. In this embodiment, the exposure amount condition at the time of transfer is the same for all exposure chips.

  After exposure, rotation correction is performed so that the notch 1803 of the wafer W shown in FIG. 18 is always in the same direction, for example, the lower side, during the exposure process and the PEB processing process. The wafer W is transferred to the heating device described above, and PEB processing is performed. At this time, heating conditions are determined according to the following procedure.

  FIG. 25 shows the relationship between the PEB processing temperature and the resist line dimensions after development. The solid line indicates the downstream exposure chip, and the broken line indicates the most upstream exposure chip.

  From FIG. 25, the PEB temperature condition for obtaining the desired resist line size of 140 nm is 140.23 ° C. for the most upstream exposure chip 1801A and 140.00 ° C. for the downstream exposure chip 1801B.

  As described above, by determining the relationship between the PEB processing temperature and the finished resist line dimensions in advance, the optimum heat processing temperature condition for each exposure chip 1801 is determined.

  In this embodiment, the heating conditions are set so that the heating temperature of the uppermost exposure chip 1801A is 140.23 ° C. and the heating temperature of the downstream exposure chip 1801B is 140.00 ° C.

  For this temperature setting, the set temperature of the divided heater corresponding to the region of the most upstream exposure chip 1801A may be increased. In this case, it is preferable to adjust the set temperature of the downstream heater in order for the heater arranged on the downstream side to receive interference from the upstream heater. For example, it is desirable to strictly adjust the set temperature of each divided heater using a temperature measuring instrument in which a plurality of temperature sensors such as thermocouples are embedded in the wafer W.

  In this way, the temperature condition of the PEB process is determined, and the PEB process for 90 seconds is performed. After the PEB process, the same process as in the first embodiment is performed to form a resist pattern.

  As a result of measuring the line dimensions of the resist pattern after development in the wafer W plane, the following results were obtained. That is, the in-plane dimension variation of the 140 nm isolated line pattern was significantly reduced to 6.1 nm compared to 12.3 nm (3σ) when the PEB processing temperature condition was not corrected.

(13th Embodiment)
A substrate processing method according to a thirteenth embodiment of the present invention will be described with reference to the drawings. In the thirteenth embodiment, exposure amount correction performed in the exposure region is performed in the wafer surface.

  As shown in FIG. 26, only the most upstream exposure area 2602A located on the most upstream side with respect to the air flow 2601 in the PEB is exposed to perform PEB and development steps, and the evaluation sample 1 is created. With respect to the most upstream exposure region 2602A in the evaluation sample 1, the resist pattern dimension is evaluated, and the exposure amount condition that achieves the desired size is optimized (correction of exposure amount).

  As shown in FIG. 27, the most upstream exposure amount region 2602A is exposed under the optimized exposure amount condition. The exposure region 2602B, which is one downstream, is exposed, and the evaluation sample 2 is created as described above. With respect to the exposure region 2602B in the sample 2 for evaluation, the resist pattern dimension is evaluated, and the exposure amount condition that achieves the desired size is optimized (correction of the exposure amount). Such optimization of the exposure amount is performed for all exposure amount regions toward the downstream side.

  As described above, the exposure amount correction condition is sequentially calculated from the exposure area arranged on the upstream side with respect to the airflow during PEB to the exposure area on the downstream side. Thereby, efficient and highly accurate correction can be performed.

  When the exposure region was formed in the wafer under the exposure amount condition thus obtained, the uniformity of the resist pattern dimension between the exposure regions could be greatly improved.

(Fourteenth embodiment)
A substrate processing method according to a fourteenth embodiment of the present invention will be described with reference to the drawings. In the fourteenth embodiment, exposure amount correction performed in the exposure region is performed. A detailed description of each step in lithography is omitted because it overlaps with the eleventh and twelfth embodiments.

  FIG. 28 schematically shows the relative positional relationship between the exposure region and the airflow during PEB. The direction from the upstream side to the downstream side with respect to the air flow 2801 was taken as the X axis, and the most upstream edge portion of the chip was set to X = 0.

  FIG. 29 schematically shows the relationship between the position X in the chip when the exposure amount is D and the resist pattern dimension (line dimension) after development. For the reasons described above, the effective exposure amount on the upstream side is lower than that on the downstream side. For this reason, when a positive resist is used, the pattern dimension increases on the upstream side. Hereinafter, a procedure for calculating the exposure amount correction at the position X in the chip will be described.

  FIG. 30 shows the relationship between the pattern size near the exposure dose D and the exposure dose. Based on the measured pattern dimension value, the relationship between the exposure amount and the pattern dimension is approximated by a linear function. When the pattern dimension at the position X = X1 is L1, the exposure amount D1 is calculated from the relationship of FIG. Next, a ratio D1 / D0 with the exposure amount D0 of the desired pattern dimension L0 is obtained. D · (D1 / D0) obtained by multiplying the exposure amount D by this becomes the optimum exposure amount at X = X1. In this procedure, an optimum exposure amount for obtaining the desired pattern dimension L0 is obtained at each position X. The result is shown in FIG.

  Such exposure amount correction in the exposure region can be performed by the following method, for example, if a step & scan type exposure apparatus is used.

  When the irradiation power of the light source during exposure is P, the scanning speed (scanning speed) is v, and the slit width of the illumination area is s, the exposure amount D is proportional to E · (s / v). From this equation, the relationship between the position X in the chip and the scanning speed v is obtained. The result is shown in FIG. As described above, the exposure amount can be corrected by controlling the scanning speed v within the exposure region.

  The exposure amount correction condition is calculated under the exposure amount condition thus obtained, and an exposure region is formed. As a result, the uniformity of the resist pattern dimension within the exposed region is greatly improved.

  In the present embodiment, the case where the pattern dimension simply decreases from the upstream side toward the downstream side is shown, but the present invention is not limited to this. For each exposure mask, it is necessary to obtain the relationship between the position X in the chip shown in FIG. 29 and the resist pattern dimension after development.

  Further, the relationship between the position X in the chip and the resist pattern dimension after development differs depending on the position of the exposure region on the wafer. For this reason, it is desirable to perform the exposure correction by obtaining the relationship in each exposure region.

  In this embodiment, the relationship between the exposure amount and the pattern dimension is approximated by a linear function based on the measured pattern dimension value, but the present invention is not limited to this. A similar effect can be obtained by approximating with a multi-order function based on the dimension measurement value.

(Fifteenth embodiment)
A substrate processing method according to the fifteenth embodiment of the present invention will be described with reference to the drawings. In the fifteenth embodiment, the amount of exposure performed in the exposure region is changed. A detailed description of each step in lithography is omitted because it overlaps with the eleventh and twelfth embodiments.

  FIG. 33 shows a configuration of a step-and-scan projection exposure apparatus. The illumination system (system) 3301 includes an excimer laser light source, a beam expander, a fly-eye lens, and the like. Illumination light 3302 emitted from the illumination 3301 enters a beam splitter 3305 through an ND (Neutral Density) filter 3303 and a mirror 3304 for adjusting the irradiation amount. The incident light is divided into light 3302a for projection exposure and light 3302b for monitoring the exposure amount. The projection exposure light 3302 a is incident on the exposure mask 3306. The light transmitted through the exposure mask 3306 is transferred to the wafer 3309 via the reduction projection optical system 3308.

  Light 3302b for monitoring the exposure amount is monitored by an exposure amount monitor unit 3311. The monitor result is fed back to the ND filter 3303 for dose adjustment via the control unit 3312 and the filter control unit 3313. The exposure mask 3306 and the wafer 3309 are held by an exposure mask stage 3307 and a wafer stage 3310, respectively. The exposure mask stage 3307 is controlled by the exposure mask stage control unit 3312. Wafer stage 3310 is controlled by wafer stage control unit 3313. The ND filter 3303 is controlled by a filter control unit 3314. The wafer stage 3310 and the ND filter 3303 are controlled by the control unit 3315 via the control units 3313 and 3314, and scan each other synchronously.

  FIG. 34 schematically shows the transmittance distribution of the ND filter 3303 for dose adjustment. The transmittance distribution was determined so as to correct an effective exposure amount variation caused by the evaporation and reattachment of the acid during the PEB. The ND filter 3303 having the transmittance distribution shown in FIG. 34 scans and moves with respect to the illumination light 3302. As a result, the amount of light incident on the exposure mask 2006 can be changed as shown in FIG. 31, for example. As a result, the exposure amount can be corrected within the exposure region.

  When exposure amount correction conditions were calculated under the exposure amount conditions thus obtained and an exposure region was formed, the uniformity of the resist pattern dimension within the exposure region was greatly improved.

(Sixteenth embodiment)
A substrate processing method according to a sixteenth embodiment of the present invention will be described with reference to the drawings. In the sixteenth embodiment, the exposure amount is corrected according to the resist pattern coverage of the exposure region.

  First, a coating film serving as an antireflection film is formed on the wafer W by a spin coating method. Next, baking is performed under the conditions of 215 ° C. and 90 seconds to form an antireflection film having a thickness of 85 nm.

  After the positive chemically amplified resist is applied on the wafer W, pre-baking is performed at 110 ° C. for 90 seconds. Thus, a resist film having a thickness of 300 nm is formed on the antireflection film.

  After pre-baking, the wafer W is cooled to room temperature. Next, the wafer W is loaded into a step-and-scan exposure apparatus using an ArF excimer laser (wavelength 193 nm) as a light source. Here, the exposure area is transferred to the wafer W under the conditions of NA = 0.55, σ = 0.75, and ε = 0.67. Hereinafter, details of the exposure region and the method of forming the exposure region will be described.

  FIG. 35 schematically shows a part of the exposure area. In FIG. 35, D is a 110 nm line and space pattern group that requires the most dimensional accuracy in the exposure region. This pattern group D exists in regions A, B, and C having different resist coverages. The scanning speed at the time of exposure is from the left to the right in the figure, and the airflow direction at the time of PEB performed after the exposure is from the top to the bottom in FIG. In region A, the resist coverage is 60%, in region B, the resist coverage is 30%, and in region C, the resist coverage is 0%. Here, the resist coverage is the percentage of the resist remaining after pattern formation.

  As described above, the pattern size varies due to re-deposition of the evaporated material generated during the PEB process on the resist surface.

  The amount of redeposition varies depending on the resist coverage, and as a result, the pattern dimension varies. For this reason, in this embodiment, the corrected exposure amount is calculated according to the following procedure.

  FIG. 36 shows the relationship between the exposure amount and the line size. In FIG. 36, each straight line indicates a region A, a region B, and a region C. These straight lines are obtained by approximating pattern measurement values with a linear function.

Based on the relationship shown in FIG. 36, the exposure amount condition of a desired 110 nm is obtained for each of the regions A, B, and C. As a result, the region A is 13.63, the region B is 13.59, and the region C is 13.55 mJ / cm ² .

  Areas A, B, and C are exposed with the exposure amount (energy amount) calculated in this way. The method for correcting the exposure amount within the exposure region is described in detail in the fourteenth and fifteenth embodiments, and is therefore omitted here.

  Next, the wafer W is transferred to the PEB processing unit, where heat treatment is performed at 130 ° C. for 90 seconds. As the PEB processing unit, the exhaust flow described in the eleventh embodiment is a one-way flow along the wafer. As shown in FIG. 35, the exhaust flow during PEB is set to be in a direction that is 90 degrees different from the scan direction during exposure. After the PEB process, the same process as in the first embodiment is performed to form a resist pattern.

  As a result of measuring the resist line dimension after development in the exposure region, the in-plane dimension variation of the 110 nm line and space pattern was significantly reduced as compared with the case where the exposure amount condition was not corrected.

  In the present embodiment, the scanning direction at the time of exposure and the airflow direction at the time of PEB are set to be 90 degrees different from each other, but the present invention is not limited to this. It is important to calculate the corrected exposure amount by obtaining the relationship between the exposure amount and the pattern dimension shown in FIG. 36 according to the resist coverage, the airflow direction during PEB, and the flow velocity.

  In this embodiment, the correction method based on the resist coverage in the exposure area has been described. However, it is preferable to perform correction between the exposure areas. As a correction method, it is desirable that the air flow direction during PEB is sequentially performed from upstream to downstream as described in the above embodiment.

  In this embodiment, the relationship between the exposure amount and the pattern dimension is approximated by a linear function based on the measured pattern dimension value, but the present invention is not limited to this. A similar effect can be obtained by approximating with a multi-order function based on the dimension measurement value.

(Seventeenth embodiment)
A substrate processing method according to the seventeenth embodiment of the present invention will be described with reference to the drawings. In the seventeenth embodiment, the exposure amount is corrected in a light irradiation process different from exposure. That is, the exposure condition at the time of transferring the desired pattern is set to be the same for all the exposure chips, and thereafter, the exposure is adjusted according to the position of the exposure chip.

The process up to exposure is the same as in the sixteenth embodiment. By exposure, an exposure chip including an isolated line pattern of 130 nm is transferred onto the wafer in an arrangement of 11 × 13 (excluding the exposure chip outside the wafer range) to form a latent image. The exposure condition is an exposure dose of 15.00 mJ / cm ² .

  FIG. 37 schematically shows a light irradiation system for adjusting the exposure amount. Wafer W is placed on stage 3701 through proximity gap 3702. A light source 3703 for light irradiation is installed above the wafer W. The light source 3703 is composed of a plurality of low-pressure mercury lamps. Irradiation light 3704 is emitted from the light source 3703. The irradiation light 3704 is only light having a wavelength of 193 nm via a wavelength selection filter (not shown). Light having a wavelength of 193 nm is applied to the wafer W through the mask 3705. This light irradiation system is installed in a chamber 3706 purged with nitrogen.

FIG. 38 schematically shows the positional relationship between the exposure region group 3801 formed on the wafer and the light irradiation region 3802 irradiated during correction. In this embodiment, as the PEB unit used in the PEB process, a radial unit in which the exhaust airflow 3901 is directed from the outer periphery toward the center is used as shown in FIG. For this reason, light having a wavelength of 193 nm is irradiated only to the outermost peripheral exposure region (3902 in FIG. 39) located at the uppermost stream with respect to the air current during PEB. The irradiation amount condition is 0.08 mJ / cm ² , and this condition is obtained by the following procedure. Reference numeral 3903 denotes a downstream exposure area.

  FIG. 40 shows the relationship between the irradiation dose during correction and the dimensional difference between the outermost (uppermost) exposure area and the inner (downstream) exposure area. From the relationship between the corrected dose condition and the pattern dimension difference, the dose condition where the pattern dimension difference is zero is found.

  Next, the wafer W is transferred to the PEB processing unit, and heat treatment is performed at 130 ° C. for 90 seconds. As the PEB processing unit, as shown in FIG. 39, a radial unit in which the exhaust flow is directed from the periphery of the wafer toward the center is used. After the PEB process, the same process as in the first embodiment is performed to form a resist pattern.

  As a result of measuring the resist line dimension after development in the exposure region, the in-plane dimension variation of the 130 nm isolated line pattern was greatly reduced as compared with the case where the exposure amount condition was not corrected.

  In this embodiment, although the exhaust airflow at the time of PEB used the radial thing, it is not limited to this. When using a PEB unit in which the airflow is unidirectional, for example, as shown in FIG. 41, a lamp having a spread can be used as a light source, and irradiation can be performed obliquely over the wafer. 41, reference numeral 4101 denotes a light source, 4102 denotes a wafer, 4103 denotes a proximity gap, and 4104 denotes a stage. In the case of such a method, correction may be performed with a dose distribution as shown in FIG.

  In this embodiment, the case where only the most upstream exposure area is corrected has been described. However, the present invention is not limited to this. Instead of the mask (3705 in FIG. 37), a filter whose transmittance changes may be used.

  In this embodiment, the low-pressure mercury lamp is used as the light source at the correction irradiation. However, the present invention is not limited to this. For example, a laser may be used as the light source.

(Eighteenth embodiment)
A substrate processing method according to an eighteenth embodiment of the present invention will be described with reference to the drawings. In the eighteenth embodiment, the exposure condition at the time of desired pattern transfer is set to be the same for all exposure areas, and thereafter, the exposure is adjusted according to the position of the exposure chip. The exposure amount adjustment is performed in another electron beam (hereinafter referred to as EB) irradiation process.

  On the wafer W, a positive chemically amplified resist for EB is applied by a spin coating method. Next, prebaking is performed at 100 ° C. for 90 seconds. As a result, a resist film having a thickness of 300 nm is formed on the wafer.

  After pre-baking, the wafer W is cooled to room temperature. The wafer W is transferred to a pattern transfer apparatus using EB as an exposure source. Here, as shown in FIG. 43, an exposure region including a 100 nm line-and-space pattern is transferred onto the wafer in an arrangement of 11 × 15, and a latent image is formed. The exposure area group on the wafer is classified into a chipped exposure area 4301 on the edge of the wafer and an exposure area 4302 that is not.

  As the PEB unit used in the PEB process, as shown in FIG. 44, an exhaust flow 4401 is a one-way flow along the wafer. For this reason, EB irradiation is performed only on the exposure region (4501 in FIG. 45) located at the uppermost stream with respect to the airflow. The dose condition at this time was determined by the following procedure.

  FIG. 46 shows the relationship between the area of the chipped exposure region (normalized by the original exposure region area) and the EB irradiation amount necessary for correcting the pattern dimension variation. The smaller the area of the chipped exposure region, the smaller the amount of acid that evaporates during PEB, so a larger amount of irradiation is required. In such a procedure, the irradiation amount necessary for correction was calculated according to the area of the missing exposure region, and the exposure amount was adjusted under the conditions.

  Next, the wafer W is transferred to the PEB processing unit, and heat treatment is performed at 110 ° C. for 90 seconds. As the PEB processing unit, as shown in FIG. 44, a unit in which the exhaust flow becomes a one-way flow along the wafer is used. After the PEB process, the same process as in the first embodiment is performed to form a resist pattern.

  As a result of measuring the resist line dimension after development in the exposure region, the in-plane dimension variation of the line and space pattern was significantly reduced as compared with the case where the exposure amount condition was not corrected.

  In this embodiment, the case where only the most upstream exposure area is corrected has been described. However, the present invention is not limited to this. As described in the thirteenth embodiment, it is desirable to calculate the corrected dose from upstream to downstream.

(Nineteenth embodiment)
A substrate processing method according to a nineteenth embodiment of the present invention will be described with reference to the drawings. In the nineteenth embodiment, the developer discharge conditions during development are adjusted according to the exposure chip.

  The process up to exposure is the same as in the eleventh embodiment. By exposure, an exposure chip including a 150 nm line-and-space pattern is transferred onto the wafer W in a vertical 11 × 13 grid arrangement (excluding exposure chips outside the range of the wafer W), and the latent image is transferred. Is formed. In this embodiment, the exposure amount condition for each exposure chip is fixed. The PEB treatment process is performed using, for example, a normal heating device similar to the conventional one shown in FIG.

  In the present embodiment, adjustment is performed in the development process so that the line dimensions of the resist pattern formed after development are equal between the most upstream exposure chip 1801A and the downstream exposure chip 1801B shown in FIG. That is, the developing speed of the resist pattern on the wafer is adjusted. Specifically, the developing speed of the most upstream exposure chip 1801A is increased by the following method.

  The developing method in this embodiment will be described with reference to FIGS. 47 (a) and 47 (b). A linear chemical solution supply nozzle 4701 is used to scan from one end (start position P0 in the drawing) to the other end (end position P1 in the drawing) of the wafer W while discharging the chemical solution. As a result, a chemical film 4702 is formed on the entire surface of the substrate to be processed.

  Normally, when it is desired to uniformly develop the wafer surface, the discharge amount of the nozzle, the distance between the nozzle and the wafer, and the scanning speed of the nozzle are constant (1.0 L / min, 1.5 mm, and 120 mm / sec, respectively). A developer film is formed. Thereafter, after static development for 60 seconds, a rinsing process and a spin drying process are performed to form a resist pattern.

FIG. 48 shows the relationship between the exposure dose and the pattern size of the resist formed through the lithography process. The solid line in FIG. 48 shows the case of the downstream exposure chip, and the broken line shows the case of the most upstream exposure chip. This relationship is obtained by measuring the dimension with respect to the exposure amount for the most upstream exposure chip and the downstream exposure chip. In the present embodiment, since the desired dimension is 150 nm (L0), all chips are exposed at 18.36 mJ / cm ² (D). However, since the effective exposure amount is reduced in the most upstream exposure chip, the dimension is 158 nm (L1).

  For the reasons described above, the exposure amount of the most upstream exposure chip is effectively reduced and the size is increased. For this reason, in the present embodiment, by increasing the discharge amount of the developer from the chemical solution supply nozzle in the most upstream exposure chip, the liquid replacement amount at the time of supplying the developer is increased. As a result, development is promoted, and the size of the most upstream exposure chip matches the size of the downstream exposure chip. Specifically, it is performed as follows.

  FIG. 49 shows the relationship between the ejection amount and the pattern dimensions. The discharge amount is determined using the relationship of FIG. In FIG. 49, the solid line indicates the case of the downstream exposure chip, and the broken line indicates the case of the most upstream exposure chip. This relationship is obtained by developing the substrate to be processed exposed with the exposure amount (D) by changing the discharge amount and measuring the pattern dimensions of the uppermost exposure chip and the downstream exposure chip. At the standard discharge rate of 1.0 L / min (S0), the downstream tip is finished at L0 and the most upstream tip is finished at L1. From this relationship, it can be seen that if the most upstream chip with a small exposure amount is processed with the discharge amount S1 (1.2 L / min), the desired dimension (L0) is obtained.

  Next, a specific method for controlling the discharge amount will be described with reference to FIGS.

  In FIG. 50, 5001 (position P0) is a position where the supply port of the chemical solution supply nozzle is applied to the wafer W. 5002 (position P1) is a position where the supply port of the chemical solution supply nozzle passes through a portion where the most upstream exposure chips are arranged in a line. 5003 (position P2) is a position where the most upstream exposure chip disappears. 5004 (position P3) is the other end of the wafer W.

  FIG. 51 shows the relationship between the position of the nozzle supply port and the discharge amount. As shown in FIG. 51, the nozzle of the chemical solution supply nozzle scans with the discharge amount S1 from P0 to the position P1, and with the discharge amount S0 after the position P2. Between the positions P1 and P2, the discharge amount is controlled to linearly decrease from S1 to S0. The change in the discharge amount from the position P1 to the position P2 is not limited to this, and may be a change that provides the most uniformity, such as a change in a quadratic function.

  In the present embodiment, the method for controlling the ejection amount is shown, but it is also possible to control the distance between the wafer and the nozzle and the scanning speed of the nozzle.

  FIG. 52 shows the relationship between the distance between the wafer and the nozzle (denoted as a gap in the figure) and the pattern dimension. In FIG. 52, the solid line indicates the case of the downstream exposure chip, and the broken line indicates the case of the most upstream exposure chip. The relationship shown in FIG. 52 is obtained by developing the substrate to be processed exposed at the exposure amount (D) by changing the gap (1-2 mm) and measuring the pattern dimensions of the uppermost exposure chip and the downstream exposure chip. .

  When the pattern dimension is controlled by controlling the distance between the wafer and the nozzle, the gap (G1) on the most upstream exposure chip is determined using the relationship shown in FIG. G0 is a standard condition gap and is 1.5 mm. G1 is a gap in the most upstream exposure chip and is 1.2 mm.

  FIG. 53 shows the relationship between the position of the nozzle supply port and the gap between the wafer and the nozzle. Using the relationship shown in FIG. 52, as shown in FIG. 53, the gaps on the most upstream exposure chip and the downstream exposure chip are controlled to optimum values, respectively, and nozzle scanning is performed. That is, the nozzle of the chemical solution supply nozzle scans with the gap G1 from the position P0 to the position P1, and after the position P2 with the gap G0. Between the positions P1 and P2, the gap is controlled to linearly increase from G1 to G0. The change in the gap from the position P1 to the position P2 is not limited to this, and may be a change that provides the most uniformity, such as a change in a quadratic function.

  Thus, the reason why the development speed can be adjusted by changing the gap is that the strength when the liquid hits the substrate surface can be changed. Specifically, development can be accelerated by increasing it, and it can be decelerated by decreasing it. In the present embodiment, since the adjustment is made by the distance (1 to 2 mm) at which the discharge pressure is directly transmitted to the substrate, the smaller the distance, the more the development can be promoted. However, according to another experiment, it was found that when the discharge port is separated from the substrate surface by 5 mm or more, the development is promoted as the distance increases. This is because the effect of gravity is greater than the discharge pressure. Accordingly, the gap for adjusting the development is preferably determined by obtaining the relationship between the pattern dimension and the gap according to the conditions.

  FIG. 54 shows the relationship between the nozzle scanning speed (scanning speed) and the pattern dimensions. In FIG. 54, the solid line indicates the case of the downstream exposure chip, and the broken line indicates the case of the most upstream exposure chip. The relationship of FIG. 54 is that the substrate to be processed exposed at the exposure amount (D) is developed by changing the nozzle scanning speed (100 to 140 mm / sec), and the pattern dimensions of the most upstream exposure chip and the downstream exposure chip are measured. Is required.

  When the pattern dimension is controlled by controlling the nozzle scanning speed, the scanning speed (V1) on the most upstream exposure chip is determined using the relationship shown in FIG. V0 is a scanning speed under standard conditions, and is 120 mm / sec. V1 is a gap in the most upstream exposure chip and is 110 mm / sec.

  Using the relationship shown in FIG. 54, as shown in FIG. 55, the scanning speed on the most upstream exposure chip and on the downstream exposure chip is controlled to optimum values, respectively, and nozzle scanning is performed. That is, the supply port of the chemical solution supply nozzle scans the nozzle at the scan speed V1 from the position P0 to the position P1, and after the position P2 at the scan speed V0. Between the positions P1 and P2, the scan speed is controlled to linearly increase from V1 to V0. The change in the scanning speed from the position P1 to the position P2 is not limited to this, and may be a change that provides the most uniformity, such as a change in a quadratic function.

  Thus, the reason why the developing speed can be adjusted by changing the scanning speed is that the staying time of the nozzle on the substrate can be changed. Specifically, since the liquid is sufficiently replaced by staying for a long time, the development speed can be accelerated. On the other hand, you can slow down by staying short. In this embodiment, since the adjustment is performed in a range (100 to 140 mm / sec) in which the replacement of the liquid by the residence time becomes dominant, the development can be promoted as the distance is shorter. However, according to another experiment, it was found that when the scanning speed is 200 mm / sec or more, the higher the scanning speed, the more the development is promoted. This is because the effect of liquid flow due to the force with which the nozzle draws liquid is greater than the staying time. Therefore, the scan speed for adjusting the development is preferably determined by obtaining the relationship between the pattern dimension and the scan speed in accordance with the conditions.

  As described above, the developer discharge conditions on the upstream exposure chip are determined using the relationship between the pattern dimensions and the control parameters (developer discharge conditions) for the downstream and uppermost exposure chips. Under these conditions, the most upstream exposure chip may be developed under different discharge conditions from the downstream exposure chip.

  When development processing was performed under the discharge amount conditions thus obtained, the uniformity of the resist pattern dimension between the exposed regions could be greatly improved.

(20th embodiment)
A substrate processing method according to the twentieth embodiment of the present invention will be described with reference to the drawings. In the twentieth embodiment, the concentration of the developer in the developing process is adjusted according to the exposure chip. That is, as in the nineteenth embodiment, the developing speed is adjusted so that the line dimensions of the resist pattern are equal between the uppermost exposure chip 1801A and the downstream exposure chip 1801B shown in FIG. Specifically, the developing speed of the most upstream exposure chip 1801A is increased by the following method.

  Similarly to the eleventh embodiment, an antireflection film having a thickness of 60 nm is formed on the wafer W, and a resist film having a thickness of 300 nm is formed on the antireflection film.

  Next, through the same exposure process as in the first embodiment, exposure chips including a 110 nm line-and-space pattern are arranged in a grid of 11 × 13 grids (excluding exposure chips outside the wafer range). Transferred onto the wafer to form a latent image. The exposure apparatus used in this embodiment uses an ArF excimer laser (wavelength 193 nm) as a light source. The exposure amount condition for each exposure chip is fixed.

As shown in the nineteenth embodiment with reference to FIGS. 47A and 47B, a resist pattern is formed. As a result, as shown in FIG. 56A, since the desired dimension is 110 nm (L0) in this embodiment, all the chips are exposed at 25.3 mJ / cm ² (D). However, the size of the most upstream exposure chip is 120 nm (L1). Therefore, the concentration of the developer at the most upstream exposure chip is raised. As a result, development is promoted, and the size of the most upstream exposure chip matches the size of the downstream exposure chip. Specifically, it is performed as follows.

  FIGS. 56B and 56C show a method of changing the concentration of the developer by blowing an air current with an air current blowing nozzle. In FIGS. 56B and 56C, 5601 is the most upstream exposure chip, and 5602 is the downstream exposure chip. During the static development, an airflow 5605 is blown by the airflow blowing nozzles 5603 and 5604 to the most upstream exposure chip 5601. Thereby, a part of water is evaporated, and the density | concentration of a developing solution is raised. This airflow spray nozzle can spray an airflow only on the most upstream exposure chip by blowing the airflow 5605 only from 5603. Reference numeral 5606 denotes a developer.

  There is a limit to the amount of water that can be evaporated using only airflow. Therefore, the thickness of the liquid is adjusted before blowing the airflow. That is, as shown in FIG. 57A, the developer 5701A is supplied. Next, as shown in FIG. 57B, the wafer W is rotated at 150 rpm for 2 seconds to form a thin film 5701B having a liquid thickness of 150 μm as shown in FIG. 57C. Thereafter, an air current is blown by an air blowing nozzle. By reducing the liquid thickness from 1 mm to 150 μm, the concentration can be greatly changed even with the same evaporation amount.

  FIG. 58 shows the relationship between the spray flow rate and the pattern size of the resist formed through the lithography process. The solid line in FIG. 58 shows the case of the downstream exposure chip, and the broken line shows the case of the most upstream exposure chip. Hereinafter, how to determine the flow rate of airflow will be described with reference to FIG. Here, the spray flow rate was a variable, and the distance between the nozzle and the wafer was constant at 15 mm. Under standard conditions, the flow rate was F0 (0 L / min), the downstream tip was finished in L0, and the most upstream tip was finished in L1. From this relationship, it can be seen that if the most upstream chip with a small amount of exposure is processed at a flow rate F1 (0.9 L / min), it is finished to a desired dimension (L0).

  As described above, using the relationship between the pattern size and the flow rate of the airflow in the case of the downstream and uppermost exposure chips, the downstream exposure chip and the uppermost exposure chip have the same dimensions on the upstream exposure chip. The flow rate of the airflow is determined. Development is performed under these conditions.

  When development processing was performed under the airflow conditions thus obtained, the uniformity of the resist pattern dimension between the exposed areas could be greatly improved.

(21st Embodiment)
A substrate processing method according to the twenty-first embodiment of the present invention will be described with reference to the drawings. In the twenty-first embodiment, the temperature of the developer in the development process is changed according to the exposure chip. As a result, development is promoted, and the pattern dimensions of the uppermost exposure chip and the downstream exposure chip match. In the combination of resist and developer used in the present embodiment, the development speed increases as the temperature increases. Therefore, development is promoted by increasing the temperature of the developer at the most upstream exposure chip. Specifically, the developing speed of the most upstream exposure chip 1801A shown in FIG. 18 is increased by the following method.

  The process up to exposure is the same as in the eleventh embodiment. Next, as shown in FIGS. 59A and 59B, the uppermost exposure chip 5901 is heated from the lower surface of the wafer by the hot plates 5903 and 5904 during the static development, and the temperature of the developer 5905 is increased. By inputting power only to the hot plate 5903, only the most upstream exposure chip 5901 can be heated.

  FIG. 60 shows the relationship between the developer temperature and pattern dimensions. The solid line in FIG. 60 shows the case of the downstream exposure chip, and the broken line shows the case of the most upstream exposure chip. Hereinafter, the method of determining the temperature will be described with reference to FIG. After the developer film is formed, a hot plate heated to a predetermined temperature is brought into contact with the back surface of the wafer for 40 seconds from 10 seconds after the liquid film is formed. Under standard conditions, the temperature is T0 (23 ° C.), the downstream tip is finished at L0, and the most upstream tip is finished at L1. From this relationship, it can be seen that if the processing is performed at the hot plate temperature T1 (28 ° C.) of the most upstream chip, it is finished to a desired dimension (L0).

  As described above, using the relationship between the pattern size and the hot plate temperature in the case of the downstream and uppermost exposure chip, the hot plate in the upstream exposure chip is set so that the downstream exposure chip and the uppermost exposure chip have the same size. The temperature is determined. Development is performed under these conditions.

  In the case of a positive resist, if the developing speed increases when the developing solution temperature is lowered, the temperature of the hot plate is adjusted so as to lower the temperature of the developing solution of the most upstream exposure chip.

  In this embodiment, the temperature is adjusted by heating from the back surface of the wafer with a hot plate. Alternatively, heating may be performed from the upper surface of the wafer with a lamp heater.

  When development processing was performed under the temperature conditions thus obtained, the uniformity of the resist pattern dimension between the exposed regions could be greatly improved.

(Twenty-second embodiment)
A substrate processing method according to the twenty-second embodiment of the present invention will be described with reference to the drawings. In the twenty-second embodiment, the developing speed is adjusted by giving a distribution to the discharge amount of the developer. Unlike the nineteenth to twenty-first embodiments, the airflow direction in the heating process (PEB treatment process) after exposure is different from that in the nineteenth to twenty-first embodiments. Specifically, as shown in FIG.

  For the reasons described above, the line size of the resist pattern formed after development is larger in the most upstream exposure chip 3902 than in the downstream exposure chip 3901. Therefore, the resist pattern development speed on the wafer is adjusted so that the uppermost exposure chip 3902 and the downstream exposure chip 3901 have equal line dimensions of the resist pattern formed after development. Specifically, the developing speed of the most upstream exposure chip 3902 is increased by the following method.

  The process up to exposure is the same as in the eleventh embodiment. Next, as shown in FIGS. 61A and 61B, the linear chemical solution supply nozzle 6101 is stopped at substantially the center of the wafer W, and the wafer W is rotated while discharging the chemical solution. As a result, a chemical film 6103 is formed on the substrate to be processed. At this time, the discharge amount of the nozzle, the distance between the nozzle and the wafer, and the rotation speed of the substrate are 1.0 L / min, 1.5 mm, and 40 rpm. Thereafter, after static development for 60 seconds, a rinsing process and a spin drying process are performed to form a uniform resist pattern.

  When it is desired to process the wafer surface more uniformly, the distribution of the discharge amount is provided in the radial direction as shown in FIGS. 62A and 62B so that the same amount can be supplied per unit area. 62A and 62B, 6201A is the most upstream exposure chip, 6201B is the downstream exposure chip, and 6203 and 6204 are developing solutions. Specifically, as shown by the solid line in FIG. 62C, the discharge amount is increased in accordance with the distance from the center.

  As shown in the nineteenth embodiment, after a normal exposure process, the relationship between the exposure amount and the resist line dimension shown in FIG. 48 is obtained. Therefore, in this embodiment, as shown by the broken line in FIG. 62C, the discharge amount at the uppermost exposure chip is set to be larger than the discharge amount (solid line) under the condition for uniformly processing. The region ejected by the ejection amount indicated by the broken line corresponds to 6202B in FIG. 62A, and the region ejected by the other ejection amount corresponds to 6202A. Thereby, the dimension of the most upstream exposure chip can be matched with the dimension of the downstream exposure chip.

  As described above, the discharge amount of the developer at the most upstream exposure chip is set to be larger than that in the case of uniform processing. As a result, the development speed of the most upstream exposure chip is increased, and the dimension of the most upstream exposure chip can be matched with the dimension of the downstream exposure chip.

  Further, in this embodiment, the developing speed of the uppermost exposure chip and the downstream exposure chip is made the same by changing the discharge amount from the chemical solution supply nozzle. However, as shown in the twentieth embodiment, the density is changed. It is possible. In this case, the airflow may be blown by the airflow blowing nozzles 5603 and 5604. Further, as shown in the twenty-first embodiment, it is also possible to change the temperature. In this case, the heating plate 5903, 5904 may be heated.

  When development processing was performed under the discharge conditions thus obtained, the uniformity of the resist pattern dimension between the exposed areas could be greatly improved.

(23rd embodiment)
A substrate processing method according to the twenty-third embodiment of the present invention will be described with reference to the drawings. In the twenty-third embodiment, the development speed is adjusted using a hydrophilic treatment. That is, the most upstream exposure chip region 3902 shown in FIG. 39 is made more hydrophilic than the downstream exposure chip region 3901. As a result, the development speed of the most upstream exposure chip region 3902 can be increased. Specifically, it is performed as follows. In addition, the direction of the airflow in the PEB processing step is the same as that in the twenty-second embodiment.

  The process up to exposure is the same as in the eleventh embodiment. Next, as shown in FIG. 63, ozone water 6303 in which 1 ppm of ozone molecules is dissolved is supplied from the straight nozzle 6301 before supplying the developer. As a result, the resist film surface is hydrophilized. Ozone water should just be 5 ppm or less.

  With the wafer W rotated at 500 rpm, the straight nozzle is positioned at the center of the substrate (6301 in the figure). Here, ozone water 6303 is discharged from the straight nozzle for 1 second. In the ejected state, it is moved to the outer periphery at 100 mm / sec (6302 in the figure). Here, the straight nozzle is kept stationary for a certain period of time (hereinafter referred to as staying time at the outer periphery). By supplying more ozone water to the outer peripheral portion, the outer peripheral portion is made more hydrophilic. After a certain period of time, the discharge of ozone water is stopped and the substrate is rotated to dry the substrate.

  Thereafter, as shown in FIGS. 47A and 47B, a linear chemical solution supply nozzle 4702 is used to discharge the chemical solution from one end (start position in the drawing) to the other end (in the drawing). Scan to the end position. As a result, a chemical film 4702 is formed on the wafer W. A developer film is formed with the nozzle discharge amount, the distance between the nozzle and the wafer, and the nozzle scanning speed being constant (1.0 L / min, 1.5 mm, and 120 mm / sec, respectively). Thereafter, a static development for 60 seconds, a rinsing process, and a spin drying process are performed to form a resist pattern.

  As shown in FIG. 48, in this embodiment, since the desired dimension is 150 nm (L0), all the chips were exposed at 17.5 mJ / cm 2 (D). However, since the effective exposure amount is reduced in the most upstream exposure chip, the dimension is 158 nm (L1). Therefore, the dimensions are adjusted by optimizing the stay time of the outer periphery.

  FIG. 64 shows the relationship between the outer peripheral portion residence time and the pattern size in the most upstream exposure chip. Under the condition of stay time t0 (= 0 seconds), the downstream chip is finished in L0 and the most upstream chip is finished in L1. From this relationship, it can be seen that if the processing is performed with the stay time t1 (= 3 seconds), the desired dimension (L0) is obtained.

  As described above, the development speed at the most upstream exposure chip is increased by making the resist surface at the most upstream exposure chip more hydrophilic. As a result, it is possible to match the size of the most upstream exposure chip with the size of the downstream exposure chip.

  In this embodiment, ozone water is used to make it hydrophilic, but this is not a limitation. Pure water or oxygenated water such as oxygen water, carbon monoxide water or hydrogen peroxide water also has a hydrophilic effect and can be applied.

  In the eighteenth, twenty-second, and twenty-third embodiments, the exhaust flow during PEB has been described as being unidirectional, but the present invention is not limited to this. Correction can be made in the same procedure using a PEB unit having a radial airflow from the wafer periphery to the center or from the center to the periphery.

  In the nineteenth and twenty-first to twenty-third embodiments, examples of chemically amplified resists for KrF excimer lasers have been shown. However, it is not limited to these. That is, the present invention can also be applied to an ArF resist. In the twentieth embodiment, an example of a chemically amplified resist for ArF excimer laser is shown. However, it is not limited to these. That is, it can be applied to a KrF resist. Furthermore, the present invention can be applied to F2 resist, EB resist, EUV resist, and the like through the nineteenth to twenty-third embodiments.

  In the first to twenty-third embodiments, the 140 nm isolated line pattern and the line and space pattern have been described. However, the present invention is not limited to this, and the present invention can be applied to formation of a hole pattern or the like.

  In the first to 23rd embodiments, an excimer laser is used for exposure. However, the present invention is not limited to this, and ultraviolet rays, far ultraviolet rays, vacuum ultraviolet rays, electron beams, and X-rays can also be used.

  Of course, the present invention can be applied not only to the positive chemically amplified resist described in the above embodiment but also to a negative chemically amplified resist. In the nineteenth to twenty-third embodiments, in the case of a negative resist, each control is performed so as to slow down the developing speed of the most upstream exposure chip. That is, in the nineteenth and twenty-second embodiments, the developer discharge conditions are controlled. In the twentieth embodiment, an air stream is blown to the downstream exposure chip so that the development speed of the most upstream exposure chip is relatively slow. In the twenty-first embodiment, the temperature of the developer is adjusted. In the twenty-third embodiment, the surface state of the resist of the developer is adjusted.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

The top view which shows typically the substrate processing apparatus concerning each embodiment of this invention. Sectional drawing which shows typically the heating apparatus concerning the 1st Embodiment of this invention. The figure which shows the pattern obtained when transferring the mask for exposure to a wafer. The figure which expands and shows the line pattern area | region in the pattern of FIG. The figure which shows the state which has arrange | positioned the exposure chip | tip on a wafer. The figure which shows the wafer surface distribution of the quality of the pattern transfer result obtained using the heating apparatus concerning the 1st Embodiment of this invention. Sectional drawing which shows typically the heating apparatus concerning the 2nd Embodiment of this invention. The figure which shows the relationship between the porosity and the reattachment of the evaporation substance, the relationship between the distance (gap) between the adsorption plate and the soaking plate, and the evaporation distance of the acid. Sectional drawing which shows typically the heating apparatus concerning the 3rd Embodiment of this invention. Sectional drawing which shows typically the heating apparatus concerning the 4th Embodiment of this invention. Sectional drawing which shows typically the heating apparatus concerning the 5th Embodiment of this invention. Sectional drawing which shows typically the heating apparatus concerning the 6th Embodiment of this invention. The figure which shows a board member. Sectional drawing which shows typically the heating apparatus concerning the 7th Embodiment of this invention. Sectional drawing which shows typically the heating apparatus concerning the 8th Embodiment of this invention. Sectional drawing which shows typically the heating apparatus concerning the 9th Embodiment of this invention. Sectional drawing which shows typically the heating apparatus concerning the 10th Embodiment of this invention. The figure which shows the positional relationship of the airflow direction in PEB, and each exposure chip. The figure which shows the relationship between the exposure amount and the resist line dimension in the substrate processing method concerning the 11th Embodiment of this invention. The figure which shows typically the positional relationship of arrangement | positioning of a heating unit group, and a wafer conveyance arm. The figure which looked at the state which conveys a wafer to the heating apparatus for PEB from the upper direction. The figure which shows typically the positional relationship of arrangement | positioning of a heating unit group, and a wafer conveyance arm. The figure which looked at the state which conveys a wafer to the heating apparatus for PEB from the upper direction. The figure which looked at the state which conveys a wafer to the heating apparatus for PEB from the upper direction. The figure which shows the relationship between the PEB process temperature and the resist line dimension in the resist pattern formation method of the 12th Embodiment of this invention. The figure which shows the positional relationship of an airflow direction and an exposure chip. The figure which shows the positional relationship of an airflow direction and an exposure chip. The figure which shows typically the relative positional relationship of an exposure area | region and the airflow at the time of PEB. The figure which shows typically the relationship between the position X in a chip | tip when it is set as the exposure amount D, and the resist pattern dimension (line dimension) after image development. The figure which shows the relationship between the pattern dimension in the exposure amount D vicinity, and exposure amount. The figure which shows typically the relationship between the position X in a chip | tip, and exposure amount. The figure which shows typically the relationship between the position X in a chip | tip, and a scanning speed. The figure which shows the structure of the projection exposure apparatus of a step and scan system. The figure which shows typically the transmittance | permeability distribution of ND filter 3303 for irradiation amount adjustment. The figure which shows a part of exposure area | region typically. The figure which shows the relationship between exposure amount and a line dimension. The figure which shows typically the light irradiation system for exposure amount adjustment. The figure which shows typically the positional relationship of the exposure area group 3801 formed on the wafer, and the light irradiation area | region 3802 irradiated at the time of correction | amendment. The figure which shows the positional relationship of an airflow direction and an exposure chip. The figure which shows the relationship of the irradiation amount irradiated at the time of a correction | amendment, and the dimensional difference between an outermost periphery (most upstream) exposure area | region and an inner periphery (downstream) exposure area | region. The figure which shows the other Example of the substrate processing method concerning the 17th Embodiment of this invention. The figure which shows the relationship between the position X in a chip | tip and irradiation energy in the Example shown in FIG. The figure which shows the state which has arrange | positioned the exposure chip | tip on a wafer. The figure which shows the positional relationship of an airflow direction and an exposure chip. The figure which shows the state which has arrange | positioned the exposure chip | tip on a wafer. The figure which shows the relationship between the area of a missing exposure area | region, and EB irradiation amount required in order to correct | amend pattern dimension fluctuation | variation. The figure which shows the supply method of a developing solution typically. The figure which shows the relationship between an exposure amount and a pattern dimension. The figure which shows the relationship between the discharge amount of a developing solution, and a pattern dimension. The figure which shows the position of a chemical | medical solution supply nozzle. The figure which shows the relationship between a nozzle position and the discharge amount of a developing solution. The figure which shows the relationship between the distance (it describes with a gap in a figure) between a wafer and a nozzle, and a pattern dimension. The figure which shows the relationship between a position and a gap. The figure which shows the relationship between a nozzle scanning speed and a pattern dimension. The figure which shows the relationship between a nozzle position and a scanning speed. The figure which shows the relationship between the discharge amount of a developing solution, and a pattern dimension, The figure which shows typically a mode that an airflow is sprayed by an airflow spray nozzle. The figure explaining thinning of a developing solution. The figure which shows the relationship between spraying flow volume and a pattern dimension. The figure which shows a mode that a board | substrate is heated with a hot plate. The figure which shows the relationship between the temperature of a developing solution, and a pattern dimension. The figure which shows the supply method of a developing solution typically. The figure which shows typically the method of controlling the discharge amount by the location of a nozzle. The figure which shows the supply method of ozone water typically. The figure which shows the relationship between a pattern dimension and the supply time in an outer peripheral part. Sectional drawing which shows the conventional heating apparatus typically. The figure which shows the positional relationship of the airflow direction in the conventional heat processing, and an exposure chip | tip. The figure which shows the in-plane distribution of the quality of the pattern transfer result obtained by heat-processing using the conventional heating apparatus.

Explanation of symbols

201 ... housing, 202 ... soaking plate, 203 ... heater, 204 ... insulating material, 205 ... frame, 206 ... proximity gap, 207 ... top plate, 208 ... chamber, 209 ... porous ceramic plate, 210 ... space, 211: 1st space part, 212 ... 2nd space part, 213 ... Support pin, 214 ... Elevating mechanism, 215 ... Air introduction port, 216 ... Exhaust port, 217 ... Airflow, 220 ... Exhaust means.

Claims (42)

A resist forming means for forming a chemically amplified resist film on the substrate to be processed;
Exposure means for irradiating the chemically amplified resist film with energy rays to form an exposure region having a latent image pattern;
Rotation correction means for rotating the direction of the substrate to be processed;
A heat treatment means for heating the chemically amplified resist film while flowing an air flow in one direction along the substrate to be treated;
Developing means for developing the chemically amplified resist film;
An apparatus for processing a resist film, comprising: Forming a chemically amplified resist film on the substrate to be processed;
Exposing to form an exposure region having a latent image pattern by irradiating the chemically amplified resist film with energy rays; and
Heating the chemically amplified resist film;
Developing the chemically amplified resist film;
In the substrate processing method for carrying out the steps in this order,
In accordance with the change in the effective energy amount caused by the change in the balance between the amount of the evaporated material evaporating from the chemically amplified resist film and the amount of the evaporated material reattached during the heating step, A resist pattern forming method, wherein the amount of energy irradiated to the exposure region is corrected before the heating step. Forming a chemically amplified resist film on the substrate to be processed;
An exposure process for forming an exposure region having a latent image pattern by irradiating the chemically amplified resist film with energy rays selected from the group consisting of ultraviolet rays, far ultraviolet rays, vacuum ultraviolet rays, electron beams, and X-rays. When,
Heating the chemically amplified resist film in the presence of airflow;
Developing the chemically amplified resist film;
In the substrate processing method for carrying out the steps in this order,
In response to a change in the effective first energy amount caused by a change in the balance between the amount of evaporate evaporated from the chemically amplified resist film and the amount of reattachment of the evaporant during the heating step A method for forming a resist pattern, wherein the amount of energy applied to the exposure region is corrected before the heating step.   4. The method of forming a resist pattern according to claim 3, wherein the correction of the energy amount is performed by adjusting an exposure amount during the exposure step.   The resist pattern forming method according to claim 4, wherein the adjustment of the exposure amount is performed within the exposure region.   The resist pattern forming method according to claim 5, wherein the adjustment of the exposure amount is performed based on a coverage of a resist pattern to be formed. The exposure area is formed by reducing and projecting a pattern on a projection exposure substrate onto a substrate to be processed with a scanning exposure apparatus,
The adjustment of the irradiation amount condition of the energy beam is performed by adjusting a scanning speed of the projection exposure substrate and the substrate to be processed in the scanning exposure apparatus, and incident incident on the projection substrate in the scanning exposure apparatus. 6. The resist pattern forming method according to claim 5, wherein the resist pattern forming method is performed by a method selected from the group consisting of adjusting an energy amount.   The exposure amount of the uppermost exposure area where no exposure area exists on the upstream side with respect to the airflow direction is adjusted to be substantially higher than the downstream exposure areas other than the uppermost exposure area. The resist pattern forming method according to claim 4, wherein: The correction of the energy amount is performed separately from the exposing step, and
The resist pattern forming method according to claim 3, wherein the resist pattern forming method is performed by irradiating the exposure area with an energy amount corresponding to a change in the first energy amount.   The step of irradiating the exposure region with an energy amount corresponding to a change in the first energy amount is selected from the group consisting of a lamp, a laser, and an electron beam having a wavelength at which the chemically amplified resist film is exposed. The resist pattern forming method according to claim 9, wherein the resist pattern forming method is performed by irradiating any one of them.   4. The resist pattern forming method according to claim 3, wherein the energy amount is corrected based on correction amounts sequentially calculated from the upstream side to the downstream side with respect to the airflow. Forming a chemically amplified resist film on the substrate to be processed;
Exposing to form an exposure region having a latent image pattern by irradiating the chemically amplified resist film with energy rays; and
Heating the chemically amplified resist film;
Developing the chemically amplified resist film;
In the resist pattern forming method for carrying out the steps in this order,
In accordance with the change in the effective energy amount caused by the change in the balance between the amount of the evaporated material evaporating from the chemically amplified resist film and the amount of the evaporated material reattached during the heating step, A resist pattern forming method, wherein the amount of energy supplied to the exposure region is corrected during the heating step. Forming a chemically amplified resist film on the substrate to be processed;
An exposure process for forming an exposure region having a latent image pattern by irradiating the chemically amplified resist film with energy rays selected from the group consisting of ultraviolet rays, far ultraviolet rays, vacuum ultraviolet rays, electron beams, and X-rays. When,
Heating the chemically amplified resist film in the presence of airflow;
Developing the chemically amplified resist film;
In the resist pattern forming method for carrying out the steps in this order,
In accordance with a change in the effective first energy amount caused by a change in the balance between the amount of the evaporate evaporated from the chemically amplified resist film and the amount of the evaporant reattached during the heating step. The method of forming a resist pattern, wherein the amount of energy supplied to the exposure region is corrected during the heating step.   The resist pattern forming method according to claim 13, wherein the correction of the energy amount is performed by a heat amount of heating.   In the heating step, the uppermost exposure area where no exposure area exists on the upstream side with respect to the direction of the airflow is substantially higher in energy than the downstream exposure area other than the uppermost exposure area. 14. The resist pattern forming method according to claim 13, wherein the amount of energy supplied to the exposure region is corrected.   The resist pattern forming method according to claim 3, wherein the airflow is in one direction along the substrate to be processed.   The resist pattern forming method according to claim 13, wherein the correction of the energy is performed based on correction amounts sequentially calculated from the upstream side to the downstream side with respect to the airflow.   14. The resist pattern forming method according to claim 3, further comprising a step of rotating the substrate to be processed between the exposing step and the heating step. Forming a chemically amplified resist film on the substrate to be processed;
Irradiating the chemically amplified resist film with energy rays, thereby exposing to form an exposure region having a latent image pattern; and
Heating the chemically amplified resist film in the presence of airflow;
Developing to form a desired resist pattern by supplying a developing solution to the chemically amplified resist film from a chemical supply nozzle; and
In the resist pattern forming method for carrying out the steps in this order,
Due to the distribution of the effective energy amount caused by the change in the balance between the amount of the evaporated material evaporating from the chemically amplified resist film during the heating step and the amount of the evaporated material reattached, and the distribution A resist pattern forming method, comprising: adjusting a developing speed of a resist pattern in the substrate to be processed in the developing step according to a value selected from a group consisting of resist pattern dimension fluctuations.   The adjustment of the developing speed is performed by discharging the chemical supply nozzle in the direction of the air flow during the heating so as to compensate for the loss of the evaporant in the most upstream exposure area where no exposure area exists on the upstream side. The resist pattern forming method according to claim 19, wherein the developing condition is changed by changing a discharge condition of the developing solution in the uppermost exposure area and a downstream exposure area other than the uppermost exposure area.   When the chemically amplified resist film is a positive type, the adjustment of the development speed promotes development in the most upstream exposure area or suppresses development in the downstream exposure area. 21. The resist pattern forming method according to claim 20, wherein the resist pattern forming method is performed by changing ejection conditions in an exposure region and the downstream exposure region.   When the chemically amplified resist film is a negative type, the adjustment of the development speed may suppress the development in the most upstream exposure area or promote the development in the downstream exposure area. 21. The resist pattern forming method according to claim 20, wherein the resist pattern forming method is performed by changing ejection conditions in an exposure region and the downstream exposure region. The adjustment of the development speed is
Determining the relationship between the developer discharge conditions and the pattern dimensions in the case of the uppermost exposure area and the case of the downstream exposure area;
Determining the discharge conditions of the developer in the most upstream exposure area and the downstream exposure area so that the pattern dimension in the most upstream exposure area is equal to the pattern dimension in the downstream exposure area;
Discharging the developer under the determined discharge conditions;
The resist pattern forming method according to claim 20, further comprising: The supply method of the developer comprises a method of forming a liquid film by scanning the nozzle from one end to the other end on the substrate to be processed in a state where the developer is discharged from a linear chemical solution supply nozzle. And
21. The resist according to claim 20, wherein the discharge condition is based on a value selected from the group consisting of a scanning speed of the nozzle, a discharge amount of the developer, and a distance between the nozzle and the substrate to be processed. Pattern forming method. The direction of the airflow is a direction selected from the group consisting of a center direction of the substrate to be processed and an outer periphery direction, and an outer periphery to the center direction,
The developing solution supply method includes a step of forming a liquid film by rotating a substrate to be processed while disposing a linear chemical solution supply nozzle at the center of the substrate to be processed and discharging the developing solution from the nozzle. And
21. The resist pattern forming method according to claim 20, wherein the adjustment of the developing speed is controlled by a discharge amount distribution of a nozzle.   The adjustment of the development speed is such that the development of the uppermost exposure area with respect to the air flow direction during the heating is performed so as to compensate for the loss of the evaporant in the uppermost exposure area where no exposure area exists on the upstream side. The resist pattern forming method according to claim 19, wherein the resist pattern forming method is performed by adjusting a liquid temperature and a developer temperature in a downstream exposure area other than the most upstream exposure area.   When the chemically amplified resist film is a positive type, the adjustment of the development speed promotes development in the most upstream exposure area or suppresses development in the downstream exposure area. 27. The resist pattern forming method according to claim 26, wherein the resist pattern forming method is performed by changing a developing solution temperature in the exposure area and the downstream exposure area.   When the chemically amplified resist film is a negative type, the adjustment of the development speed may suppress the development in the most upstream exposure area or promote the development in the downstream exposure area. 27. The resist pattern forming method according to claim 26, wherein the resist pattern forming method is performed by changing a developing solution temperature in the exposure area and the downstream exposure area. The adjustment of the development speed is
Determining the relationship between the developer temperature and the pattern dimension in the case of the uppermost exposure area and the case of the downstream exposure area;
Determining development temperatures of the most upstream exposure area and the downstream exposure area so that the pattern dimension of the most upstream exposure area is equal to the pattern dimension of the downstream exposure area;
Adjusting to the determined developer temperature;
27. The method of forming a resist pattern according to claim 26, further comprising:   27. The resist pattern forming method according to claim 26, wherein the adjustment of the developing solution temperature is performed from the lower surface of the substrate to be processed using a heat source selected from the group consisting of a hot plate and a lamp heater.   27. The resist pattern forming method according to claim 26, wherein the adjustment of the developer temperature is performed using a lamp heater from the upper surface of the substrate to be processed.   The adjustment of the developing speed is performed by adjusting the developer concentration in the uppermost exposure area where no exposure area exists upstream with respect to the airflow direction and the developer concentration in the downstream exposure area other than the uppermost exposure area. The resist pattern forming method according to claim 19, wherein the resist pattern forming method is performed by adjusting.   When the chemically amplified resist film is a positive type, the adjustment of the development speed promotes development in the most upstream exposure area or suppresses development in the downstream exposure area. The resist pattern forming method according to claim 32, wherein the resist pattern forming method is performed by changing a developer concentration in an exposure area and the downstream exposure area.   When the chemically amplified resist film is a negative type, the adjustment of the development speed may suppress the development in the most upstream exposure area or promote the development in the downstream exposure area. The resist pattern forming method according to claim 32, wherein the resist pattern forming method is performed by changing a developer concentration in an exposure area and the downstream exposure area. The adjustment of the development speed is
Determining the relationship between the developer concentration and the pattern dimension in the case of the uppermost exposure area and the case of the downstream exposure area;
Determining the developer concentration of the most upstream exposure area and the downstream exposure area so that the pattern dimension of the most upstream exposure area is equal to the pattern dimension of the downstream exposure area;
Adjusting to the determined developer concentration;
The resist pattern forming method according to claim 32, further comprising:   33. The resist pattern forming method according to claim 32, wherein the adjustment of the developer concentration is performed by blowing an air flow from the upper surface of the substrate to be processed to the developer surface. The adjustment of the developer concentration is
Thinning the developer film on the substrate to be processed;
A step of blowing an air current on the developer surface;
The resist pattern forming method according to claim 32, further comprising: When the direction of the airflow is a direction selected from the group consisting of the center to the outer periphery direction and the outer periphery to the center direction along the substrate to be processed, the adjustment of the developing speed is performed before supplying the developer in the developing step. In addition,
Supply liquid to the surface of the resist film,
Adjusting the surface state of the most upstream exposure region and the surface state of the downstream exposure region other than the most upstream exposure region with respect to the direction of the airflow;
The resist pattern forming method according to claim 19, further comprising:   The method of forming a resist pattern according to claim 38, wherein the liquid is pure water.   The method of forming a resist pattern according to claim 38, wherein the liquid is an oxidizing liquid.   41. The method of forming a resist pattern according to claim 40, wherein the oxidizing liquid is an aqueous solution selected from a group consisting of ozone, oxygen, carbon monoxide, and hydrogen peroxide.   41. The resist pattern forming method according to claim 40, wherein the oxidizing liquid is ozone water of 5 ppm or less.

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