JP2000349018A - Bake furnace for photoresist - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bake furnace which can manufacture a wafer which is equal in line width by dissolving the inequality of the line width at the surface of a wafer where a developer is applied. SOLUTION: Heating of the wafer 12 within a bake furnace 11 is performed, using a plurality of heating heaters 13, 14, and 15 arranged concentrically. At that time, the temperature control of each heater is performed, using exclusive temperature controllers 16, 17, and 18, and the heating of a wafer is performed at different temperatures. The power of attack by the position and the power of this temperature are offset with each other, and a wafer having a photoresist equal in line width can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a baking furnace capable of developing a wafer while suppressing variations in photoresist line width.

[0002]

2. Description of the Related Art Along with miniaturization of semiconductor pattern rules, a photoresist wafer used for etching an insulating layer (SiO ₂ layer) in order to accurately form each semiconductor electrode on a semiconductor substrate. Improvement of in-plane dimensional uniformity is becoming increasingly important. In the etching, a photoresist made of a photosensitive resin or the like is applied to a substrate coated with an insulating layer, a mask is coated on the photoresist, and exposure and development are performed to form a predetermined pattern. Bake process (Post Exposure Bake, PEB) from the end of exposure to just before development in developing this photoresist
A baking furnace is used for the baking.

FIG. 6 shows a conventional baking furnace for PEB, FIG. 6 (a) is a schematic longitudinal sectional view thereof, and FIG. 6 (b) is a transverse sectional view thereof. In FIG. 6, the wafer is depicted as being transparent for clarity. As shown in FIG. 6, a conventional PEB baking furnace 31 heats a disk-shaped wafer 32 accommodated in the baking furnace 31 by upper and lower heaters 33, and controls the heater 33 by baking. Since the temperature control apparatus 36 accommodates only one furnace per furnace, the temperature distribution on the surface of the wafer 32 could not be controlled. In this case, the surface temperature of the wafer is generally uniform regardless of the position on the wafer. Therefore, the control temperature of the heater of the conventional baking furnace is, as shown in FIG. It is almost constant without dependence, and is about 150 ° C. in FIG. For this reason, the temperature of the wafer surface is almost constant without depending on the distance from the center of the wafer, as shown in FIG. 8, and is about 150 ° C., similar to the control temperature of the heater. FIGS. 7 and 8 are graphs showing the relationship between the distance and the control temperature of the heater, with one being a positive distance and the other being a negative distance, with the wafer center being 0, and the relationship between the distance and the wafer temperature.

[0004]

When the temperature of the wafer surface is constant, the line width of the formed photoresist varies depending on the distance from the center of the wafer. FIG. 9 shows the in-plane line width variation of a typical annealing type photoresist. FIG. 9 shows that the standard value of the line width of the photoresist after development of the wafer coated with the developing solution and the standard value is 100, with the center of the wafer being 0, one being a positive distance and the other being a negative distance. 9 is a graph showing a relationship between a change in line width and a value expressed as a percentage when coordinates are set to 0. As shown in the figure, the line width is small near the center of the wafer, and conversely, the line width is large near the periphery. The line width varies in this manner because the annealing type photoresist is easily affected by in-plane non-uniformity when the developing solution is filled.

As apparent from FIG. 9, the line width of the wafer coated with the developing solution is narrower toward the center thereof, and is reduced by about 13% from the standard value. Conversely, as one approaches the periphery (a distance of about 100 mm), the line width increases and increases by about 15% from the standard value, with a difference of about 28%. This variation in line width is fatal in a normal wafer manufacturing process. That is, when the developer is filled, the developer is attacked for a relatively long time near the center of the wafer, whereas the attack of the developer is short for the peripheral portion. Due to the above reasons, in-plane line width variations concentrically distributed at a rate of about 20% of the standard line width occur. The degree of this variation is fatal in a normal device manufacturing process. Generally, in order to obtain a good wafer, the line width of the photoresist immediately before development is almost constant, and at least 10% or less. Needs to be suppressed.

Various other methods have been proposed to make the line width of the photoresist uniform (see, for example,
The technique described in this publication attempts to suppress the line width variation due to fluidization of the material by light irradiation. There is no technology that can solve the problem caused by the influence of the in-plane non-uniformity at the time of filling the developer with the other conventional technologies. An object of the present invention is to provide a baking furnace capable of eliminating a non-uniformity of line width on a wafer surface coated with the developing solution, which is a problem in the prior art, and manufacturing a wafer having a uniform line width. I do.

[0007]

SUMMARY OF THE INVENTION The present invention provides a photoresist baking furnace for heating and developing a wafer on which a photoresist pattern has been formed, wherein a plurality of heaters are installed in close proximity to the wafer. Baking furnace for photoresist, wherein a temperature distribution of the wafer is controlled by heating the heaters at different temperatures so as to generate a temperature distribution in which the center portion is low and the peripheral portion is high in the wafer. Are desirably arranged concentrically.

Hereinafter, the present invention will be described in detail. The present invention
The present invention relates to a baking furnace that can be used in an exposure step and a developing step in a semiconductor manufacturing process, and particularly to a baking furnace that improves in-plane line width variation of a photoresist due to in-plane non-uniformity when a developer is filled. It is. Chemically amplified resists called annealing type (or high temperature bake type) are susceptible to in-plane non-uniformity when the developer is filled, and this causes the concentric circles to be about 20% of the standard line width. A distribution of in-plane line width distribution occurs.
Even this degree of variation is fatal in a normal device process.

The line width distribution on the surface of the wafer coated with the developer as shown in FIG. 9 is caused by the conventional photoresist baking furnace which is heated by a single heater as shown in FIG. Because there was. Therefore, in the present invention, a plurality of, and preferably concentric, heaters of the baking furnace for the PEB process performed after the end of the exposure and before the development are arranged in one baking furnace, and the respective heaters are arranged at different temperatures at the center. By controlling the lower edge to be higher, a temperature distribution is generated on the wafer. Since the line width of the annealing type photoresist can be easily controlled by the PEB temperature, the temperature distribution cancels out the in-plane line width variation caused by the in-plane non-uniformity when the developing solution is filled, and makes the line width uniform. It is possible to do. In the present invention, if there is a difference in heating temperature between the central portion and the peripheral portion of the wafer, the effect of suppressing line width variation also occurs more or less. For example, in addition to the concentric shape, one heater at the center is provided at the peripheral portion. Two heaters that are not donut-shaped may be installed.

As described above, in the present invention, a plurality of heaters are used, and a wafer is locally controlled by each heater.
By heating the wafer as a whole with all the heaters, it is intended to eliminate variations in line width as shown in FIG. Since variations in the line width on the wafer surface occur concentrically, it is desirable in the present invention that a plurality of heaters be arranged concentrically. When the heater closer to the center has a lower heating temperature and the peripheral heater has a higher heating temperature, a valley-shaped temperature distribution is obtained.
Variations in line width are eliminated, and a wafer having a uniform line width can be manufactured.

The heater used in the present invention may be placed or contacted with a wafer at a distance, and in the present invention, it is referred to as "close" in both aspects. In a normal baking furnace, the wafer is supported by heat-resistant pins and is substantially suspended. Therefore, the heat generated by the heater is indirectly transmitted to the wafer by radiation or convection, so that it takes about 45 seconds after the wafer is placed in a baking furnace until the temperature of the wafer surface reaches a steady state. For this reason, when PEB processing is performed using this type of baking furnace, P
An EB time of about 90 seconds is required, but it is desirable that the processing can be performed in a short time as much as possible in consideration of the throughput in manufacturing.

When the wafer is kept in contact with the heater, the time required for the surface temperature of the wafer to reach a steady state is about 15 seconds, and when the wafer and the heater are installed at a distance of about 10 mm, there is a problem. Decrease to / 3. Therefore, the total PEB time of about 60 seconds is sufficient, and the manufacturing time can be reduced. Furthermore, when the wafer and the heater are set apart from each other, it is preferable to install a heater above and below the wafer in order to secure heating efficiency. Since the heating is performed reliably, the line width can be sufficiently made uniform with either one of the upper and lower heaters.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a photoresist baking furnace according to the present invention will be described with reference to FIG. FIG. 1 shows a first embodiment of a photoresist baking furnace according to the present invention. FIG. 1 (a) is a schematic longitudinal sectional view thereof, and FIG. 1 (b) is a plan view thereof. In FIG. 1, the wafer is depicted as being transparent for clarity. The short cylindrical baking furnace 11 has a wafer 12 installed horizontally in the inside thereof and held substantially at the center by three heat-resistant pins 20. A first heater 13 having a circular shape in the center in plan view with a small space above and below the wafer 12, a second doughnut-shaped heater 14 installed so as to be substantially aligned with the periphery of the heater 13, and A doughnut-shaped third heater installed so as to be substantially aligned with the periphery of the heater 14
15 are installed, and each heater is arranged concentrically. It is desirable to use a single metal such as Pt, an alloy such as Ni-Cr, or a ceramic such as a Si-C compound as a heating element of each heater.

The heaters 13, 14, and 15 are connected to dedicated temperature controllers 16, 17, and 18, respectively, so that they can be controlled at different temperatures. Generally, an S-type or K-type thermocouple is used for temperature measurement for temperature control, and a PID control method is used for a sequence for temperature control. The heater control temperature changes abruptly at the boundary between each heater, but the wafer and the heater are usually arranged at a distance of about 10 mm as described above, and a stainless steel alloy or the like is interposed between the two. It is possible to dispose a thermally conductive cover 19 to generate a gentle temperature distribution.

As described above, it is desirable that the heaters are arranged in a vertically symmetrical position with respect to the wafer, and that the heaters corresponding to the same upper and lower positions are controlled to the same temperature. Even if a heater is provided, the effect of suppressing variation can be achieved. In the present embodiment, three heaters are arranged concentrically. However, if two or more heaters are arranged in an arbitrary number, the temperature on the wafer 12 can be distributed concentrically. is there. However, from the viewpoint of controllability of the temperature distribution, it is desirable to arrange three or more heaters if possible. For example, as shown in FIG. 2, control is performed so that the temperature of the heater near the center of the wafer is low and the temperature of the heater near the periphery is high. More specifically, the control temperature of the center heater is set to 140 ° C, and a range of ± 20 mm from the center of the wafer is set.
Heat to 140 ° C and control temperature of the second heater to 150 ° C
Then, the range of ± 20 mm to ± 60 mm from the center of the wafer is heated to 150 ° C., the control temperature of the third heater is set to 160 ° C., and the range of ± 60 mm to ± 100 mm from the center of the wafer is heated to 160 ° C.

As a result, the temperature on the wafer is distributed smoothly as shown in FIG. In the case of this temperature distribution, FIG.
According to the results shown in the above, near the center of the wafer, the line width of the photoresist becomes narrower when viewed from the side of the attack by the developer, and the line width of the photoresist becomes thicker when viewed from the side of the temperature, and the two cancel each other out. Medium line width. Conversely, in the vicinity of the wafer periphery, the line width of the photoresist becomes wider when viewed from the side of the attack by the developer, and the line width of the photoresist becomes narrower when viewed from the temperature side, and the two lines cancel each other out, so that the line width is medium. become. Therefore, a substantially constant line width can be obtained over the entire wafer. FIG. 4 shows the in-plane line width variation of the annealing type photoresist of the wafer that was actually subjected to the PEB process using the photoresist baking furnace according to the present embodiment. The in-plane line width variation of this example is about 3%, and it can be seen that the in-plane line width variation of the photoresist was significantly improved from 28% to 3% by this embodiment.

FIG. 5 shows a second embodiment of the baking furnace of the present invention. FIG. 5A is a schematic longitudinal sectional view, and FIG. 5B is a plan view. In FIG. 5, the wafer is depicted as being transparent for clarity. The bake furnace 51 has a wafer 52 installed horizontally in the inside thereof. This wafer
Reference numeral 52 denotes a first heater 53 having a circular shape in the center in plan view, a doughnut-shaped second heater 54 installed so as to be substantially aligned with the periphery of the heater 53, and the heater 54.
The doughnut-shaped third heater 55 is disposed so as to be substantially aligned with the peripheral edge of the heater. Using this baking furnace 51, the wafer 52
Is performed, the wafer 52 and each heater 53,
Due to the structure in which the covers 59 of the 54 and 55 are in direct contact, the time required for the surface temperature of the wafer 52 to reach a steady state is reduced to about 1/3 compared to the first embodiment, and the total PEB time is also 60 seconds. To a degree.

Also in the case of the baking furnace of this embodiment, a plurality of heaters are arranged concentrically in a single baking furnace, and each heater is controlled at a different temperature, so that the temperature on the wafer is concentric. Can be distributed. In the present embodiment, the heater control temperature also changes abruptly at the boundary between the heaters, but between the wafer and the heater, because a thermally conductive cover 59 made of a stainless alloy or the like is arranged, The wafer surface temperature is
Distributed smoothly. Therefore, in the present embodiment as well as in the first embodiment, it is possible to cancel out and uniform the in-plane line width variation caused by the in-plane non-uniformity when the developer is filled, and to achieve it in a short time. it can.

[0019]

According to the present invention, a plurality of heaters are installed in proximity to a wafer in a photoresist baking furnace used in a baking process performed after the end of pattern exposure of a photoresist and before the start of development. A baking furnace for a photoresist, wherein the heater is heated at different temperatures to generate a temperature distribution in the wafer with a lower center portion and a higher peripheral portion to control the temperature of the wafer. During the wafer development process, the wafer is attacked by the developer for a relatively long time near its center, and the edge is short, so if the entire wafer is heated at a uniform temperature, the line width of the photoresist will vary. Occurs, and the line width becomes narrower nearer the center.

When baking (PEB) is performed between the end of exposure and the start of development while a temperature distribution is generated by using a plurality of heaters according to the present invention, the line width variation and the temperature distribution depending on the position are obtained. The line width variations due to the above are offset each other, and a uniform line width can be obtained. In addition, since the line width variation in wafer processing by a single heater occurs concentrically, in the baking furnace of the present invention, it is desirable to arrange a plurality of heaters concentrically, and the heater is donut-shaped. Preferably, there is. As a result, the temperature distribution becomes radial from the center of the wafer toward the periphery, and the most efficient temperature distribution can be obtained.

When the wafer is brought into contact with the heater, the heat of the heater is reliably transferred to the wafer, and an effective and desired temperature distribution can be achieved. Further, when the wafer is brought into contact with the heater through a cover coated with the heater, a rapid temperature change at the boundary between the heaters is alleviated, a gentle temperature distribution is obtained, and a further variation in line width is obtained. Suppression becomes possible.

[Brief description of the drawings]

FIG. 1 is a first view of a photoresist baking furnace according to the present invention.
FIG. 1A shows an embodiment, and FIG.
(b) is a plan view thereof.

FIG. 2 is a graph showing a relationship between a distance from a wafer center and control temperatures of a plurality of heaters according to the first embodiment of the present invention.

FIG. 3 is a graph showing a relationship between a distance from a wafer center and a wafer temperature in the first embodiment of the present invention.

FIG. 4 is a graph showing a relationship between a distance from a wafer center and a resist line width according to the first embodiment of the present invention.

FIG. 5 is a second view of the photoresist baking furnace according to the present invention.
FIG. 5A shows an embodiment, and FIG.
(b) is a plan view thereof.

FIG. 6 shows a conventional photoresist baking furnace;
(a) is a schematic longitudinal sectional view thereof, and FIG. 6 (b) is a plan view thereof.

FIG. 7 is a graph showing the relationship between the distance from the center of the wafer and the control temperature of the heater when the baking furnace of FIG. 6 is used.

8 is a graph showing a relationship between a distance from a wafer center and a wafer temperature when the baking furnace shown in FIG. 6 is used.

FIG. 9 is a graph showing a relationship between a distance from a wafer center and a resist line width when the baking furnace of FIG. 6 is used.

FIG. 10 is a graph showing a relationship between a PEB temperature and a resist line width.

[Explanation of symbols]

 11 Bake furnace 12 Wafer 13 First heater 14 Second heater 15 Third heater 16, 17, 18 Temperature controller 19 Cover 20 Heat-resistant pin

Claims (5)

[Claims] In a photoresist baking furnace used in a baking step performed after the end of pattern exposure of a photoresist and before the start of development, a plurality of heaters are installed in proximity to the wafer, and the heaters are turned on. A baking furnace for photoresist, wherein the wafer is heated at different temperatures to generate a temperature distribution in the wafer having a lower center portion and a higher peripheral portion to control the temperature of the wafer. 2. In a photoresist baking furnace used in a baking step performed after the end of pattern exposure of a photoresist and before the start of development, a plurality of heaters arranged concentrically are installed close to the wafer. Then, the heater is heated at different temperatures to generate a temperature distribution in which the central portion is low and the peripheral portion is high in the wafer, thereby controlling the temperature of the wafer and suppressing the variation in the in-plane line width of the photoresist. Characteristic baking furnace for photoresist. 3. The photoresist baking furnace according to claim 2, wherein the heater other than the central portion has a donut shape. 4. The photoresist baking furnace according to claim 2, wherein the wafer is brought into contact with a heater. 5. The photoresist baking furnace according to claim 2, wherein the wafer is brought into contact with the heater through a cover coated with the heater.