JP2008004591A - Method and system for treating substrate, program, and computer readable recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct the dimensions of a resist pattern formed on a wafer appropriately for each wafer. <P>SOLUTION: A resist film is formed on the wafer W and is exposed for development, thus forming the resist pattern on the wafer W. After that, the dimensions of the resist pattern are measured. Based on the measured result of the dimensions, the measured wafer W is heated to a prescribed temperature of not less than a glass transition point for expanding the resist pattern on the wafer W, and the dimensions of the resist pattern are adjusted to prescribed target dimensions. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a substrate processing method, a program, a computer-readable recording medium storing the program, and a substrate processing system.

  For example, in a photolithography process in the manufacture of semiconductor devices, for example, a resist coating process for applying a resist solution on a wafer to form a resist film, an exposure process for exposing the resist film to a predetermined pattern, and a development for developing the exposed resist film Processing is sequentially performed, and a predetermined resist pattern is formed on the wafer.

  The resist pattern described above determines the pattern shape of the underlying film to be etched and must be formed with strict dimensions. Therefore, for example, a resist pattern is first formed on a wafer for inspection, the line width of the resist pattern is measured, and various setting parameters in the resist pattern forming process are corrected based on the line width measurement result. It has been proposed to optimize the line width of the resist pattern (see Patent Document 1).

JP 2002-190446 A

  However, as described above, in the so-called feedback method in which the line width of the resist pattern of the wafer for inspection is measured and the processing setting of the subsequent product wafer is corrected based on the measurement result, the processing is performed with the wafer to be measured and the new setting. For example, it is not possible to sufficiently cope with a case where there is a variation in the line width inherent to each wafer or each wafer processing. As described above, in the above-described feed pack method, it is difficult to correct the line width of the resist pattern according to the characteristics of individual wafers.

  The present invention has been made in view of such a point, and an object thereof is to appropriately correct dimensions such as a line width of a resist pattern formed on a substrate such as a wafer for each substrate.

  The present invention for achieving the above object is a substrate processing method, comprising: a first step of forming a resist pattern on a substrate; a second step of measuring a dimension of the resist pattern; And a third step of adjusting the dimension of the resist pattern on the substrate to a predetermined target dimension by heating the measured substrate to a predetermined temperature not lower than the glass transition point based on the measurement result. It is characterized by that.

  According to the present invention, after the resist pattern is formed, the dimension of the resist pattern is measured, and based on the measurement result, the dimension of the resist pattern of the measurement substrate is adjusted to the target dimension. Accordingly, the dimension of the resist pattern can be corrected appropriately.

  In the second step, the dimensions of a plurality of regions in the substrate surface may be measured, and in the third step, the substrate may be heated at a predetermined temperature for each region.

  In the third step, a region having a small dimension in the substrate surface may be heated at a higher temperature than a region having a large dimension.

  The heating temperature in the third step may be set based on the correlation between the heating temperature and the dimensions that are obtained in advance.

  The first step includes a resist film forming process for forming a resist film on a substrate, an exposure process for exposing the resist film, and a developing process for developing the exposed resist film. May be performed after the development processing.

  The first step includes a resist film forming process for forming a resist film on the substrate, an exposure process for exposing the resist film, a developing process for developing the exposed resist film, and heating the substrate after the developing process. A heat treatment may be provided, and the second step may be performed after the heat treatment after the development processing.

  In the first step, the resist pattern may be formed to a size smaller than the final target size.

  According to another aspect of the present invention, there is provided a program for causing a computer to implement the substrate processing method.

  According to another aspect of the present invention, there is provided a computer-readable recording medium on which a program for causing a computer to implement the substrate processing method is recorded.

  Another aspect of the present invention is a substrate processing system, which is based on a resist pattern forming unit that forms a resist pattern on a substrate, a dimension measuring unit that measures the dimension of the resist pattern, and a measurement result of the dimension. And a dimension adjusting unit that heats the measured substrate to a predetermined temperature equal to or higher than the glass transition point to adjust the dimension of the resist pattern on the substrate to a predetermined target dimension. .

  The dimension measuring unit may measure dimensions of a plurality of regions in the substrate surface, and the dimension adjusting unit may heat the substrate at a predetermined temperature for each of the regions.

  The dimension adjusting unit may heat a small area in the substrate surface at a higher temperature than a large area.

  The heating temperature for the dimension adjustment may be set on the basis of the correlation between the heating temperature and the dimension obtained in advance.

  In the resist pattern forming unit, a resist film forming process for forming a resist film on the substrate and a developing process for developing the exposed resist film are performed. In the dimension adjusting unit, the dimension adjustment is performed after the developing process. It may be performed.

  In the resist pattern forming unit, a resist film forming process for forming a resist film on the substrate, a developing process for developing the exposed resist film, and a heating process for heating the substrate after the developing process are performed. Then, the dimension adjustment may be performed after the heat treatment after the development processing.

  In the resist pattern forming unit, the resist pattern may be formed to a size smaller than the final target size.

  According to the present invention, since the resist pattern of each substrate is formed in an appropriate dimension, the yield can be improved.

  Hereinafter, preferred embodiments of the present invention will be described. FIG. 1 is a plan view schematically showing the configuration of a coating and developing treatment system 1 as a substrate processing system according to the present embodiment, FIG. 2 is a front view of the coating and developing treatment system 1, and FIG. 2 is a rear view of the coating and developing treatment system 1. FIG.

  As shown in FIG. 1, the coating and developing treatment system 1 is a cassette that carries, for example, 25 wafers W from the outside to the coating and developing treatment system 1 in a cassette unit, and carries a wafer W into and out of the cassette C. A station 2, an inspection station 3 that performs a predetermined inspection on the wafer W, a processing station 4 in which a plurality of various processing apparatuses that perform predetermined processing in a single-wafer type in a photolithography process are arranged in multiple stages, An interface station 5 for transferring the wafer W to and from the exposure apparatus A provided adjacent to the processing station 4 is integrally connected.

  In the cassette station 2, a cassette mounting table 6 is provided, and the cassette mounting table 6 is capable of mounting a plurality of cassettes C in a row in the X direction (vertical direction in FIG. 1). The cassette station 2 is provided with a wafer transfer body 8 that can move along the X direction on the transfer path 7. The wafer transfer body 8 is also movable in the wafer arrangement direction (Z direction; vertical direction) of the wafers W accommodated in the cassette C, and selectively with respect to the wafers W arranged in the vertical direction in the cassette C. Accessible. The wafer carrier 8 can rotate around the vertical axis (θ direction), and can also access a delivery unit 10 on the inspection station 3 side described later.

  The inspection station 3 adjacent to the cassette station 2 is provided with a pattern dimension measuring device 20 as a dimension measuring unit. The pattern dimension measuring device 20 is disposed, for example, on the negative side in the X direction (downward in FIG. 1) of the inspection station 3. For example, on the cassette station 2 side of the inspection station 3, a delivery unit 10 for delivering the wafer W to and from the cassette station 2 is disposed. The delivery unit 10 is provided with a placement unit 10a on which, for example, a wafer W is placed. In the positive direction of the X direction of the pattern dimension measuring apparatus 20 (upward in FIG. 1), for example, a wafer transfer device 12 that can move along the X direction on the transfer path 11 is provided. For example, the wafer transfer device 12 is movable in the vertical direction and is also rotatable in the θ direction, and each processing of the pattern size measuring device 20, the transfer unit 10, and a third processing device group G3 described later on the processing station 4 side. Has access to the device.

  The processing station 4 adjacent to the inspection station 3 includes, for example, five processing device groups G1 to G5 in which a plurality of processing devices are arranged in multiple stages. A first processing device group G1 and a second processing device group G2 are arranged in this order from the inspection station 3 side on the X direction negative direction (downward direction in FIG. 1) side of the processing station 4. A third processing device group G3, a fourth processing device group G4, and a fifth processing device group G5 are sequentially arranged from the inspection station 3 side on the X direction positive direction (upward direction in FIG. 1) side of the processing station 4. Has been placed. A first transfer device 30 is provided between the third processing device group G3 and the fourth processing device group G4. The first transfer device 30 can selectively access each device in the first processing device group G1, the third processing device group G3, and the fourth processing device group G4 to transfer the wafer W. A second transport device 31 is provided between the fourth processing device group G4 and the fifth processing device group G5. The second transfer device 31 can selectively access each device in the second processing device group G2, the fourth processing device group G4, and the fifth processing device group G5 to transfer the wafer W.

  As shown in FIG. 2, in the first processing unit group G1, a liquid processing apparatus that supplies a predetermined liquid to the wafer W and performs processing, for example, a resist coating that applies a resist solution to the wafer W to form a resist film. Apparatuses 40, 41, and 42, and bottom coating apparatuses 43 and 44 that form an antireflection film for preventing reflection of light during the exposure process are stacked in five stages in order from the bottom. In the second processing unit group G2, liquid processing units, for example, development processing units 50 to 54 for supplying a developing solution to the wafer W and performing development processing are stacked in five stages in order from the bottom. Further, chemical chambers 60 and 61 for supplying various processing liquids to the liquid processing apparatuses in the processing apparatus groups G1 and G2 are provided at the lowermost stage of the first processing apparatus group G1 and the second processing apparatus group G2. Are provided.

  For example, as shown in FIG. 3, the third processing unit group G3 includes a temperature control unit 70, a transition unit 71 for delivering the wafer W, and a high-precision temperature control that adjusts the wafer temperature under high-precision temperature control. The apparatus 72-74 and the dimension adjustment apparatus 75-78 as a dimension adjustment part which heat-processes the wafer W at high temperature are piled up in nine steps in order from the bottom.

  In the fourth processing unit group G4, for example, a high-precision temperature control device 80, pre-baking devices 81 to 84 that heat-treat the resist-coated wafer W, and post-baking devices 85 to 85 that heat-process the developed wafer W. 89 are stacked in 10 steps from the bottom.

  In the fifth processing apparatus group G5, a plurality of heat treatment apparatuses that heat-treat the wafer W, for example, high-precision temperature control apparatuses 90 to 93 and post-exposure baking apparatuses 94 to 99 are stacked in 10 stages in order from the bottom.

  As shown in FIG. 1, a plurality of processing devices are arranged on the positive side in the X direction of the first transfer device 30. For example, as shown in FIG. 3, an adhesion device 100 for hydrophobizing the wafer W is shown. , 101, and heat treatment apparatuses 102 and 103 for heat-treating the wafer W are stacked in four stages in order from the bottom. As shown in FIG. 1, a peripheral exposure device 104 that selectively exposes only the edge portion of the wafer W, for example, is disposed on the positive side in the X direction of the second transfer device 31.

  For example, as shown in FIG. 1, the interface station 5 is provided with a wafer transfer body 111 that moves on a transfer path 110 that extends in the X direction, and a buffer cassette 112. The wafer carrier 111 is movable in the Z direction and rotatable in the θ direction, and accesses the exposure apparatus A adjacent to the interface station 5, the buffer cassette 112, and the fifth processing apparatus group G5. The wafer W can be transferred.

  In the present embodiment, for example, the resist coating apparatuses 40 to 42, the pre-baking apparatuses 81 to 84, the development processing apparatuses 50 to 54, the post exposure baking apparatuses 94 to 99, and the post baking apparatuses 85 to 89 of the processing station 4 are used. A resist pattern forming portion is configured.

  Next, the configuration of the pattern dimension measuring apparatus 20 will be described. For example, as shown in FIG. 4, the pattern dimension measuring apparatus 20 includes a mounting table 120 on which a wafer W is mounted horizontally and an optical surface shape measuring instrument 121. The mounting table 120 is, for example, an XY stage and can move in a two-dimensional direction in the horizontal direction. The optical surface shape measuring instrument 121 includes, for example, a light irradiation unit 122 that irradiates light on the wafer W from an oblique direction, a light detection unit 123 that detects light irradiated from the light irradiation unit 122 and reflected by the wafer W, A measurement unit 124 that calculates the size of the resist pattern on the wafer W based on the light reception information of the light detection unit 123 is provided. The pattern dimension measuring apparatus 20 according to the present embodiment measures a resist pattern dimension using, for example, a scatterometry method, and the wafer surface detected by the light detection unit 123 in the measurement unit 124. The size of the resist pattern can be measured by collating the light intensity distribution in the image with the virtual light intensity distribution stored in advance and obtaining the dimension of the resist pattern corresponding to the collated virtual light intensity distribution. .

In addition, the pattern forming apparatus 20 moves the wafer W relatively horizontally with respect to the light irradiation unit 122 and the light detection unit 123, so that a plurality of regions in the wafer surface, for example, each wafer region W as shown in FIG. it can be measured pattern size of ₁ to _W-5. The wafer regions W _{1 to} W ₅ correspond to hot plate regions R _{1 to} R ₅ of dimension adjusting devices 75 to 78 described later.

  Next, the structure of the dimension adjusting devices 75 to 78 described above will be described. For example, as shown in FIG. 6, the dimension adjusting device 75 includes a casing 130 a in which the processing chamber K is integrated with the lid 130 that is located on the upper side and is movable up and down, and the lid 130 that is located on the lower side. It has a hot plate housing part 131 to be formed.

  The lid 130 has a substantially cylindrical shape with an open bottom surface. An exhaust part 130 a is provided at the center of the upper surface of the lid 130. The atmosphere in the processing chamber K is uniformly exhausted from the exhaust part 130a.

As shown in FIG. 7, the hot plate 140 is divided into a plurality of, for example, five hot plate regions R ₁ , R ₂ , R ₃ , R ₄ , and R ₅ . The hot plate 140 is, for example, positioned in the center when viewed from the plane, and is divided into a circular hot plate region R ₁ and hot plate regions R _{2 to} R ₅ whose periphery is divided into four arcs.

Each of the hot plate regions R _{1 to} R ₅ of the hot plate 140 has a built-in heater 141 that generates heat by power feeding and can be heated for each of the hot plate regions R _{1 to} R ₅ . The amount of heat generated by the heater 141 in each of the hot plate regions R _{1 to} R ₅ is adjusted by the temperature controller 142. The temperature control device 142 can control the temperature of each of the hot plate regions R _{1 to} R ₅ to a predetermined heating temperature by adjusting the amount of heat generated by the heater 141. The setting of the heating temperature in the temperature control device 142 is performed by, for example, the control unit 170 described later.

  As shown in FIG. 6, elevating pins 150 for supporting the wafer W from below and elevating it are provided below the hot platen 140. The elevating pin 150 can be moved up and down by an elevating drive mechanism 151. A through-hole 152 that penetrates the hot plate 140 in the thickness direction is formed near the center of the hot plate 140, and the lift pins 150 rise from below the hot plate 140 and pass through the through-hole 152, It can protrude above the plate 140.

  The hot plate accommodating portion 131 includes, for example, an annular holding member 160 that holds the hot plate 140 and holds the outer peripheral portion of the hot plate 140, and a substantially cylindrical support ring 161 that surrounds the outer periphery of the holding member 160. .

  In addition, about the structure of the dimension adjustment apparatuses 76-78, since it is the same as that of the said dimension adjustment apparatus 75, description is abbreviate | omitted.

  Next, the structure of the control part 170 which sets the heating temperature of the said dimension adjustment apparatus 75-78 is demonstrated. For example, the control part 170 is comprised by the general purpose computer provided with CPU, memory, etc., for example, is connected to the temperature control apparatus 142 as shown, for example in FIG.6 and FIG.7.

  For example, as shown in FIG. 8, the control unit 170 inputs the dimension measurement result from the pattern dimension measurement device 20, for example, and calculates the heating temperature of the dimension adjustment devices 75 to 78 from the dimension measurement result. A data storage unit 201 for storing various necessary information, a program storage unit 202 for storing a program P for calculating the heating temperature of the dimension adjusting devices 75 to 78, and an arithmetic unit for calculating the heating temperature by executing the program P 203 and an output unit 204 that outputs the calculated heating temperature to the dimension adjustment devices 75 to 78.

For example, the data storage unit 201 stores data indicating the correlation M between the heating temperature T and the dimension D in the dimension adjusting devices 75 to 78 as shown in FIG. The program P stored in the program storage unit 202 uses, for example, the correlation measurement M on the basis of the dimension measurement result in the wafer surface from the pattern dimension measurement apparatus 20, and each hot plate region R ₁ in the dimension adjustment apparatuses 75 to 78. the heating temperature of to R ₅ can be calculated. This program P calculates a heating temperature equal to or higher than the glass transition point at which the resist pattern in the wafer surface is expanded by heating the hot plate 140 to a predetermined target dimension. Note that the program P for realizing the functions of the control unit 170 may be installed in the control unit 170 using a computer-readable recording medium.

  Next, a processing process for the wafer W in the coating and developing processing system 1 configured as described above will be described. FIG. 10 is a flow showing an example of the processing process of the wafer W.

  First, unprocessed wafers W are taken out one by one from the cassette C on the cassette mounting table 6 by the wafer transfer body 8 shown in FIG. 1 and sequentially transferred to the delivery unit 10 of the inspection station 3. The wafer W transferred to the delivery unit 10 is transferred to the processing station 4 by the wafer transfer device 12, and a resist pattern forming process is performed (step S1 in FIG. 10). For example, the wafer W is first transported to the temperature control device 70 belonging to the third processing device group G3 of the processing station 4, and after the temperature is adjusted to a predetermined temperature, it is transported to the bottom coating device 43 by the first transport device 30. Then, an antireflection film is formed. Thereafter, the wafer W is sequentially transferred to the heat processing apparatus 102 and the high-precision temperature control apparatus 80 by the first transfer apparatus 30 and subjected to predetermined processing in each processing apparatus. Thereafter, the wafer W is transferred to the resist coating apparatus 40 by the first transfer apparatus 30.

  In the resist coating apparatus 40, for example, a predetermined amount of resist solution is supplied to the surface of the rotated wafer W, and the resist solution diffuses over the entire surface of the wafer W to form a resist film on the wafer W ( Step S2 in FIG.

  The wafer W on which the resist film is formed is transferred to, for example, a pre-baking device 81 by the first transfer device 30 and subjected to heat treatment, and then the peripheral transfer device 104 and the high-precision temperature control are performed by the second transfer device 31. It is sequentially transported to the apparatus 93, and a predetermined process is performed in each apparatus. Thereafter, the wafer is transferred to the exposure apparatus A by the wafer transfer body 111 of the interface station 5, and a predetermined pattern is exposed on the resist film on the wafer W (step S3 in FIG. 10). The wafer W that has been subjected to the exposure process is transferred by the wafer transfer body 111 to, for example, the post-exposure baking apparatus 94 in the processing station 4, and the wafer W is heated.

  The wafer W that has been subjected to the heat treatment is transported to the high-precision temperature control device 81 by the second transport device 31 to adjust the temperature, and then transported to the development processing device 30 to develop the resist film on the wafer W. (Step S4 in FIG. 10). Thereafter, the wafer W is, for example, transferred to the post-baking device 85 by the second transfer device 31 and subjected to post-baking (step S5 in FIG. 10), and then to the high-precision temperature controller 72 by the first transfer device 30. Transported and temperature adjusted. Thus, the resist pattern forming step S1 is completed. In this resist pattern formation step S1, a resist pattern is formed with a line width smaller than the final target line width.

  The wafer W on which the resist pattern forming step S1 has been completed is transferred to the transition device 71 by the first transfer device 30 and transferred to the pattern dimension measuring device 20 of the inspection station 3 by the wafer transfer device 12.

In the pattern dimension measuring apparatus 20, the wafer W is mounted on the mounting table 120 as shown in FIG. Next, light is irradiated onto a predetermined portion of the wafer W from the light irradiation unit 122, the reflected light is detected by the light detection unit 123, and the dimension of the resist pattern on the wafer W, for example, the line width is measured by the measurement unit 124. (Step S6 in FIG. 10). In the pattern dimension measuring apparatus 20, the wafer W with respect to the light irradiation unit 122 and the light detection unit 123 is horizontally moved, the line width of the resist pattern for each wafer regions W ₁ to _W-5 is measured. The measurement results of the line widths of these wafer regions W _{1 to} W ₅ are output to the control unit 170.

For example, in the control unit 170, the program P causes the hot plate regions R _{1 to} R _{5 in} the dimension adjustment devices 75 to 78 to be based on the line width measurement result from the pattern dimension measurement device 20 and the correlation M of the data storage unit 201. The heating temperature is calculated. This heating temperature is a temperature of, for example, about 140 ° C. to 160 ° C. above the glass transition point Tg, and the line widths of the resist patterns in all the wafer regions W _{1 to} W ₅ are constant by the heat treatment of the dimension adjusting devices 75 to 78. The temperature is calculated so as to be the target line width.

For example, as shown in FIG. 11, the final target line width of the resist pattern is 90 μm, the measurement line width of the wafer area W ₁ at the center of the wafer W is 80 μm, and the wafer area W _2- When the measurement line width of W ₅ is 85 μm, the heating temperature of the hot plate regions R _{2 to} R ₅ corresponding to the wafer regions W _{2 to} W ₅ exceeds the glass transition point Tg as shown in FIG. T1 ° C. where the width is increased by +5 μm is calculated. In addition, as the heating temperature of the hot plate region R ₁ corresponding to the wafer region W ₁ , T2 ° C. that is higher than the temperature T1 ° C. of other regions and whose line width is +10 μm is calculated. These calculated heating temperatures are set as the heating temperatures of the hot plate regions R _{1 to} R ₅ in the temperature control device 142 of the dimension adjusting devices 75 to 78 (step S7 in FIG. 10).

Thereafter, the wafer W unloaded from the pattern dimension measuring apparatus 20 is transferred by the wafer transfer body 8 to, for example, the dimension adjusting apparatus 75 of the processing station 4. The wafer W is transferred to the raising / lowering pins 150 that have been raised and waiting in advance. After the lid 130 is closed, the raising / lowering pins 150 are lowered and the wafer W is placed on the hot platen 140. In this way, the wafer W is heated by the hot plate 140 that has been heated to a predetermined heating temperature in advance. At this time, the wafer W is the wafer area _{W 1} and the wafer area _W 2 to _W-5 with different temperature settings and the thermal plate regions _{R 1} and the thermal plate regions _R 2 to R ₅ described above are heated at different temperatures. Wafer area W ₁ and the wafer area W ₂ to _W-5, since both are heated to a temperature higher than the glass transition point Tg, the thermal shrinkage behavior, as shown in FIG. 12, the line width D resist pattern B is softened Is expanded. Further, since the temperature of the wafer area _{W 1} is heated at a temperature higher than the wafer area _W 2 to _W-5, the resist pattern B of the wafer area _{W 1} as shown in FIG. 11 as compared to the wafer area _W 2 to _W-5 spread larger Te, for example, the line width D of the resist pattern on the wafer regions _{W 1} is adjusted to 80 [mu] m → 90 [mu] m, line width D of the resist pattern of the wafer area _W 2 to _W-5 is adjusted to 85 .mu.m → 90 [mu] m. As described above, the line width of the resist pattern in each of the wafer regions W _{1 to} W ₅ is widened according to the heating temperature, and finally the line width of the resist pattern in the wafer surface is uniformly adjusted (step of FIG. 10). S8).

  The wafer W whose line width has been adjusted by the dimension adjusting device 75 is then transferred to the transfer unit 10 of the inspection station 3 by the wafer transfer device 12 and returned from the transfer unit 10 to the cassette C by the wafer transfer body 8. Thus, a series of wafer processing in the coating and developing processing system 1 is completed.

  According to the above embodiment, after forming the resist pattern on the wafer W, the line width of the resist pattern is measured, and the wafer W is higher than the glass transition point Tg based on the result of the line width measurement. Since heating is performed at a predetermined temperature, the line width of the resist pattern on the wafer W can be adjusted to a desired target line width. As a result, a resist pattern having a desired line width can be formed for each wafer W that is continuously processed. Further, after the resist pattern is formed by the photolithography process, the resist pattern is heated again to the glass transition point Tg or more to be softened, so that the line edge waviness (line edge roughness) of the resist pattern can be reduced.

Also, by measuring the line width of each wafer area W ₁ to _W-5 of the wafer W, since the heating temperature was set for each wafer area W ₁ to _W-5, it is possible to align uniformly the line width within the wafer.

  Since the heating temperature in the line width adjustment step S8 is calculated using the correlation M between the heating temperature and the dimension obtained in advance, the final line width dimension can be adjusted more accurately.

  In the resist pattern forming step S1, since the resist pattern is formed to have a line width smaller than the final target line width, the adjustment to the final target line width in the line width adjusting step S8 can be easily performed. .

  In the above embodiment, the line width measurement step S6 is performed immediately after the post-baking after the development processing, but may be performed immediately after the development processing as shown in FIG. Moreover, when performing post baking, you may perform post baking with line | wire width adjustment in the dimension adjustment apparatuses 75-78. In such a case, post-baking may be performed at a temperature lower than the glass transition point Tg, and then the line width may be adjusted at a temperature equal to or higher than the glass transition point Tg.

  In the above embodiment, the entire surface of the wafer W is heated by the dimension adjusting device 75 to adjust the line width. However, only the wafer area where the line width of the resist pattern needs to be adjusted is selectively heated. Also good.

  Further, in the above embodiment, the line width is adjusted as the dimension of the resist pattern. However, the dimension of a part where holes are formed may be adjusted.

  The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples. It will be apparent to those skilled in the art that various changes or modifications can be made within the scope of the ideas described in the claims, and these are naturally within the technical scope of the present invention. It is understood that it belongs. For example, in the above embodiment, the pattern dimension measuring apparatus 20 measures the dimensions of the five areas of the wafer W, and the dimension adjusting apparatus 75 sets the heating temperatures of the five areas of the hot platen 140. The number and shape can be arbitrarily selected. In the above-described embodiment, the pattern dimension measuring apparatus 20 is provided in the inspection station 3, but may be provided in the processing station 4.

  Although the dimension adjusting devices 75 to 78 are provided in the processing station 4, they may be provided in the same inspection station 3 as the pattern dimension measuring device 20. For example, as shown in FIG. 14, the dimension adjusting devices 75 to 78 may be provided at a position accessible by the wafer transfer device 12 in the inspection station 3 and at a position facing the pattern dimension measuring device 20 in the X direction. . Further, the dimension adjusting devices 75 to 78 may be arranged in multiple stages with the delivery unit 10 of the inspection station 3. In these cases, since the measurement and adjustment of the pattern dimensions are both performed at the inspection station 3, the wafer processing flow having the pattern dimension measurement process and the pattern dimension adjustment process can be smoothly constructed, and the throughput can be improved.

  Furthermore, the present invention can also be applied to processing of other substrates such as an FPD (Flat Panel Display) other than a wafer and a mask reticle for a photomask.

  The present invention is useful when a resist pattern having a desired dimension is formed on each substrate.

It is a top view which shows the outline of a structure of a coating-development processing system. FIG. 2 is a front view of the coating and developing treatment system of FIG. 1. FIG. 2 is a rear view of the coating and developing treatment system of FIG. 1. It is explanatory drawing of the longitudinal cross-section which shows the outline of a structure of a pattern dimension measuring apparatus. It is explanatory drawing which shows the divided | segmented wafer area | region. It is explanatory drawing of the longitudinal cross-section which shows the outline of a structure of a dimension adjustment apparatus. It is a top view which shows the structure of the hot platen of a dimension adjustment apparatus. It is a block diagram which shows the structure of a control part. It is a graph which shows the correlation of heating temperature and a dimension. It is a flowchart which shows the processing process of a wafer. It is explanatory drawing which shows a mode that line | wire width is adjusted with a dimension adjustment apparatus. It is explanatory drawing which shows a mode that the line | wire width of a resist pattern spreads by the heating by a dimension adjustment apparatus. It is a flowchart which shows the processing process of the wafer in the case of measuring a line width immediately after development processing. It is a top view which shows the coating and developing treatment system when a dimension adjustment apparatus is provided in the inspection station.

Explanation of symbols

1 coating and developing treatment system 20 pattern dimension measuring apparatus 75 size adjustment device 140 hot plate R ₁ to R ₅ of the thermal plate regions 170 controller W wafer W ₁ to _W-5 wafer area

Claims (16)

A substrate processing method comprising:
A first step of forming a resist pattern on the substrate;
A second step of measuring the dimensions of the resist pattern;
A third step of adjusting the dimension of the resist pattern on the substrate to a predetermined target dimension by heating the measured substrate to a predetermined temperature equal to or higher than the glass transition point based on the measurement result of the dimension; And a substrate processing method. In the second step, the dimensions of a plurality of regions in the substrate surface are measured,
The substrate processing method according to claim 1, wherein in the third step, the substrate is heated at a predetermined temperature for each of the regions. The substrate processing method according to claim 2, wherein in the third step, a region having a small dimension in the substrate surface is heated at a temperature higher than that of the region having a large dimension. The substrate processing according to any one of claims 1 to 3, wherein the heating temperature in the third step is set based on a correlation between the heating temperature and the dimension obtained in advance. Method. The first step includes a resist film forming process for forming a resist film on the substrate, an exposure process for exposing the resist film, and a developing process for developing the exposed resist film,
The substrate processing method according to claim 1, wherein the second step is performed after the development processing. The first step includes a resist film forming process for forming a resist film on the substrate, an exposure process for exposing the resist film, a developing process for developing the exposed resist film, and heating the substrate after the developing process. Have heat treatment,
The substrate processing method according to claim 1, wherein the second step is performed after the heat treatment after the development processing. The substrate processing method according to claim 1, wherein in the first step, the resist pattern is formed to a size smaller than a final target size. A program for causing a computer to implement the substrate processing method according to claim 1. A computer-readable recording medium recording a program for causing a computer to implement the substrate processing method according to claim 1. A substrate processing system,
A resist pattern forming portion for forming a resist pattern on the substrate;
A dimension measuring unit for measuring the dimension of the resist pattern;
Based on the measurement result of the dimension, the measured substrate is heated to a predetermined temperature equal to or higher than the glass transition point, and a dimension adjustment unit that adjusts the dimension of the resist pattern on the substrate to a predetermined target dimension; A substrate processing system comprising: The dimension measuring unit measures dimensions of a plurality of regions in the substrate surface,
The substrate processing system according to claim 10, wherein the dimension adjusting unit heats the substrate at a predetermined temperature for each region. The substrate processing system according to claim 11, wherein the dimension adjusting unit heats a region having a small dimension in the substrate surface at a temperature higher than that of the region having a large dimension. The substrate processing system according to claim 10, wherein a heating temperature for the dimension adjustment is set based on a correlation between the heating temperature and the dimension that are obtained in advance. . In the resist pattern forming portion, a resist film forming process for forming a resist film on the substrate and a developing process for developing the exposed resist film are performed,
The substrate processing system according to claim 10, wherein the dimension adjustment unit performs the dimension adjustment after the development processing. In the resist pattern forming portion, a resist film forming process for forming a resist film on the substrate, a developing process for developing the exposed resist film, and a heating process for heating the substrate after the developing process are performed,
14. The substrate processing system according to claim 10, wherein the dimension adjustment unit performs the dimension adjustment after the heat treatment after the development processing. 16. The substrate processing system according to claim 10, wherein the resist pattern forming unit forms the resist pattern in a size smaller than a final target size.

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