CN114488723A - Phase shift mask photoresist baking method for semiconductor chip and storage medium - Google Patents
Phase shift mask photoresist baking method for semiconductor chip and storage medium Download PDFInfo
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- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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Abstract
The invention discloses a semiconductor chip mask photoresist baking device, a phase shift mask photoresist baking method for a semiconductor chip and a storage medium, wherein the semiconductor chip mask photoresist baking device comprises a temperature analysis module and a heating module, the heating module comprises a heating plate and is used for baking a mask placed on the surface of the heating plate, and the heating plate comprises a temperature control array; the temperature analysis module is used for determining the baking temperature of each sub-area in the PSM substrate according to a mask pattern formed on the PSM substrate of the mask; the temperature control array comprises a plurality of temperature adjusting units, and the temperature adjusting units are connected with the temperature analysis module and used for adjusting the temperature of each sub-area to the corresponding baking temperature. The accurate baking temperature is provided for different areas of the PSM substrate by converting the pattern distribution density of each grid of the mask pattern into the baking temperature of each sub-area in proportion, so that the image size uniformity of the mask plate is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor chip mask photoresist baking device, a phase shift mask photoresist baking method for a semiconductor chip and a storage medium.
Background
A mask, also called a photomask or reticle, is a link and bridge connecting a design end and a process end. With the progress of design technology and manufacturing process, phase shift masks are currently available, which utilize the phase interference principle to form a pattern on a substrate and also form a phase shift layer region and a non-phase shift layer region, when the phase shift mask is used for an exposure process, the light passing through the phase shift layer region can generate 180-degree phase change, so as to achieve the purpose of better controlling the pattern dimension (CD), in the process of manufacturing the phase shift mask, the method comprises the steps of performing an exposure operation on an electronic photoresist on the mask by using an electronic beam, baking the exposed mask to complete the chemical reaction of the photoresist, and performing a development operation on the baked mask by using a developing solution, wherein in the general technology, the uniform temperature is generally adopted to bake all regions of the mask, but when the baking is performed based on the uniform temperature, the area with high distribution density can not obtain enough high temperature to meet the area, so that the chemical reaction rate of the photoresist and the developing solution in different areas is inconsistent, the chemical change of the mask is not uniform, and the uniformity of the image size (CD) is affected. In addition, when the fine pattern is developed, the developing solution slowly permeates into the pattern relative to the large pattern, so that the chemical reaction rates of the fine pattern, the large pattern and the developing solution are different, the uniformity of the pattern size (CD) is further influenced, the deviation degree of the process procedure between the pattern baked on the mask plate before development and the actual pattern formed after development is further increased, and the processing effect of the mask plate is influenced.
The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.
Disclosure of Invention
The invention mainly aims to provide semiconductor chip mask photoresist baking equipment, a phase shift mask photoresist baking method for a semiconductor chip and a storage medium, and aims to solve the technical problem of nonuniformity of mask image sizes.
In order to achieve the purpose, the invention provides a semiconductor chip mask photoresist baking device which comprises a temperature analysis module and a heating module, wherein the heating module comprises a heating plate used for baking a mask placed on the surface of the heating plate, the heating plate comprises a temperature control array, and the temperature control array is connected with the temperature analysis module;
the temperature analysis module is used for determining the baking temperature of each sub-area in a PSM substrate according to a mask pattern formed on the PSM substrate of the mask, wherein the baking temperature of each sub-area corresponds to the pattern distribution density of each grid of the mask pattern;
the temperature control array comprises a plurality of temperature adjusting units, the temperature adjusting units are connected with the temperature analysis module and used for adjusting the temperature of each sub-area to the corresponding baking temperature so as to perform baking operation on the mask, and each temperature adjusting unit corresponds to each sub-area of the PSM substrate.
Optionally, the temperature analysis module includes a light transmittance calculation unit, the light transmittance calculation unit divides the mask pattern into grids according to the mask pattern, and determines the light transmittance of each sub-region according to the image distribution density of each grid;
after the light transmittance of each sub-area is determined, the baking temperature of each sub-area is determined according to the light transmittance of each sub-area, wherein the higher the light transmittance is, the lower the baking temperature is, the lower the light transmittance is, and the higher the baking temperature is.
Optionally, the temperature control array further includes temperature sensors, the temperature sensors are installed in the temperature adjusting units and used for measuring actual temperatures of the sub-regions, and the temperature sensors are connected to the temperature analysis module and used for sending the detected actual temperatures of the corresponding sub-regions to the temperature analysis module;
the temperature analysis module determines working parameters of each temperature adjusting unit according to the actual temperature and the temperature difference value of the baking temperature, and sends the working parameters to each temperature adjusting unit so that the temperature adjusting unit adjusts the temperature of each sub-area to the corresponding baking temperature according to the corresponding working parameters, the working parameters comprise working modes and temperature compensation values, and the working modes comprise a refrigeration mode and a heating mode.
Optionally, the temperature adjusting unit comprises a semiconductor refrigeration module and a direct current power controller, and the semiconductor refrigeration module is connected with the direct current power controller;
and the direct current power controller determines the current direction and the current value according to the working parameters, and inputs the corresponding current value to the semiconductor refrigeration module in the current direction so that the semiconductor refrigeration module provides the corresponding temperature difference value for the corresponding sub-region.
Optionally, the semiconductor chip mask photoresist baking equipment further comprises a constant bottom temperature control module, wherein the constant bottom temperature control module is connected with the temperature analysis module and is used for providing a preset heating temperature for the mask placed on the heating plate;
invariable bottom temperature control module includes hot air circulating system, hot air circulating system includes hot air circulating pipeline and vortex circulation heat dissipation wind channel, the hot air circulating pipeline with the entrance point connection in vortex circulation heat dissipation wind channel, the inside canalis spinalis that is the trapezoidal form that sets up in vortex circulation heat dissipation wind channel, the canalis spinalis includes vortex heat dissipation perk face and lower vortex heat dissipation perk face, go up vortex heat dissipation perk face and the surface area of lower vortex heat dissipation perk face and follow the exit end in entrance point to vortex circulation heat dissipation wind channel is linear proportion and increases progressively.
Optionally, the constant bottom temperature control module further comprises a liquid flow equalizing and heat conducting device, and the liquid flow equalizing and heat conducting device is arranged below the heating plate and connected with the hot air circulating system.
In addition, in order to achieve the above object, the present invention further provides a method for baking a phase shift mask photoresist for a semiconductor chip, which is applied to the above equipment for baking a mask photoresist for a semiconductor chip, wherein the method for baking a phase shift mask photoresist for a semiconductor chip comprises the steps of:
obtaining a mask pattern on the exposed photoresist on a PSM substrate of a mask, and rasterizing the mask pattern to obtain a plurality of grids corresponding to the mask pattern;
determining the baking temperature corresponding to each sub-area in the PSM substrate according to the pattern distribution density of each grid, wherein each sub-area corresponds to each grid;
and providing corresponding baking temperatures for the sub-regions according to the baking temperatures so as to perform baking operation on the exposed mask.
Optionally, the step of determining the baking temperature corresponding to each sub-region in the PSM substrate according to the pattern distribution density of each grid includes:
determining the light transmittance corresponding to each grid according to the pattern distribution density of each grid;
and determining the baking temperature corresponding to each sub-area according to the light transmittance, wherein the higher the light transmittance is, the lower the baking temperature is, and the lower the light transmittance is, the higher the baking temperature is.
Optionally, the step of providing a corresponding baking temperature for each sub-region according to the baking temperature to perform a baking operation on the exposed reticle includes:
acquiring actual temperatures corresponding to all the sub-areas, and acquiring the baking temperature and the temperature difference value of the actual temperatures;
providing the temperature difference value to the corresponding sub-area so that the temperature of each sub-area reaches the baking temperature.
In addition, in order to achieve the above object, the present invention further provides a storage medium, where the storage medium stores a photoresist baking program for a phase shift mask for a semiconductor chip, and the photoresist baking program for a phase shift mask for a semiconductor chip is executed by a processor to implement the steps of the photoresist baking method for a phase shift mask for a semiconductor chip as described above.
According to the semiconductor chip mask photoresist baking equipment, the phase shift mask photoresist baking method for the semiconductor chip and the storage medium, the semiconductor chip mask photoresist baking equipment is provided with the temperature analysis module and the heating module, the heating module comprises the heating plate, the heating plate comprises the temperature control array, the temperature control array comprises a plurality of temperature adjusting units, each temperature adjusting unit corresponds to each sub-area of a PSM substrate of a mask to be baked, in actual baking, the temperature analysis module converts the image distribution density of each grid in a mask image formed on the mask to be baked into the baking temperature corresponding to each grid in an equal proportion mode, the baking temperature of each sub-area of the PSM substrate is determined according to the baking temperature corresponding to each grid, and the corresponding temperature adjusting units are controlled to provide the corresponding baking temperature for each sub-area, the sub-regions corresponding to different pattern distribution densities can acquire accurate baking temperature, so that the photoresist of each sub-region can absorb enough heat to generate weak acid hinge-lock reaction, the rate of the weak acid hinge-lock reaction of each sub-region is ensured to be the same, and the rate of the chemical reaction of each sub-region and the developer after baking is ensured to be the same, thereby improving the uniformity of the image size of the mask.
Drawings
FIG. 1 is a schematic structural diagram of a semiconductor chip reticle photoresist baking apparatus in a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a semiconductor chip reticle photoresist baking apparatus according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a temperature control array according to an embodiment of the present invention;
fig. 4 is a schematic structural view of a disturbed flow circulation heat dissipation air duct according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a mask pattern according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a process for calculating a baking temperature according to an embodiment of the present invention;
FIG. 7 is a schematic flowchart of a first embodiment of a method for baking a phase-shift mask photoresist for a semiconductor chip according to an embodiment of the present invention;
FIG. 8 is a schematic view of a complete flow chart of a method for baking a phase shift mask photoresist for a semiconductor chip according to an embodiment of the present invention;
FIG. 9 is a schematic view of a detailed flow chart of a step 20 of a phase-shift mask photoresist baking method for a semiconductor chip according to a second embodiment of the present invention;
FIG. 10 is a flowchart illustrating a step S30 of a third embodiment of a method for baking a phase-shift mask photoresist for a semiconductor chip according to an embodiment of the present invention;
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Since the prior art includes performing an exposure operation on an electron photoresist on a phase shift mask by using an electron beam in the process of manufacturing the phase shift mask, baking the exposed mask to complete the chemical reaction of the photoresist, and performing a developing operation on the baked mask by using a developing solution, wherein in the general technology, a uniform temperature is generally adopted to bake all areas of the mask, however, when baking is performed at a uniform temperature based on the distribution density of the pattern, a region having a high distribution density cannot obtain a sufficiently high temperature for the region, therefore, the chemical reaction rates of the photoresist in different areas are different, and the chemical reaction rates of different areas of the mask are different due to the fact that the mask is developed directly by using the developing solution, so that the chemical change of the mask is not uniform, and the uniformity of the image size (CD) is influenced. In addition, when the fine pattern is developed, the developing solution slowly permeates into the pattern relative to the large pattern, so that the chemical reaction rates of the fine pattern, the large pattern and the developing solution are different, the uniformity of the pattern size (CD) is further influenced, the deviation degree of the process procedure between the pattern baked on the mask plate before development and the actual pattern formed after development is further increased, and the processing effect of the mask plate is influenced.
The invention provides a semiconductor chip mask photoresist baking device, a phase shift mask photoresist baking method for a semiconductor chip and a storage medium, wherein the semiconductor chip mask photoresist baking device comprises a temperature analysis module and a heating module, the heating module comprises a heating plate and is used for baking a mask placed on the surface of the heating plate, the heating plate comprises a temperature control array, and the temperature control array is connected with the temperature analysis module; the temperature analysis module is used for determining the baking temperature of each sub-area in a PSM substrate according to a mask pattern formed on the PSM substrate of the mask, wherein the baking temperature of each sub-area corresponds to the pattern distribution density of each grid of the mask pattern; the temperature control array comprises a plurality of temperature adjusting units, the temperature adjusting units are connected with the temperature analysis module and used for adjusting the temperature of each sub-area to the corresponding baking temperature so as to perform baking operation on the mask, and each temperature adjusting unit corresponds to each sub-area of the PSM substrate.
The baking method of the photoresist of the phase shift mask for the semiconductor chip is applied to baking equipment of the photoresist of the mask of the semiconductor chip, and the baking method of the photoresist of the phase shift mask for the semiconductor chip comprises the following steps:
obtaining a mask pattern on the exposed photoresist on a PSM substrate of a mask, and rasterizing the mask pattern to obtain a plurality of grids corresponding to the mask pattern;
determining the baking temperature corresponding to each sub-area in the PSM substrate according to the pattern distribution density of each grid, wherein each sub-area corresponds to each grid;
and providing corresponding baking temperatures for the sub-regions according to the baking temperatures so as to perform baking operation on the exposed mask.
According to the scheme, the photoresist baking equipment for the mask plate of the semiconductor chip can provide corresponding baking temperatures for different areas of the mask plate according to the pattern distribution density of each grid in the mask image, so that the chemical reaction rate of the photoresist in each area on the mask plate is kept consistent, the image size uniformity of the mask plate is improved, and the mask plate processing effect is improved.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a semiconductor chip reticle photoresist baking apparatus in a hardware operating environment according to an embodiment of the present invention.
As shown in fig. 1, the semiconductor chip reticle photoresist baking apparatus may include: a processor 1001, e.g. a CPU, a network interface 1004, a user interface 1003, a memory 1005, a communication bus 1002. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface). The memory 1005 may be a high-speed RAM memory or a non-volatile memory (e.g., a magnetic disk memory). The memory 1005 may alternatively be a storage device separate from the processor 1001.
Those skilled in the art will appreciate that the semiconductor chip reticle photoresist baking apparatus configuration shown in fig. 1 does not constitute a limitation of the semiconductor chip reticle photoresist baking apparatus and may include more or fewer components than shown, or some components in combination, or a different arrangement of components.
As shown in fig. 1, a memory 1005, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and a phase shift mask photoresist baking program for semiconductor chips.
In the terminal shown in fig. 1, the network interface 1004 is mainly used for connecting to a backend server and performing data communication with the backend server; the user interface 1003 is mainly used for connecting a client (user side) and performing data communication with the client; and the processor 1001 may be configured to call a phase shift mask baking program for semiconductor chips stored in the memory 1005, and perform the following operations:
obtaining a mask pattern on the exposed photoresist on a PSM substrate of a mask, and rasterizing the mask pattern to obtain a plurality of grids corresponding to the mask pattern;
determining the baking temperature corresponding to each sub-area in the PSM substrate according to the pattern distribution density of each grid, wherein each sub-area corresponds to each grid;
and providing corresponding baking temperatures for the sub-regions according to the baking temperatures so as to perform baking operation on the exposed mask.
Further, the processor 1001 may call a phase shift mask photoresist baking program for semiconductor chips stored in the memory 1005, and also perform the following operations:
determining the light transmittance corresponding to each grid according to the pattern distribution density of each grid;
and determining the baking temperature corresponding to each sub-area according to the light transmittance, wherein the higher the light transmittance is, the lower the baking temperature is, and the lower the light transmittance is, the higher the baking temperature is.
Further, the processor 1001 may invoke a phase shift reticle photoresist bake program stored in the memory 1005, and also perform the following operations:
acquiring actual temperatures corresponding to all the sub-areas, and acquiring the baking temperature and the temperature difference value of the actual temperatures;
providing the temperature difference to the corresponding sub-area so that the temperature of each sub-area reaches the baking temperature.
Referring to fig. 2 to 4, fig. 2 to 4 are schematic structural views of a semiconductor chip reticle photoresist baking apparatus according to an embodiment of the present invention.
The semiconductor chip mask photoresist baking equipment comprises a temperature analysis module (not shown in the figure) and a heating module 20, wherein in the embodiment of the application, the heating module 20 comprises a heating plate for baking the mask 10 placed on the surface of the heating plate, the heating plate comprises a temperature control array 21, and the temperature control array 2021 is connected with the temperature analysis module for baking the mask 10 placed on the surface of the heating plate 20.
Optionally, the temperature analysis module is configured to determine a baking temperature of each sub-region in the PSM substrate according to a mask pattern formed on the PSM substrate of the mask 10, where the baking temperature of each sub-region corresponds to a pattern distribution density of each grid of the mask pattern, optionally, the mask 10 is the exposed mask 10, and the photoresist on the PSM substrate of the exposed mask 10 is exposed with the mask pattern, where the mask pattern may be an original pattern file before exposure, and the baking temperature is a temperature required when performing a baking operation on each sub-region.
Optionally, before baking, after obtaining the mask pattern, rasterizing the mask pattern to obtain a pattern distribution density corresponding to each grid, further determining a baking temperature corresponding to each grid according to the pattern distribution density corresponding to each grid, obtaining a coordinate corresponding to each grid, determining a sub-region corresponding to each grid according to the coordinate, and determining the baking temperature corresponding to each grid as the baking temperature of each sub-region in the PSM substrate, where the pattern distribution densities corresponding to different grids may be different or the same, and fig. 5 shows a schematic diagram of a mask pattern.
Optionally, the temperature analysis module includes a light transmittance calculation unit (not shown) that divides the mask pattern into respective cells according to the mask pattern, and determines light transmittance of the respective cells according to pattern distribution density of the respective cells, determining the light transmittance of each sub-area according to the light transmittance of each grid, optionally, determining the light transmittance of each sub-area according to the pattern distribution density of each grid, after the light transmittance of each subarea is determined, the baking temperature of each subarea is determined according to the light transmittance of each subarea, alternatively, the higher the transmittance, the higher the distribution density of the pattern representing the grid corresponding to the sub-area, the more photoresist distributed in the subarea, the more heat is needed for the photoresist to carry out chemical reaction, so the baking temperature needed by the subarea is higher; conversely, the smaller the transmittance is, the lower the pattern distribution density of the grid corresponding to the sub-region is, the less the photoresist is distributed in the sub-region, and the less the heat required is for the region with more photoresist, so that the baking temperature corresponding to the sub-region is lower than that of the sub-region with high transmittance. It can be understood that the temperature analysis module determines the baking temperature of each sub-region according to the light transmittance corresponding to each sub-region, so that the pertinence and the accuracy of the baking temperature of each sub-region are improved, the sub-region with high pattern distribution density is prevented from having insufficient heat to react, the reaction rate is low, the reaction efficiency of the sub-region with low pattern distribution density is higher than that of the sub-region with high pattern distribution density, the chemical reaction efficiency of each sub-region is inconsistent, and the image size uniformity of the mask plate is influenced.
Optionally, when the temperature analysis module calculates the baking temperature corresponding to the pattern distribution density of each grid of the mask pattern, the temperature analysis module performs digital-to-analog conversion on the light transmittance corresponding to each grid, and determines the baking temperature corresponding to each sub-area (grid) in a manner of converting light transmittance data at a unit coordinate into PDI to complete accurate point-to-point temperature control, referring to fig. 6, which is an exemplary diagram illustrating the determination of the baking temperature of each sub-area (grid).
Optionally, after the baking temperature of each sub-region is determined, the temperature control array 20 is controlled to provide the corresponding baking temperature for each corresponding sub-region, optionally, the temperature control array 2021 includes a plurality of temperature adjusting units 211, each temperature adjusting unit 211 corresponds to each sub-region of the mask, and is configured to adjust the temperature of each sub-region to the corresponding baking temperature, where the manner of adjusting to the corresponding baking temperature includes heating and cooling, that is, increasing the temperature or decreasing the temperature.
Optionally, the temperature control array 20 further includes a temperature sensor 2112, each temperature sensor is installed in each temperature adjustment unit, each temperature sensor corresponds to each temperature adjustment unit and each sub-area, the temperature sensor is connected to the temperature analysis module, and is configured to measure an actual temperature of each sub-area and send the actual temperature of each sub-area to the temperature analysis module, so that the temperature analysis module controls the temperature adjustment unit to adjust the temperature of each sub-area to the baking temperature according to a difference between the actual temperature and the baking temperature, it can be understood that, if the actual temperature is lower than the baking temperature, the temperature adjustment unit is controlled to perform a heating operation on the corresponding sub-area to raise the temperature of the area to the baking temperature, and vice versa, and if the actual temperature is higher than the baking temperature, controlling the temperature adjusting unit to refrigerate to the corresponding sub-area so as to adjust the temperature of the sub-area to be lower than the baking temperature.
Optionally, the manner in which the temperature analysis module controls the temperature adjustment unit to adjust the temperature of each sub-region to the baking temperature according to the difference between the actual temperature and the baking temperature includes that the temperature analysis module performs a difference according to the actual temperature and the baking temperature after acquiring the actual temperature and the baking temperature corresponding to each sub-region, so as to acquire a temperature difference between the actual temperature and the baking temperature corresponding to each sub-region, and further determines the working parameters of the temperature adjustment unit corresponding to each sub-region according to the temperature difference corresponding to each sub-region, the working parameters include a working mode and a temperature compensation value, the working mode includes a cooling mode and a heating mode, the temperature compensation value corresponds to the temperature difference value, and after determining the working parameters of each temperature adjustment unit, and controlling each temperature adjusting unit to adjust the temperature of each sub-area to the baking temperature according to the working parameters so that the actual temperature of each sub-area reaches the baking temperature.
Optionally, in order to achieve the purpose of temperature compensation, the temperature adjustment unit provided by the present application includes a semiconductor refrigeration module and a dc power supply controller, the semiconductor refrigeration module is connected to the dc power supply controller, after the temperature adjustment unit determines each corresponding working parameter, the dc power supply controller determines a current direction and a current value according to the working parameter, the current direction corresponds to the working mode, and different working modes correspond to different current directions.
Optionally, the current value is used to compensate the actual temperature of each sub-region, the working current corresponds to the temperature compensation value, the current values corresponding to different temperature compensation values are different, the larger the absolute value of the temperature compensation value is, the larger the current value is, the smaller the absolute value of the temperature compensation value is, and the smaller the current value is.
Optionally, after the current direction and the current value are determined, the dc power controller inputs a corresponding current value to the semiconductor refrigeration module in the current direction, so that the semiconductor refrigeration module provides a corresponding temperature difference value to a corresponding sub-region, that is, provides a corresponding temperature compensation value to the corresponding sub-region, so that the actual temperature of each sub-region reaches the baking temperature corresponding to each sub-region.
Optionally, the semiconductor chip mask photoresist baking equipment further comprises a constant bottom temperature control module, wherein the constant bottom temperature control module is used for providing preset heating temperature for the mask to be baked, so that the temperature of each sub-region of the mask can be maintained at the preset heating temperature, the continuous stability of the whole space of the internal environment of the whole baking equipment and the thermal field of the peripheral thermal radiation is kept, the temperature of the mask is rapidly increased to the preset heating temperature, and the baking efficiency of the mask is improved.
Optionally, the preset heating temperature may be set by a user, and the preset heating temperature may be less than or equal to a minimum baking temperature of the baking temperatures corresponding to the sub-regions.
Optionally, the constant bottom temperature control module is connected to the temperature analysis module, and the temperature analysis module is configured to set the preset heating temperature and control the constant bottom temperature control module 50 to provide a constant bottom temperature of the preset heating temperature to the mask 10 according to the preset heating temperature.
Optionally, invariable bottom temperature control module includes hot air circulating system 50, hot air circulating system 50 set up in heating module below, hot air circulating system 50 includes hot air circulating pipeline 51 and vortex circulation heat dissipation wind channel 52, refer to fig. 4, and fig. 4 shows the schematic diagram of vortex circulation heat dissipation wind channel 52, the inside canalis spinalis that sets to the trapezoidal form in vortex circulation heat dissipation wind channel 52, the canalis spinalis includes vortex heat dissipation perk face and lower vortex heat dissipation perk face, vortex circulation heat dissipation wind channel 52's entrance point with hot air circulating pipeline 51 is connected.
Optionally, the heated air circulation pipeline 51 includes an air return temperature compensation infrared heating controller 511, a circulating fan air supply system 512 and an air inlet temperature compensation infrared heating controller 513, the air return temperature compensation infrared heating controller 511 and the air inlet temperature compensation infrared heating controller 513 are in under the power support of the circulating fan air supply system 512, the heated air is connected through the heated air circulation pipeline 51 the inlet end of the turbulent flow circulation heat dissipation air duct 52 is fed into the inlet end of the turbulent flow circulation heat dissipation air duct 52, so that the turbulent flow circulation heat dissipation air duct 52 transfers the heat of the heated air to the mask 10.
It can be understood that, after the air after heating enters the turbulent flow circulation heat dissipation air duct 52, the air can flow through the outlet end of the turbulent flow circulation heat dissipation air duct 52 from the inlet end of the turbulent flow circulation heat dissipation air duct 52, along with the increase of the distance that the air flows through the turbulent flow circulation heat dissipation air duct 52, the temperature at the inlet end can be higher, along with the increase of the distance, the temperature can be gradually reduced towards the outlet end, and can be reduced based on the temperature, so that the heating unevenness of each subarea of the mask 10 is easily caused, based on this, the embodiment of the present application sets the inner part of the turbulent flow circulation heat dissipation air duct 52 into the tapered tube in the trapezoidal shape, thereby relieving the reduction efficiency of the temperature, and calculates and increases the upper and lower turbulent flow heat dissipation tilted surfaces by utilizing the surface area integral linear heat dissipation temperature equalization principle, the surface areas of the upper turbulent flow heat dissipation tilted surface and the lower turbulent flow heat dissipation tilted surface increase from the outlet end of the turbulent flow circulation heat dissipation air duct to the inlet end, the upper surface and the lower surface of the mask plate are uniformly heated, and the heat transfer quantity of the inlet end, the outlet end and the upper surface and the lower surface of the mask plate are consistent, so that the problem of uneven heating quantity caused by the fact that temperature heat dissipation is gradually reduced along with the flow direction is solved, and the conduction temperature difference effect is eliminated.
Optionally, in order to further improve the baking efficiency, the embodiment of the present application is further provided with a liquid state flow equalizing heat conducting device 53, the liquid-state flow-equalizing heat-conducting device 53 is disposed between the heating plate and the hot air circulating system 50, and is connected with the hot air circulating system 50, specifically, the liquid-state flow-equalizing and heat-conducting device 53 includes a liquid-state sensing liquid with a high heat capacity ratio, in the process that the disturbed flow circulation heat dissipation air duct 52 provides heat for the mask 10, the heat transferred by the disturbed flow circulation heat dissipation air duct 52 is transferred to the mask 10 by the liquid-state heat-equalizing and conducting device 53, and based on the sensing liquid with high liquid heat capacity ratio in the liquid-state heat-equalizing and conducting device 53, the small temperature fluctuation brought by the hot air circulation system 50 can be more stable, thereby providing a more stable, constant base temperature for the temperature control array 20, maintaining a constant thermal field of thermal radiation throughout the space and around.
Optionally, the semiconductor chip reticle photoresist baking apparatus includes, but is not limited to, the above-described module, and further includes an environment cleaning and maintaining system 60 for providing a stable airflow environment for baking the reticle.
In the embodiment of the application, a temperature analysis module and a temperature adjustment array 21 including a plurality of temperature adjustment units 2111 are provided, during the actual baking of the mask, grid-coordinate is provided for the mask pattern, the pattern distribution density corresponding to each grid of each mask pattern is determined, the transmittance corresponding to each grid is converted in proportion according to the pattern distribution density, analog-to-digital conversion is performed on the transmittance to obtain the baking temperature corresponding to each sub-area of the PSM substrate, the temperature adjustment units 2111 are further controlled to adjust the baking temperature of each sub-area to the respective baking temperature, it is ensured that the corresponding heat received in the areas with dense patterns is more, the corresponding heat received in the areas with sparse patterns is less, and the reaction efficiency uniformity of each sub-area is improved, thereby improving the image size uniformity of the mask, providing less heat for the areas with high pattern distribution density based on providing more heat for the areas with high pattern distribution density, and determining that the areas with high pattern distribution density (fine pattern) can react with the developing solution more quickly during development, and the areas with low pattern distribution density (large pattern) can react with the developing solution more quickly because the transferred heat is less than the areas with high pattern distribution density, even if the developing solution permeates more quickly, based on lower heat, the chemical effect speed during development tends to be consistent with the chemical effect speed of the areas with high pattern distribution density, thereby balancing the problem that the chemical reaction speed is inconsistent due to different pattern distribution densities, and solving the problem that the chemical reaction speed is different between the fine pattern and the large pattern and the developing solution due to slower permeation of the developing solution into the pattern during development of the fine pattern, the uniformity of the pattern size (CD) is influenced, thereby improving the uniformity of the image size of the mask, reducing the deviation degree of the process procedure between the pattern baked on the mask before development and the actual pattern formed after development, and improving the processing effect of the mask.
Referring to fig. 7, a first embodiment of the method for baking a phase shift mask photoresist for a semiconductor chip according to the present invention provides a method for baking a phase shift mask photoresist for a semiconductor chip, the method for baking a phase shift mask photoresist for a semiconductor chip comprising:
step S10, obtaining a mask pattern on the exposed photoresist on the PSM substrate of the mask, and rasterizing the mask pattern to obtain a plurality of grids corresponding to the mask pattern;
step S20, determining the baking temperature corresponding to each sub-area in the PSM substrate according to the pattern distribution density of each grid, wherein each sub-area corresponds to each grid;
and step S30, providing corresponding baking temperatures for the sub-regions according to the baking temperatures, so as to perform baking operation on the exposed mask.
In this embodiment, the method is applied to the semiconductor chip mask photoresist baking equipment, the mask is a phase shift mask, the photoresist of the phase shift mask is an electronic photoresist, the phase shift mask is exposed by using an electron beam, and the exposed photoresist is baked by the baking equipment.
Optionally, the mask pattern may be an original pattern file before exposure, before baking, after obtaining the mask pattern, grid-coordinating the mask pattern to obtain a pattern distribution density corresponding to each grid, further determining a baking temperature corresponding to each grid according to the pattern distribution density corresponding to each grid, determining a sub-region corresponding to each grid according to the coordinates corresponding to each grid, and determining the baking temperature corresponding to each grid as the baking temperature of each sub-region in the PSM template, where the pattern distribution densities corresponding to different grids may be different or the same, and fig. 5 shows a schematic diagram of the mask pattern. It is understood that the pattern distribution density is proportional to the baking temperature, and that the higher the pattern distribution density, the higher the amount of heat required for the reaction to occur, i.e., the higher the required baking temperature, and the lower the pattern distribution density, the lower the amount of heat required for the reaction to occur, i.e., the lower the required baking temperature.
Optionally, determining the baking temperature corresponding to each grid as the baking temperature of each sub-region in the PSM template is as follows: and determining the area distribution position of each sub-area according to the grid distribution position of each grid in the mask pattern and the mask, and enabling each grid to correspond to each sub-area according to the area distribution position, so that the baking temperature of each sub-area can be controlled according to the pattern distribution density of each grid during subsequent baking.
Optionally, after determining the sub-regions on the PSM template corresponding to each grid, corresponding each sub-region to each temperature adjusting unit of the temperature control array one-to-one, and after determining the baking temperature corresponding to each sub-region, controlling each temperature adjusting unit to adjust each sub-region to the corresponding baking temperature, so as to achieve the purpose of providing the corresponding baking temperature for each sub-region according to the baking temperature.
Optionally, the semiconductor chip mask photoresist baking apparatus further includes a constant bottom temperature control module, the constant bottom temperature control module includes a hot air circulation system and a liquid flow equalizing and guiding device, the constant bottom temperature module is configured to provide a thermal field of continuous-temperature thermal radiation for a space where the mask is located, the manner of controlling each temperature adjusting unit to adjust each sub-region to a corresponding baking temperature may be to obtain an actual temperature of each sub-region under control of the constant bottom temperature control module, and provide corresponding temperature compensation for each sub-region according to a temperature difference between the actual temperature and the baking temperature, the temperature compensation includes temperature positive compensation and temperature negative compensation, the temperature positive compensation includes increasing an actual temperature of the sub-region to the baking temperature according to the temperature difference, the temperature negative compensation includes decreasing the actual temperature of the sub-region to the baking temperature according to the temperature difference, optionally, when the actual temperature is lower than the baking temperature, the temperature compensation is positive compensation, and when the actual temperature is higher than the baking temperature, the temperature compensation is negative compensation.
Optionally, referring to fig. 8, fig. 8 is a schematic view illustrating a complete process of baking a phase shift mask, where the heat transfer direction is transferred from a hot air circulation system to a liquid flow-equalizing heat conduction device, and then the heat is transferred to the temperature control array through the liquid flow-equalizing heat conduction device, and after the heat is subjected to temperature compensation by the temperature control array, each sub-region of the PSM substrate is precisely baked.
In the embodiment of the application, in the process of baking the mask, grid coordinates are carried out on the mask graph to obtain each grid in the mask graph, each grid corresponds to each subarea coordinate of a PSM substrate of the mask one by one, the baking temperature of each subarea is further determined according to the distribution density of each grid, and the corresponding baking temperature is provided for each subarea according to the baking temperature to carry out the baking operation on the exposed mask, in the embodiment of the application, more heat is provided for the subarea corresponding to the high distribution density of the graph, less heat is provided for the subarea corresponding to the low distribution density of the graph, the chemical reaction rate of each subarea is balanced, so that the size uniformity of the graph is improved, and the process deviation degree between the graph baked before the mask and the actual graph formed after the development on the mask is reduced, the mask plate processing effect is improved.
Alternatively, based on the first embodiment, referring to fig. 9, the S20 includes:
step S21, determining the light transmittance corresponding to each grid according to the graph distribution density of each grid;
and step S22, determining the baking temperature corresponding to each subarea according to the light transmittance, wherein the higher the light transmittance is, the lower the baking temperature is, and the lower the light transmittance is, the higher the baking temperature is.
In this embodiment, the baking temperature is inversely proportional to the light transmittance, and the light transmittance is inversely proportional to the pattern distribution density, that is, the greater the image distribution density of the grid, the lower the light transmittance is, the higher the baking temperature required by the sub-area corresponding to the grid is, the smaller the pattern distribution density of the grid is, the higher the light transmittance is, and the lower the baking temperature required by the sub-area corresponding to the grid is.
Optionally, after the light transmittance of each grid is determined according to the graph distribution density of each grid, digital-to-analog conversion is performed on the light transmittance corresponding to each grid, and the baking temperature corresponding to each sub-area (grid) is determined in a manner that light transmittance data at a unit coordinate is converted into PDI, so as to complete point-to-point temperature accurate control.
In this application embodiment, after the figure distribution density that each grid corresponds is obtained, the luminousness that each grid corresponds is confirmed according to the figure distribution density that each grid corresponds, and then confirms the stoving temperature that the subregion that each grid corresponds according to the luminousness that each grid corresponds, this application embodiment is through converting figure distribution density into luminousness, and then confirms the mode of stoving temperature through the luminousness and accurately obtain the required stoving temperature of each subregion, has improved temperature control's precision and pertinence.
Alternatively, based on the first embodiment, referring to fig. 10, the S30 includes:
s31, acquiring actual temperatures corresponding to the sub-regions, and acquiring the baking temperature and the temperature difference of the actual temperatures;
s32, providing the temperature difference value for the corresponding sub-area, so that the temperature of each sub-area reaches the baking temperature.
In the embodiment of the application, corresponding temperature sensors are arranged in the temperature adjusting units and correspond to the sub-regions, in the actual baking process, constant bottom temperature is provided for the mask through a constant bottom temperature control module, the temperature sensors respectively detect the actual temperatures of the corresponding sub-regions, the actual temperatures are the temperatures of the sub-regions after the constant bottom temperature control module performs baking, and the actual temperatures can also be the temperatures of the sub-regions after the temperature adjusting units perform adjustment. It can be understood that the temperature sensor provided in the embodiment of the present application can detect the temperature of each sub-region in real time, and control the temperature adjusting unit to adjust each sub-region according to the detected temperature in real time, so that the temperature of each sub-region reaches the baking temperature.
Optionally, the manner of controlling the temperature adjustment unit to adjust each sub-region according to the detected temperature in real time includes: the method comprises the steps of obtaining a temperature difference value between the actual temperature and the baking temperature, determining working parameters of temperature adjusting units corresponding to the sub-regions according to the temperature difference value corresponding to each sub-region, wherein the working parameters comprise a working mode and a temperature compensation value, the working mode comprises a refrigeration mode and a heating mode, and after the working parameters of each temperature adjusting unit are determined, controlling each temperature adjusting unit to adjust the temperature of each sub-region to the baking temperature according to the working parameters so that the actual temperature of each sub-region can reach the baking temperature, and optionally, the temperature compensation value corresponds to the temperature difference value.
Optionally, the temperature adjusting unit includes a semiconductor refrigeration module and a dc power controller, the semiconductor refrigeration module is connected to the dc power controller, and after the temperature adjusting unit determines each corresponding working parameter, the dc power controller determines a current direction and a current value according to the working parameter, the current direction corresponds to the working mode, and different working modes correspond to different current directions.
Optionally, the current value is used to compensate the actual temperature of each sub-region, the working current corresponds to the temperature compensation value, the current values corresponding to different temperature compensation values are different, the larger the absolute value of the temperature compensation value is, the larger the current value is, the smaller the absolute value of the temperature compensation value is, and the smaller the current value is.
Optionally, after the current direction and the current value are determined, the dc power controller inputs a corresponding current value to the semiconductor refrigeration module in the current direction, so that the semiconductor refrigeration module provides a corresponding temperature difference value to a corresponding sub-region, that is, provides a corresponding temperature compensation value to the corresponding sub-region, so that the actual temperature of each sub-region reaches the baking temperature corresponding to each sub-region.
In the embodiment of the application, the actual temperature of each sub-area is detected in real time, and each temperature adjusting unit is controlled to provide corresponding temperature compensation for each sub-area according to the temperature difference between the actual temperature and the baking temperature, so that the temperature of each sub-area is controlled to be at the corresponding baking temperature, the heat correspondingly received by the area with dense patterns is larger, the heat correspondingly received by the area with sparse patterns is smaller, the reaction efficiency uniformity of each sub-area is improved, the image size uniformity of the mask plate is improved, and less heat is provided for the area with lower pattern distribution density based on providing more heat for the area with high pattern distribution density, so that the area with high pattern distribution density (fine pattern) can be determined to react with the developing solution more quickly during development, and the area with low pattern distribution density (large pattern) can be determined to be smaller than the pattern distribution density due to the transferred heat The method has the advantages that even though the developing solution permeates more quickly, the heat is low, the chemical effect rate during development tends to be consistent with the chemical effect rate of an area with high pattern distribution density, the problem that the chemical reaction rate is inconsistent due to different pattern distribution densities is solved, and the problem that the pattern size (CD) uniformity is influenced due to the fact that the developing solution permeates into the patterns slowly relative to a large-size pattern when a fine-size pattern is developed, the chemical reaction rate of the fine-size pattern and the large-size pattern is different from that of the developing solution, so that the image size uniformity of the mask plate is improved, the process deviation degree between the pattern baked on the mask plate before development and the actual pattern formed after development is reduced, and the mask plate pattern precision and the mask pattern uniformity effect are improved.
In addition, an embodiment of the present invention further provides a storage medium, where the storage medium stores a phase shift mask photoresist baking program for a semiconductor chip, and the phase shift mask photoresist baking program for a semiconductor chip implements the steps of the above embodiments when executed by a processor.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. The semiconductor chip mask photoresist baking equipment is characterized by comprising a temperature analysis module and a heating module, wherein the heating module comprises a heating plate and is used for baking masks placed on the surface of the heating plate, the heating plate comprises a temperature control array, and the temperature control array is connected with the temperature analysis module;
the temperature analysis module is used for determining the baking temperature of each sub-area in a PSM substrate according to a mask pattern formed on the PSM substrate of the mask, wherein the baking temperature of each sub-area corresponds to the pattern distribution density of each grid of the mask pattern;
the temperature control array comprises a plurality of temperature adjusting units, the temperature adjusting units are connected with the temperature analysis module and used for adjusting the temperature of each sub-area to the corresponding baking temperature so as to perform baking operation on the mask, and each temperature adjusting unit corresponds to each sub-area of the PSM substrate.
2. The semiconductor chip reticle photoresist baking apparatus of claim 1, wherein the temperature analysis module comprises a light transmittance calculation unit that divides the mask pattern into individual grids according to the mask pattern and determines light transmittance of individual sub-regions according to image distribution density of the individual grids;
after the light transmittance of each sub-area is determined, the baking temperature of each sub-area is determined according to the light transmittance of each sub-area, wherein the higher the light transmittance is, the lower the baking temperature is, the lower the light transmittance is, and the higher the baking temperature is.
3. The semiconductor chip reticle photoresist baking apparatus of claim 1, wherein the temperature control array further comprises a temperature sensor mounted in each temperature adjustment unit for measuring an actual temperature of each sub-region, the temperature sensor being connected to the temperature analysis module for sending the detected actual temperature of the corresponding sub-region to the temperature analysis module;
the temperature analysis module determines working parameters of each temperature adjusting unit according to the actual temperature and the temperature difference value of the baking temperature, and sends the working parameters to each temperature adjusting unit so that the temperature adjusting unit adjusts the temperature of each sub-area to the corresponding baking temperature according to the corresponding working parameters, the working parameters comprise a working mode and a temperature compensation value, and the working mode comprises a working mode refrigerating mode and a heating mode.
4. The semiconductor chip reticle photoresist baking apparatus of claim 3, wherein the temperature adjustment unit comprises a semiconductor refrigeration module and a DC power controller, the semiconductor refrigeration module being connected to the DC power controller;
and the direct current power controller determines a current direction and a current value according to the working parameters, and inputs a corresponding current value to the semiconductor refrigeration module in the current direction so that the semiconductor refrigeration module provides a corresponding temperature difference value for a corresponding sub-region.
5. The semiconductor chip reticle photoresist baking apparatus of claim 1, further comprising a constant base temperature control module connected to the temperature analysis module for providing a preset heating temperature to a reticle placed on the heating plate;
invariable bottom temperature control module includes hot air circulating system, hot air circulating system includes hot air circulating pipeline and vortex circulation heat dissipation wind channel, the hot air circulating pipeline with the entrance point connection in vortex circulation heat dissipation wind channel, the inside canalis spinalis that is the trapezoidal form that sets up in vortex circulation heat dissipation wind channel, the canalis spinalis includes vortex heat dissipation perk face and lower vortex heat dissipation perk face, go up vortex heat dissipation perk face and the surface area of lower vortex heat dissipation perk face and follow the exit end in entrance point to vortex circulation heat dissipation wind channel is linear proportion and increases progressively.
6. The semiconductor chip reticle photoresist baking apparatus of claim 5, wherein the constant bottom temperature control module further comprises a liquid flow equalizing and heat conducting device disposed below the heating plate and connected to the hot air circulation system.
7. A method for baking a photoresist of a phase shift mask for a semiconductor chip is applied to the photoresist baking equipment of the mask for the semiconductor chip according to any one of claims 1 to 6, and the method for baking the photoresist of the phase shift mask for the semiconductor chip comprises the following steps:
obtaining a mask pattern on the exposed photoresist on a PSM substrate of a mask, and rasterizing the mask pattern to obtain a plurality of grids corresponding to the mask pattern;
determining the baking temperature corresponding to each sub-area in the PSM substrate according to the pattern distribution density of each grid, wherein each sub-area corresponds to each grid;
and providing corresponding baking temperatures for the sub-regions according to the baking temperatures so as to perform baking operation on the exposed mask.
8. The method of claim 7, wherein determining the baking temperature for each sub-region of the PSM substrate based on the pattern distribution density of each grid comprises:
determining the light transmittance corresponding to each grid according to the pattern distribution density of each grid;
and determining the baking temperature corresponding to each sub-area according to the light transmittance, wherein the higher the light transmittance is, the lower the baking temperature is, and the lower the light transmittance is, the higher the baking temperature is.
9. The method of claim 7, wherein the step of providing a corresponding baking temperature for each of the sub-regions according to the baking temperature to perform a baking operation on the exposed reticle comprises:
acquiring actual temperatures corresponding to all the sub-areas, and acquiring the baking temperature and the temperature difference value of the actual temperatures;
providing the temperature difference value to the corresponding sub-area so that the temperature of each sub-area reaches the baking temperature.
10. A storage medium having stored thereon a phase shift mask photoresist baking program for a semiconductor chip, the phase shift mask photoresist baking program for a semiconductor chip, when executed by a processor, implementing the steps of the phase shift mask photoresist baking method for a semiconductor chip according to any one of claims 7 to 9.
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| JPH09330873A (en) * | 1996-06-13 | 1997-12-22 | Mitsubishi Electric Corp | Bake oven |
| JPH11274030A (en) * | 1998-03-20 | 1999-10-08 | Hitachi Ltd | Method and device for resist processing, and method for coating resist |
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Address after: 518000 The first floor of plant 4 #, Shengzuozhi Science and Technology Industrial Park, north of Xinyu Road, Shajing Street, Bao'an District, Shenzhen, Guangdong Patentee after: Shenzhen Longtu Optical Mask Co.,Ltd. Address before: 518000 The first floor of plant 4 #, Shengzuozhi Science and Technology Industrial Park, north of Xinyu Road, Shajing Street, Bao'an District, Shenzhen, Guangdong Patentee before: SHENZHEN LONGTU PHOTOMASK CO.,LTD. |