JPH0563967B2 - - Google Patents

Info

Publication number
JPH0563967B2
JPH0563967B2 JP63502395A JP50239588A JPH0563967B2 JP H0563967 B2 JPH0563967 B2 JP H0563967B2 JP 63502395 A JP63502395 A JP 63502395A JP 50239588 A JP50239588 A JP 50239588A JP H0563967 B2 JPH0563967 B2 JP H0563967B2
Authority
JP
Japan
Prior art keywords
circuit
gate
supply potential
transfer
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63502395A
Other languages
English (en)
Japanese (ja)
Other versions
JPH02501613A (ja
Inventor
Kuruto Hofuman
Osukaaru Kowariiku
Rainaa Kurausu
Hansuudeiitaa Oberure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of JPH02501613A publication Critical patent/JPH02501613A/ja
Publication of JPH0563967B2 publication Critical patent/JPH0563967B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
JP63502395A 1987-03-16 1988-03-15 Ｍｏｓトランジスタを有するゲート回路 Granted JPH02501613A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE3708534 1987-03-16
DE3708534.4 1987-03-16
DE3805798 1988-02-24
DE3805798.0 1988-02-24

Publications (2)

Publication Number Publication Date
JPH02501613A JPH02501613A (ja) 1990-05-31
JPH0563967B2 true JPH0563967B2 (enrdf_load_stackoverflow) 1993-09-13

Family

ID=25853544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63502395A Granted JPH02501613A (ja) 1987-03-16 1988-03-15 Ｍｏｓトランジスタを有するゲート回路

Country Status (8)

Country Link
US (1) US5030861A (enrdf_load_stackoverflow)
EP (1) EP0349557B1 (enrdf_load_stackoverflow)
JP (1) JPH02501613A (enrdf_load_stackoverflow)
KR (1) KR960009402B1 (enrdf_load_stackoverflow)
AT (1) ATE68298T1 (enrdf_load_stackoverflow)
DE (1) DE3865432D1 (enrdf_load_stackoverflow)
HK (1) HK106093A (enrdf_load_stackoverflow)
WO (1) WO1988007292A1 (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4857768A (en) * 1988-04-27 1989-08-15 Sun Microsystems, Inc. Triple rail logic gate
FR2666183B1 (fr) * 1990-08-23 1992-11-06 Bull Sa Circuit a constante de temps reglable et application a un circuit a retard reglable.
US5111069A (en) * 1990-08-27 1992-05-05 Dallas Semiconductor Corporation Layout of integrated circuit with very large transistors
FR2666424B1 (fr) * 1990-08-30 1992-11-06 Bull Sa Procede et dispositif de reglage des signaux d'horloge dans un systeme synchrone.
US5744995A (en) * 1996-04-17 1998-04-28 Xilinx, Inc. Six-input multiplexer wtih two gate levels and three memory cells
US6020776A (en) * 1998-06-22 2000-02-01 Xilinx, Inc. Efficient multiplexer structure for use in FPGA logic blocks

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468574A (en) * 1982-05-03 1984-08-28 General Electric Company Dual gate CMOS transistor circuits having reduced electrode capacitance
JPH0616586B2 (ja) * 1983-07-15 1994-03-02 株式会社日立製作所 Ｎ ｏ ｒ 回 路
JPS60120615A (ja) * 1983-12-02 1985-06-28 Toshiba Corp 論理回路
US4590391A (en) * 1983-12-19 1986-05-20 Unitrode Corporation Multi-input zero offset comparator
US4595845A (en) * 1984-03-13 1986-06-17 Mostek Corporation Non-overlapping clock CMOS circuit with two threshold voltages

Also Published As

Publication number Publication date
US5030861A (en) 1991-07-09
JPH02501613A (ja) 1990-05-31
KR960009402B1 (en) 1996-07-18
EP0349557B1 (de) 1991-10-09
ATE68298T1 (de) 1991-10-15
DE3865432D1 (de) 1991-11-14
WO1988007292A1 (en) 1988-09-22
EP0349557A1 (de) 1990-01-10
HK106093A (en) 1993-10-15
KR890700970A (ko) 1989-04-28

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