JPH0563685A - Inter-carrier delay difference adjustment device - Google Patents
Inter-carrier delay difference adjustment deviceInfo
- Publication number
- JPH0563685A JPH0563685A JP3223787A JP22378791A JPH0563685A JP H0563685 A JPH0563685 A JP H0563685A JP 3223787 A JP3223787 A JP 3223787A JP 22378791 A JP22378791 A JP 22378791A JP H0563685 A JPH0563685 A JP H0563685A
- Authority
- JP
- Japan
- Prior art keywords
- delay
- data signal
- delay difference
- carrier
- inter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はマルチキャリアディジタ
ル無線通信システムに適用するキャリア間遅延差調整器
に関し、特に現用回線と予備回線とをマトリクス同期切
替えするために予備回線のキャリア間の遅延差を調整す
るキャリア間遅延差調整器に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-carrier delay difference adjuster applied to a multi-carrier digital radio communication system, and more particularly to a delay difference between carriers of a protection line for matrix synchronous switching between a working line and a protection line. The present invention relates to an inter-carrier delay difference adjuster for adjusting.
【0002】[0002]
【従来の技術】一般に、マルチキャリアディジタル無線
通信システムでは、フェージング等により現用回線の品
質が劣化した場合、送端側および受端側において、マト
リクス同期切替器によって正常なキャリアを選択し、キ
ャリアごとに現用回線から予備回線へ切替えている。2. Description of the Related Art Generally, in a multi-carrier digital radio communication system, when the quality of a working line is deteriorated due to fading or the like, a normal carrier is selected by a matrix synchronization switch on the transmitting end side and the receiving end side, Is switching from the working line to the protection line.
【0003】この場合、現用回線の線路と予備回線の線
路との間には伝搬遅延差が存在するため、受端側におい
てこの遅延差を補償している。しかし、この伝搬遅延差
はキャリアごとに異なるので、予備回線のキャリア間に
生じる伝搬遅延差についても補償する必要があり、この
ためキャリア間遅延差調整器を設けている。In this case, since there is a propagation delay difference between the line of the working line and the line of the protection line, this delay difference is compensated for on the receiving end side. However, since this propagation delay difference differs for each carrier, it is also necessary to compensate for the propagation delay difference that occurs between carriers on the protection line. Therefore, an inter-carrier delay difference adjuster is provided.
【0004】従来のこの種のキャリア間遅延差調整器
は、シフトレジスタ等からなる遅延回路で構成されてお
り、予備回線を介して伝送されてきた信号を各遅延回路
で所定量遅延させることにより、キャリア間の遅延差を
補償している。This type of conventional inter-carrier delay difference adjuster is composed of a delay circuit composed of a shift register or the like, and delays a signal transmitted through a protection line by a predetermined amount in each delay circuit. , The delay difference between carriers is compensated.
【0005】ところで、遅延回路を調整する際は、予備
回線を介して伝送されてきた各データ信号列、および各
データ信号列と共に伝送されてきたフレーム同期パルス
を、それぞれ遅延回路で遅延させ、遅延回路を通過した
各フレーム同期パルスを観測しながら、全キャリアのフ
レーム同期パルスのタイミングが一致するように、各遅
延回路のシフトレジスタの遅延ビット数等を手動で調整
している。By the way, when adjusting the delay circuit, each data signal train transmitted through the protection line and the frame synchronization pulse transmitted together with each data signal train are delayed by the delay circuit, respectively, and delayed. While observing each frame synchronization pulse that has passed through the circuit, the number of delay bits in the shift register of each delay circuit is manually adjusted so that the timings of the frame synchronization pulses of all carriers match.
【0006】[0006]
【発明が解決しようとする課題】上述した従来のキャリ
ア間遅延差調整器では、システム建設時等にキャリア間
の遅延調整をする場合、遅延回路を通過した各フレーム
同期パルスをオシロスコープ等で観測し、各遅延回路の
シフトレジスタの遅延ビット数等を手動で調整しなけれ
ばならないため、調整作業が煩雑であるばかりでなく、
誤調整する可能性もあるという問題点を有している。In the conventional inter-carrier delay difference adjuster described above, when adjusting the delay between carriers when constructing a system or the like, each frame synchronization pulse that has passed through the delay circuit is observed with an oscilloscope or the like. Since the number of delay bits of the shift register of each delay circuit must be manually adjusted, not only the adjustment work is complicated, but also
There is a problem that there is a possibility of making an erroneous adjustment.
【0007】本発明の目的は、システム建設時等にキャ
リア間の遅延調整をする場合、キャリア間の遅延調整を
自動的に行うことにより調整作業が簡略化でき、誤調整
を防止できるキャリア間遅延差調整器を提供することに
ある。An object of the present invention is to provide an inter-carrier delay which can simplify the adjustment work and prevent erroneous adjustment by automatically adjusting the inter-carrier delay when adjusting the inter-carrier delay during system construction. To provide a difference adjuster.
【0008】[0008]
【課題を解決するための手段】本発明のキャリア間遅延
差調整器は、n(nは2以上の整数)個のキャリアに対
してキャリアごとに現用回線から予備回線へマトリクス
同期切替えを行うマルチキャリアディジタル無線通信シ
ステムにおける予備回線のキャリア間遅延差調整器にお
いて、前記n個のキャリアにより前記予備回線を介して
伝送されてきたn個のデータ信号列の内最も遅れている
データ信号列を検出する手段と、前記最も遅れているデ
ータ信号列を基準として前記n個のデータ信号列の相対
遅延差を検出して遅延制御データを生成する手段と、前
記遅延制御データを記憶し出力する手段と、この記憶手
段から出力される遅延制御データに応じて前記n個のデ
ータ信号列のそれぞれに遅延を与え前記n個のデータ信
号列間の遅延差を一致させる手段とを備えて構成されて
いる。SUMMARY OF THE INVENTION An inter-carrier delay difference adjuster of the present invention is a multi-channel switch that performs matrix synchronous switching from a working line to a protection line for each of n (n is an integer of 2 or more) carriers. An inter-carrier delay difference adjuster for a protection line in a carrier digital wireless communication system detects the data signal sequence that is the most delayed among the n data signal sequences transmitted by the n carriers via the protection line. Means, means for detecting a relative delay difference between the n data signal sequences based on the most delayed data signal sequence to generate delay control data, and means for storing and outputting the delay control data. A delay difference is given to each of the n data signal sequences according to the delay control data output from the storage means. It is configured to include a means for Itasa.
【0009】[0009]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【0010】図1は本発明の一実施例を示すブロック図
である。ここで、データ信号列D1〜Dnは、n(nは
2以上の整数)個のキャリアにより予備回線を介して送
信側から伝送されてきたデータ信号列であり、予備回線
の受信装置の復調部(図示せず)によって受信復調され
たものである。また、フレーム同期パルスF1〜Fn
は、各データ信号列D1〜Dnのそれぞれにフレーム同
期したパルスであり、同様に受信装置のフレーム同期部
(図示せず)によって再生されたものである。FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the data signal sequences D1 to Dn are data signal sequences transmitted from the transmitting side via n (n is an integer of 2 or more) carriers via the protection line, and the demodulation unit of the reception device on the protection line. It is received and demodulated by (not shown). Further, the frame synchronization pulses F1 to Fn
Is a pulse that is frame-synchronized with each of the data signal sequences D1 to Dn and is similarly reproduced by a frame synchronization unit (not shown) of the receiving device.
【0011】さて、遅延回路1〜nは、遅延制御データ
S1〜Snに応じた遅延量を入力信号に与えて、受信端
マトリクス切替器(図示せず)へ出力する。この場合、
遅延回路i(1≦i≦n)は、データ信号列Diおよび
フレーム同期パルスFiに対して同じ遅延を与える。ま
た遅延制御データS1〜Snは、全キャリアのデータ信
号列およびフレーム同期パルスの位相が一致するように
設定される。ここで、遅延制御データS1〜Snを生成
するために、絶対遅延検出回路11と、相対遅延検出回
路12と、遅延データ記憶回路13とを設けている。The delay circuits 1 to n give a delay amount corresponding to the delay control data S1 to Sn to an input signal and output it to a receiving end matrix switch (not shown). in this case,
The delay circuit i (1 ≦ i ≦ n) gives the same delay to the data signal sequence Di and the frame synchronization pulse Fi. Further, the delay control data S1 to Sn are set so that the phases of the data signal trains of all carriers and the frame synchronization pulse match. Here, an absolute delay detection circuit 11, a relative delay detection circuit 12, and a delay data storage circuit 13 are provided to generate the delay control data S1 to Sn.
【0012】システム建設時、キャリア間遅延差調整器
の調整は次のように実行する。When the system is constructed, the adjustment of the inter-carrier delay difference adjuster is executed as follows.
【0013】まず、絶対遅延検出回路11は、データ信
号列D1〜Dnおよびフレーム同期パルスF1〜Fnを
それぞれ受け、n個のデータ信号列の内、最も遅延して
いるデータ信号列を検出し、検出情報Saを相対遅延検
出回路12へ送出する。また、相対遅延検出回路12
は、データ信号列D1〜Dnおよびフレーム同期パルス
F1〜Fn並びに検出情報Saにより、最も遅延してい
るデータ信号列を基準としてn個のデータ信号列間の相
対遅延差を検出し、遅延制御データS1〜Snを生成し
て遅延データ記憶回路13へ送出する。遅延データ記憶
回路13は、書込み読出しが可能な不揮発性記憶回路、
例えばEEPROM(electrically er
asable PROM)により構成され、遅延制御デ
ータS1〜Snを一旦記憶して遅延回路1〜nへ送出す
る。First, the absolute delay detection circuit 11 receives the data signal sequences D1 to Dn and the frame synchronization pulses F1 to Fn, respectively, and detects the most delayed data signal sequence among the n data signal sequences. The detection information Sa is sent to the relative delay detection circuit 12. In addition, the relative delay detection circuit 12
Is a delay control data for detecting a relative delay difference between n data signal sequences based on the most delayed data signal sequence based on the data signal sequences D1 to Dn, the frame synchronization pulses F1 to Fn, and the detection information Sa. S1 to Sn are generated and sent to the delay data storage circuit 13. The delay data storage circuit 13 is a writable and readable nonvolatile storage circuit,
For example, EEPROM (electrically er)
The delay control data S1 to Sn are temporarily stored and sent to the delay circuits 1 to n.
【0014】このようにすることにより、遅延回路1〜
nは、遅延制御データS1〜Snをそれぞれ受けて、全
キャリアのデータ信号列およびフレーム同期パルスの位
相が一致するように遅延を与えるので、受信端マトリク
ス切替器における同期切替が可能となる。By doing so, the delay circuits 1 to
n receives the delay control data S1 to Sn and gives a delay so that the phases of the data signal trains of all carriers and the frame synchronization pulse match, so that synchronous switching can be performed in the receiving end matrix switching device.
【0015】[0015]
【発明の効果】以上説明したように本発明によれば、遅
延制御データに応じて、キャリアのデータ信号列および
フレーム同期パルスの位相がそれぞれ一致するように遅
延を与える遅延回路をキャリアに対応してそれぞれ設
け、また、キャリア間遅延差調整器を調整する場合は、
複数のキャリアの内最も遅延しているデータ信号列を検
出し、この最も遅延しているデータ信号列を基準として
複数のキャリア間の相対遅延差を検出して遅延制御デー
タを生成し、更に、遅延制御データを保持し対応する遅
延回路へ送出することにより、予備回線のキャリア間に
生じる伝搬遅延差を補償するための遅延調整を自動的に
行うことができるので、調整作業が簡略化でき、誤調整
を防止できる。As described above, according to the present invention, a delay circuit for delaying the carrier data signal train and the phase of the frame sync pulse in accordance with the delay control data is provided for the carrier. When adjusting the inter-carrier delay difference adjuster,
Detects the most delayed data signal sequence of a plurality of carriers, generates a delay control data by detecting the relative delay difference between a plurality of carriers with reference to this most delayed data signal sequence, further, By holding the delay control data and sending it to the corresponding delay circuit, the delay adjustment for compensating for the propagation delay difference occurring between the carriers of the protection line can be automatically performed, so the adjustment work can be simplified, It can prevent erroneous adjustment.
【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.
1〜n 遅延回路 11 絶対遅延検出回路 12 相対遅延検出回路 13 遅延データ記憶回路 D1〜Dn データ信号列 F1〜Fn フレーム同期パルス S1〜Sn 遅延制御データ 1 to n delay circuit 11 absolute delay detection circuit 12 relative delay detection circuit 13 delay data storage circuit D1 to Dn data signal sequence F1 to Fn frame synchronization pulse S1 to Sn delay control data
Claims (1)
対してキャリアごとに現用回線から予備回線へマトリク
ス同期切替えを行うマルチキャリアディジタル無線通信
システムにおける予備回線のキャリア間遅延差調整器に
おいて、前記n個のキャリアにより前記予備回線を介し
て伝送されてきたn個のデータ信号列の内最も遅れてい
るデータ信号列を検出する手段と、前記最も遅れている
データ信号列を基準として前記n個のデータ信号列の相
対遅延差を検出して遅延制御データを生成する手段と、
前記遅延制御データを記憶し出力する手段と、この記憶
手段から出力される遅延制御データに応じて前記n個の
データ信号列のそれぞれに遅延を与え前記n個のデータ
信号列間の遅延差を一致させる手段とを備えることを特
徴とするキャリア間遅延差調整器。1. An inter-carrier delay difference adjuster for a protection line in a multi-carrier digital wireless communication system for performing matrix synchronization switching from a working line to a protection line for each of n (n is an integer of 2 or more) carriers. A means for detecting the most delayed data signal sequence of the n number of data signal sequences transmitted by the n number of carriers via the protection line, and the most delayed data signal sequence as a reference Means for detecting a relative delay difference between the n data signal strings to generate delay control data;
Means for storing and outputting the delay control data, and delaying each of the n data signal trains in accordance with the delay control data output from the storing device to obtain a delay difference between the n data signal trains. An inter-carrier delay difference adjuster comprising: means for matching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3223787A JP2658658B2 (en) | 1991-09-04 | 1991-09-04 | Delay difference adjuster between carriers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3223787A JP2658658B2 (en) | 1991-09-04 | 1991-09-04 | Delay difference adjuster between carriers |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0563685A true JPH0563685A (en) | 1993-03-12 |
JP2658658B2 JP2658658B2 (en) | 1997-09-30 |
Family
ID=16803709
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3223787A Expired - Lifetime JP2658658B2 (en) | 1991-09-04 | 1991-09-04 | Delay difference adjuster between carriers |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2658658B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6370200B1 (en) | 1997-08-04 | 2002-04-09 | Matsushita Electric Industrial Co., Ltd. | Delay adjusting device and method for plural transmission lines |
JP2007235318A (en) * | 2006-02-28 | 2007-09-13 | Fujitsu Ltd | Data receiving circuit |
-
1991
- 1991-09-04 JP JP3223787A patent/JP2658658B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6370200B1 (en) | 1997-08-04 | 2002-04-09 | Matsushita Electric Industrial Co., Ltd. | Delay adjusting device and method for plural transmission lines |
KR100546924B1 (en) * | 1997-08-04 | 2006-03-23 | 마츠시타 덴끼 산교 가부시키가이샤 | Delay adjusting device and method for plural transmission lines |
JP2007235318A (en) * | 2006-02-28 | 2007-09-13 | Fujitsu Ltd | Data receiving circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2658658B2 (en) | 1997-09-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4001692A (en) | Time diversity data transmission apparatus | |
US5872823A (en) | Reliable switching between data sources in a synchronous communication system | |
JP2006311559A (en) | Line-timing in packet-based network | |
MXPA02002227A (en) | Method, system and apparatus for reducing synchronization and resynchronization times for systems with pulse stuffing. | |
US5321727A (en) | Signal phasing arrangement in a system for doubling the digital channel | |
JP3125348B2 (en) | Parallel bit synchronization method | |
JP2658658B2 (en) | Delay difference adjuster between carriers | |
US6959011B2 (en) | Data transmission and reception system, data transmitter and data receiver | |
KR100304776B1 (en) | Synchronization system and method, and recording medium | |
EP0909491B1 (en) | Device and method for maintaining synchronization and frequency stability in a wireless telecommunication system | |
JP2603608B2 (en) | Propagation time difference correction circuit for switched space diversity digital wireless communication. | |
JP3674576B2 (en) | Line switching device | |
JP2785755B2 (en) | Hitless switching device | |
JPH01263566A (en) | System for measuring transmission delay difference | |
JP3655142B2 (en) | Mobile communication terminal device | |
JPH11284622A (en) | Multi-carrier system radio reception device | |
JP2820191B2 (en) | Carrier delay adjustment circuit | |
JP2713009B2 (en) | Delay time difference absorption device | |
JP2730519B2 (en) | Staff synchronization circuit | |
JP2621606B2 (en) | Line switching method | |
JPH0795186A (en) | Transmission line changeover device | |
JPH1093487A (en) | Delay correction system for radio calling system | |
JPH0767103B2 (en) | Delay adjustment circuit | |
JPH07221724A (en) | Changeover circuit for active/standby system | |
JPH0884136A (en) | Communication method and device for correcting delay of transmission line |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970506 |