JP2007235318A - Data receiving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data receiving circuit for further increasing in speed to transmit/receive data between common clock synchronized circuit modules. <P>SOLUTION: A delay circuit 42 delays an acknowledge signal ack1 from the circuit module 1_1 and outputs an acknowledge signal ack1d whose phase is equal to or delayed from the phase of a data signal most delayed among data signals data1_00 to data1_63. The delay value of the delay circuit 42 is determined by calculating a skew between system clocks sck0 and sck1 and a skew between a data signal earliest transmitted (a data signal whose phase is most advanced) and the data signal transmitted latest (the data signal whose phase is most delayed) among the data signals data1_00 to data1_63. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data receiving circuit suitable for being mounted on a common clock synchronous circuit module.

  FIG. 28 is a circuit diagram showing a connection example of a common clock synchronous circuit module that transmits and receives data. In FIG. 28, 1_0 and 1_1 are common clock synchronous circuit modules (LSIs) for transmitting and receiving data, 2 is a bus, and ck is a common clock supplied to the circuit modules 1_0 and 1_1.

  In this example, when the circuit module 1_0 requests data from the circuit module 1_1, the circuit module 1_0 transmits a request signal req0 to the circuit module 1_1. When the circuit module 1_1 receives the request signal req0, it is necessary for the circuit module 1_0 to recognize the data signals data1_00 to data1_63 (however, the data signals data1_01 to data1_62 are not shown) and the data signals data1_00 to data1_63. An acknowledge signal (data recognition signal) ack1 is transmitted.

  When the circuit module 1_1 requests data from the circuit module 1_0, the circuit module 1_1 transmits a request signal req1 to the circuit module 1_0. When the circuit module 1_0 receives the request signal req1, it is necessary for the circuit module 1_1 to recognize the data signals data0_00 to data0_63 (however, the data signals data0_01 to data0_62 are not shown) and the data signals data0_00 to data0_63. Acknowledge signal ack0 is transmitted.

  In the circuit module 1_0, 3 is an output terminal for the request signal req0, 4 is an output terminal for the acknowledge signal ack0, 5_00 is an output terminal for the data signal data0_00, and 5_63 is an output terminal for the data signal data0_63. The output terminals 5_01 to 5_62 for the data signals data0_01 to data0_62 are not shown.

  6 is an input terminal for the common clock ck, 7 is an input terminal for the request signal req1, 8 is an input terminal for the acknowledge signal ack1, 9_00 is an input terminal for the data signal data1_00, and 9_63 is an input terminal for the data signal data1_63. The input terminals 9_01 to 9_62 for the data signals data1_01 to data1_62, which are input terminals, are not shown.

  In the circuit module 1_1, 10 is an output terminal for the request signal req1, 11 is an output terminal for the acknowledge signal ack1, 12_00 is an output terminal for the data signal data1_00, and 12_63 is an output terminal for the data signal data1_63. The output terminals 12_01 to 12_62 for the data signals data1_01 to data1_62 are not shown.

  Further, 13 is an input terminal for the common clock ck, 14 is an input terminal for the request signal req0, 15 is an input terminal for the acknowledge signal ack0, 16_00 is an input terminal for the data signal data0_00, and 16_63 is for the data signal data0_63. The input terminals 16_01 to 16_62 for the data signals data0_01 to data0_62 are not shown in the figure.

  FIG. 29 is a circuit diagram showing a conventional configuration example of a part of the internal circuit of the circuit modules 1_0 and 1_1. In the circuit module 1_0, 18 is a system clock generation circuit including a PLL circuit that receives the common clock ck via the input terminal 6 and generates the system clock sck0 inside the circuit module 1_0, and 19 is a phase comparator and a charge pump. A PLL block 20 in which a low-pass filter and a voltage controlled oscillator are connected in series is a feedback delay circuit.

  Further, 21 is a data transmission circuit, 22 is a D flip-flop that outputs a request signal req0, 23 is a D flip-flop that outputs an acknowledge signal ack0, and 24_00 is a D flip-flop that outputs a data signal data0_00. The D flip-flops 24_01 to 24_63 that output the data signals data0_01 to data0_63 are not shown.

  25 is a data receiving circuit, 26 is a D flip-flop that latches the request signal req1, 27 is a D flip-flop that latches the acknowledge signal ack1, and 28_00 is a D flip-flop that latches the data signal data1_00. The D flip-flops 28_01 to 28_63 that latch the data signals data1_01 to data1_63 are not shown.

  In the circuit module 1_1, 29 is a system clock generation circuit including a PLL circuit that receives the common clock ck via the input terminal 13 and generates the system clock sck1 inside the circuit module 1_1, and 30 is a phase comparator and A PLL block 31 in which a charge pump, a low-pass filter, and a voltage-controlled oscillator are connected in cascade is a feedback delay circuit.

  Further, 32 is a data transmission circuit, 33 is a D flip-flop that outputs a request signal req1, 34 is a D flip-flop that outputs an acknowledge signal ack1, and 35_00 is a D flip-flop that outputs a data signal data1_00. The D flip-flops 35_01 to 35_63 that output the data signals data1_01 to data1_63 are not shown.

  Further, 36 is a data receiving circuit, 37 is a D flip-flop that latches the request signal req0, 38 is a D flip-flop that latches the acknowledge signal ack0, and 39_00 is a D flip-flop that latches the data signal data0_00. The D flip-flops 39_01 to 39_63 that latch the data signals data0_01 to data0_63 are not shown.

  In this example, in order to adjust the phase of the system clocks sck0 and sck1 with respect to the common clock ck, the PLL blocks 19 and 30 and the feedback delay circuits 20 and 31 are mounted as clock phase adjusting means, and the data is obtained by adjusting the feedback delay. Transmission / reception timing adjustment is performed to synchronize received data.

  FIG. 30 is a waveform diagram showing an example of data transmission / reception operation between the circuit modules 1_0 and 1_1. When the circuit module 1_0 is the data reception side and the circuit module 1_1 is the data transmission side, the data reception circuit 25 of the circuit module 1_0. Shows an example of successful synchronization of the received data signal.

  30, (A) is a common clock ck applied to the circuit modules 1_0 and 1_1, (B) is a system clock sck0 generated by the system clock generation circuit 18 of the circuit module 1_0, and (C) is a system of the circuit module 1_1. The system clock sck1 generated by the clock generation circuit 29 is shown.

  (D) is a request signal req0 output from the D flip-flop 22 of the data transmission circuit 21 of the circuit module 1_0, and (E) is an acknowledge signal ack1 output from the D flip-flop 34 of the data transmission circuit 32 of the circuit module 1_1. , (F) show data signals data1_00 to data1_63 output from the D flip-flops 35_00 to 35_63 of the circuit module 1_1.

  In this example, data transmission is performed by burst transfer with a burst length = 4, and b0, b1, b2, and b3 each indicate 64-bit width data including data signals data1_00 to data1_63 having a parallel 64-bit configuration. ing.

(G) is a system clock sck0 generated by the system clock generation circuit 18 of the circuit module 1_0, and (H) is an acknowledge signal ack1, (I) output from the D flip-flop 27 of the data reception circuit 25 of the circuit module 1_0. ) Shows data1_00 to data1_63 output from the D flip-flops 28_00 to 28_63 of the data receiving circuit 25 of the circuit module 1_0.
JP 2005-316879 A

  In recent years, there has been a demand for further speeding up of data transmission / reception between common clock synchronous circuit modules. However, there is a problem that the data receiving circuits 25 and 36 shown in FIG. 29 cannot cope with further increase in the speed of data transmission / reception between the circuit modules 1_0 and 1_1. As a main cause, there is a skew generated due to manufacturing variations of the circuit modules 1_0 and 1_1 between the system clocks sck0 and sck1 and between data signals transmitted and received.

  FIG. 31 is a waveform diagram for explaining a problem that the data receiving circuit 25 has for further increasing the speed of data transmission / reception. The circuit module 1_0 is the data receiving side, and the circuit module 1_1 is the data transmitting side. In this case, the data receiving circuit 25 fails to synchronize the received data signal.

  31, (A) is a common clock ck supplied to the circuit modules 1_0 and 1_1, (B) is a system clock sck0 generated by the system clock generation circuit 18 of the circuit module 1_0, and (C) is a system of the circuit module 1_1. The system clock sck1 generated by the clock generation circuit 29 is shown.

  (D) is a request signal req0 output from the D flip-flop 22 of the data transmission circuit 21 of the circuit module 1_0, and (E) is an acknowledge signal ack1 output from the D flip-flop 34 of the data transmission circuit 32 of the circuit module 1_1. (F) is a data signal data1_00 to data1_31 output from the D flip-flops 35_00 to 35_31 of the data transmission circuit 32 of the circuit module 1_1, and (G) is output from the D flip-flops 35_32 to 35_63 of the data transmission circuit 32 of the circuit module 1_1. Data signals data1_32 to data1_63 are shown.

  (H) is a system clock sck0 generated by the system clock generation circuit 18 of the circuit module 1_0, and (I) is an acknowledge signal ack1 (J) output from the D flip-flop 27 of the data receiving circuit 25 of the circuit module 1_0. ) Are data1_00 to data1_31 output from the D flip-flops 28_00 to 28_31 of the data receiving circuit 25 of the circuit module 1_0, and (K) is a data signal data1_32 to output from the D flip-flops 28_32 to 28_63 of the data receiving circuit 25 of the circuit module 1_0. data1_63 is shown.

  However, b0a, b1a, b2a, and b3a respectively indicate the portions of the data signals data1_00 to data1_31 of the 64-bit width data b0, b1, b2, and b3 formed of the parallel 64-bit data signals data1_00 to data1_63. Yes. Further, b0b, b1b, b2b, b3b respectively indicate portions of the data signals data1_32 to data1_63 out of the 64-bit width data b0, b1, b2, b3 composed of the parallel 64-bit data signals data1_00 to data1_63. Yes.

  In the example of FIG. 31, the skew between the system clocks sck0 and sck1 and the skew between the data signals data1_00 to data1_31 and data1_32 to data1_63 can no longer be ignored due to further increase in data transmission / reception, and the circuit module 1_0 has received it. The data signals data1_00 to data1_31 (b0a to b3a) have been synchronized successfully, but the data signals data1_32 to data1_63 (b0b to b3b) have failed to be synchronized. The same thing can happen with the data receiving circuit 36.

  In other words, when the conventional data receiving circuits 25 and 36 are used, when the data transmission / reception is performed at the conventional speed, the influence of the skew generated between the system clocks sck0 and sck1 and between the data signals can be ignored. Although it can be performed without any problem, if the data transmission / reception is performed at a speed higher than the conventional speed, the influence of the skew generated between the system clocks sck0 and sck1 and between the data signals cannot be ignored. There was a problem that the data could not be synchronized. Actually, when the conventional data transmission / reception circuits 25 and 36 are used, the synchronization of received data is limited to a transmission / reception transfer rate per bit of data of 100 to 120 Mbps.

  In view of the above, an object of the present invention is to provide a data receiving circuit capable of further increasing the speed of data transmission / reception between common clock synchronous circuit modules.

  The present invention is a data receiving circuit that receives a plurality of data signals transmitted in parallel and an acknowledge signal necessary for recognizing the plurality of data signals, and delays the acknowledge signal to thereby receive the plurality of data signals. A delay circuit that outputs a delayed acknowledge signal having the same phase or a delayed phase with respect to the most delayed data signal, and a first clock that captures the delayed acknowledge signal and the plurality of data signals with a first clock. A capture circuit; a second capture circuit that captures the delayed acknowledge signal and the plurality of data signals with a second clock having a phase opposite to that of the first clock; and Of these, the acknowledge signal and the plurality of data signals output from the fetch circuit that previously fetched the delayed acknowledge signal are handled as valid signals.

  According to the present invention, the delayed acknowledge signal output from the delay circuit is the same or delayed in phase with respect to the most delayed data signal among the plurality of data signals. Among the capture circuits, the acknowledge signal and the plurality of data signals output from the capture circuit that previously captures the delayed acknowledge signal are synchronized. Therefore, even when clock skew and skew between multiple data signals can no longer be ignored as data transmission / reception is further accelerated, it is possible to synchronize received data signals. The speed of data transmission / reception between circuit modules can be further increased.

(First embodiment)
FIG. 1 is a circuit diagram showing a state in which the data receiving circuit 40 according to the first embodiment of the present invention is mounted on the circuit module 1_0. The data receiving circuit 40 of the first embodiment of the present invention is used in place of the conventional data receiving circuits 25 and 36 shown in FIG. 29, and is also mounted on the circuit module 1_1.

  The request signal req0, the acknowledge signal ack0, the data signal data0_00 to data0_63 transmitted by the circuit module 1_0, and the request signal req1 and the data signals data1_01 to data1_62 transmitted by the circuit module 1_1 are not shown.

  In the data receiving circuit 40 according to the first embodiment of the present invention, reference numeral 41 denotes an inverter that inverts the system clock sck0 and outputs an inverted system clock sck0x. A system clock generating circuit that generates the system clock sck0 is shown in FIG. The configuration is the same as that of the system clock generation circuit 18, and the illustration is omitted. Further, the part that receives the request signal req1 transmitted by the circuit module 1_1 is also configured in the same manner as in the prior art, and is not shown.

  42 delays the acknowledge signal ack1 from the circuit module 1_1 input through the input terminal 8, and with respect to the most delayed data signal in the data signals data1_00 through data1_63 input through the input terminals 9_00 to 9_63. The delay circuit outputs an acknowledge signal ack1d having the same phase or a delayed phase, and the delay value is fixed.

  The delay value of the delay circuit 42 includes the skew between the system clocks sck0 and sck1, and the data signal transmitted first (data signal with the most advanced phase) and the data transmitted latest among the data signals data1_00 to data1_63. In order to calculate the skew between the signals (the data signal with the most delayed phase), so that the phase of the acknowledge signal ack1d is the same or delayed with respect to the most delayed data signal in the data signals data1_00 to data1_63. This is the minimum value required.

  43 is a D flip-flop that latches the acknowledge signal ack1d output from the delay circuit 42 in synchronization with the rising edge of the system clock sck0, and ack1dz is an acknowledge signal output from the D flip-flop 43. 44 is a D flip-flop that latches the acknowledge signal ack1d output from the delay circuit 42 in synchronization with the rising edge of the inverted system clock sck0x, and ack1dx is an acknowledge signal output from the D flip-flop 44.

  45_00z is a D flip-flop that latches the data signal data1_00 from the circuit module 1_1 input via the input terminal 9_00 in synchronization with the rising edge of the system clock sck0, and data1_00z is a data signal output by the D flip-flop 45_00z. 45_00x is a D flip-flop that latches the data signal data1_00 from the circuit module 1_1 input via the input terminal 9_00 in synchronization with the rising edge of the inverted system clock sck0x, and data1_00x is a data signal output by the D flip-flop 45_00x.

  45_63z is a D flip-flop that latches the data signal data1_63 from the circuit module 1_1 input via the input terminal 9_63 in synchronization with the rising edge of the system clock sck0, and data1_63z is a data signal output from the D flip-flop 45_63z. 45_63x is a D flip-flop that latches the data signal data1_63 from the circuit module 1_1 input via the input terminal 9_63 in synchronization with the rising edge of the inverted system clock sck0x, and data1_63x is a data signal output from the D flip-flop 45_63x.

  The data signals data1_01z to data1_62z output by the D flip-flops 45_01z to 45_62z and the D flip-flops 45_01z to 45_62z that latch the data signals data1_01 to data1_62 from the circuit module 1_1 in synchronization with the rising edge of the system clock sck0 are shown in the figure. Omitted. Similarly, the data signals data1_01x to data1_62x output by the D flip-flops 45_01x to 45_62x and the D flip-flops 45_01x to 45_62x that latch the data signals data1_01 to data1_62 in synchronization with the rising edge of the inverted system clock sck0x are not shown.

  46 receives the acknowledge signal ack1dz output from the D flip-flop 43 and the acknowledge signal ack1dx output from the D flip-flop 44, and which of the acknowledge signals ack1dz and ack1dx has the rising transition earlier? That is, it is a detection circuit that detects which one of the D flip-flops 43 and 44 latches the acknowledge signal ack1d output from the delay circuit 42 first and outputs a detection signal sy.

  The detection circuit 46 inputs the acknowledge signal ack1dz to the z terminal, inputs the acknowledge signal ack1dx to the x terminal, and outputs the detection signal sy to the y terminal. The detection signal sy is set to a high potential (hereinafter referred to as “H”) in the initial state, and then maintains “H” when the D flip-flop 44 first latches the acknowledge signal ack1d. When the flip-flop 43 first latches the acknowledge signal ack1dz, it is set to a low potential (hereinafter referred to as “L”) for a predetermined period described later.

  A selector 47 selects the acknowledge signal ack1dz or ack1dx. When the detection signal sy is given as a selection control signal and the level of the detection signal sy = “L”, the acknowledge signal ack1dz is selected and the detection signal When the level of sy = “H”, the acknowledge signal ack1dx is selected. ac1 is an acknowledge signal output from the selector 47.

  48_00 is a selector that selects the data signal data1_00z or data1_00x. When the detection signal sy is given as a selection control signal and the level of the detection signal sy = “L”, the data signal data1_00z is selected and the detection signal sy When the level = “H”, the data signal data1_00x is selected. da1_00 is a data signal output from the selector 48_00.

  48_63 is a selector for selecting the data signal data1_63z or data1_63x. When the detection signal sy is given as a selection control signal and the level of the detection signal sy = “L”, the data signal data1_63z is selected, and the detection signal sy When the level = “H”, the data signal data1_63x is selected. da1_63 is a data signal output from the selector 48_63.

  In addition, selectors 48_01 to 48_62 similar to the selectors 48_00 and 48_63 are provided corresponding to the data signals data1_01z, data1_01x to data1_62z, and data1_62x (not shown), but the selectors 48_01 to 48_62 are not shown.

  Reference numeral 49 denotes a D flip-flop that latches the acknowledge signal ac1 output from the selector 47 in synchronization with the rising edge of the system clock sck0, and the acknowledge signal a1 output from the D flip-flop 49 is the acknowledge signal from the circuit module 1_1. The received signal is transferred to the internal circuit as an ack1 received signal.

  50_00 is a D flip-flop that latches the data signal da1_00 output from the selector 48_00 in synchronization with the rising edge of the system clock sck0, and the data signal d1_00 output from the D flip-flop 50_00 receives the data signal data1_00 from the circuit module 1_1. The signal is transferred to the internal circuit.

  50_63 is a D flip-flop that latches the data signal da1_63 output from the selector 48_63 in synchronization with the rising edge of the system clock sck0, and the data signal d1_63 output from the D flip-flop 50_63 receives the data signal data1_63 from the circuit module 1_1. The signal is transferred to the internal circuit.

  The data signals d1_01 to d1_62 output from the D flip-flops 50_01 to 50_62 and the D flip-flops 50_01 to 50_62 that latch the data signals da1_01 to da1_62 output from the selectors 48_01 to 48_62 (not shown) in synchronization with the rising edge of the system clock sck0. The illustration is omitted.

  FIG. 2 is a circuit diagram showing a configuration of the detection circuit 46. In FIG. 2, 52 is an input buffer for inputting the acknowledge signal ack1dx output from the D flip-flop 44, and 53 is an input buffer for inputting the acknowledge signal ack1dz output from the D flip-flop 43.

  54 is a transmission gate provided corresponding to the output s1 of the input buffer 52, 55 is a P-channel MOS transistor, and 56 is an N-channel MOS transistor. 57 is a transmission gate control circuit for controlling on / off of the transmission gate 54, 58 is an AND circuit, and 59 to 61 are NOR circuits.

  The AND circuit 58 has one input terminal connected to the output terminal of the input buffer 52 and the other input terminal connected to the output terminal of the input buffer 53. The NOR circuit 59 also has one input terminal connected to the output terminal of the input buffer 52 and the other input terminal connected to the output terminal of the input buffer 53.

  The NOR circuit 60 has one input terminal connected to the output terminal of the AND circuit 58, the other input terminal connected to the output terminal of the NOR circuit 61, and the output terminal connected to the gate of the N-channel MOS transistor 56. . The NOR circuit 61 has one input terminal connected to the output terminal of the NOR circuit 59, the other input terminal connected to the output terminal of the NOR circuit 60, and the output terminal connected to the gate of the P-channel MOS transistor 55. .

  62 is a latch unit for latching the output of the transmission gate 54, and 63 and 64 are inverters. The inverters 63 and 64 are ring-connected, and the connection point between the input terminal of the inverter 63 and the output terminal of the inverter 64 is connected to the node 65.

  66 is a transition detection unit, and 67 and 68 are NAND circuits. The NAND circuit 67 has one input terminal connected to the output terminal of the input buffer 53 and the other input terminal connected to the output terminal of the NAND circuit 68. The NAND circuit 68 has one input terminal connected to the node 65 and the other input terminal connected to the output terminal of the NAND circuit 67. Reference numeral 69 denotes an output buffer, which has an input terminal connected to the output terminal of the NAND circuit 67 and outputs a detection signal sy to the output terminal.

  3 and 4 are waveform diagrams showing an operation example of the detection circuit 46. (A) is an acknowledge signal ack1dx (output s1 of the input buffer 52), and (B) is an acknowledge signal ack1dz (output of the input buffer 53). (S2) and (C) are outputs s4 of the AND circuit 58, (D) is an output s5 of the NOR circuit 59, (E) is an output s6 of the NOR circuit 61, (F) is an output s7 of the NOR circuit 60, (G). Indicates the level v8 of the node 65, (H) indicates the output s9 of the AND circuit 68, and (I) indicates the detection signal sy (output s3 of the NAND circuit 67).

  FIG. 3 shows a first operation example of the detection circuit 46. When the D flip-flop 44 first latches the acknowledge signal ack1d output from the delay circuit 42, that is, the rising transition of the acknowledge signal ack1dx is acknowledged. A case where the signal is earlier than the rising transition of the signal ack1dz is shown.

  In this example, the level of the acknowledge signal ack1 is set to “L” in the initial state. As a result, the levels of the acknowledge signals ack1dx and ack1dz = “L”, the level of the output s1 of the input buffer 52 = “L”, the level of the output s2 of the input buffer 53 = “L”, and the level of the output s3 of the NAND circuit 67 = “H” and the level of the detection signal sy = “H”.

  The level of the output s4 of the AND circuit 58 = “L”, the level of the output s5 of the NOR circuit 59 = “L”, the level of the output s6 of the NOR circuit 61 = “L”, and the level of the output s7 of the NOR circuit 60 = It becomes “H”, and the transmission gate 54 is turned on. As a result, the level v8 = “L” of the node 65 and the level s9 of the NAND circuit 68 = “H”.

  From this state, even when the D flip-flop 44 first takes in the acknowledge signal ack1d at time t1 and the acknowledge signal ack1dx rises to “H”, the level of the acknowledge signal ack1dz is maintained at “L”. Therefore, the level of the output s2 of the input buffer 53 = “L”, the level of the output s3 of the NAND circuit 67 = “H”, and the level of the detection signal sy = “H” are maintained.

  In this case, the level of the output s5 of the NOR circuit 59 is “L”, the level of the output s4 of the AND circuit 58 is “L”, the level of the output s7 of the NOR circuit 60 is “H”, and the NOR circuit 61 Since the level s6 of the output s6 is maintained at the "L" state, the transmission gate 54 is maintained in the ON state. As a result, the level v8 = “H” of the node 65 and the level s9 of the NAND circuit 68 = “L”.

  Thereafter, when the acknowledge signal ack1dz rises to “H” at time t2, the level of the output s2 of the input buffer 53 = “H”, the level of the output s4 of the AND circuit 58 = “H”, and the output s7 of the NOR circuit 60 Level = “L”, the level of the output s6 of the NOR circuit 61 = “H”, and the transmission gate 54 is turned off. In this case, the level v8 of the node 65 = “H”, the level of the output s9 of the NAND circuit 68 = “L”, the level of the output s3 of the NAND circuit 67 = “H”, and the level of the detection signal sy = “H”. Is maintained.

  Thereafter, when the acknowledge signal ack1dx falls to “L” at time t3, the level of the output s1 of the input buffer 52 becomes “L” and the level of the output s4 of the AND circuit 58 becomes “L”, but the NOR circuit 59, the level of output s5 = “L”, the level of output s7 of NOR circuit 60 = “L”, the level of output s6 of NOR circuit 61 = “H”, and the transmission gate 54 remains off. To do. As a result, the level v8 of the node 65 = “H”, the level of the output s9 of the NAND circuit 68 = “L”, the level of the output s3 of the NAND circuit 67 = “H”, and the level of the detection signal sy = “H”. Is maintained.

  Thereafter, when the acknowledge signal ack1dz falls to “L” at time t4, the level of the output s2 of the input buffer 53 = L ”, the level of the output s5 of the NOR circuit 59 =“ H ”, and the output s6 of the NOR circuit 61 Level = “L”, the level of the output s7 of the NOR circuit 60 = “H”, and the transmission gate 54 is turned on, resulting in the level v8 = “L” of the node 65 and the output s9 of the NAND circuit 68. Although the level = “H”, the level of the output s2 of the input buffer 53 = “L”, so that the level of the output s3 of the NAND circuit 67 = “H” and the level of the detection signal sy = “H”. Maintained.

  As described above, when the D flip-flop 44 latches the acknowledge signal ack1d output from the delay circuit 42, that is, when the rising transition of the acknowledge signal ack1dx is earlier than the rising transition of the acknowledge signal ack1dz, The level of the detection signal sy = “H” is maintained.

  FIG. 4 shows a second operation example of the detection circuit 46. When the D flip-flop 43 first latches the acknowledge signal ack1d output from the delay circuit 42, that is, the rising transition of the acknowledge signal ack1dz is acknowledged. This is a case earlier than the rising transition of the signal ack1dx.

  In the initial state, as described above, the level of the acknowledge signal ack1 is set to “L”. As a result, the levels of the acknowledge signals ack1dx and ack1dz = “L” and the level of the output s1 of the input buffer 52 = “L”. The level of the output s2 of the input buffer 53 is “L”, the level of the output s3 of the NAND circuit 67 is “H”, and the level of the detection signal sy is “H”.

  The level of the output s4 of the AND circuit 58 = “L”, the level of the output s5 of the NOR circuit 59 = “H”, the level of the output s6 of the NOR circuit 61 = “L”, and the level of the output s7 of the NOR circuit 60 = It becomes “H”, and the transmission gate 54 is turned on. As a result, the level v8 = “L” of the node 65 and the level s9 of the NAND circuit 68 = “H”.

  From this state, at time t1, when the D flip-flop 43 takes in the acknowledge signal ack1d first and the acknowledge signal ack1dz rises to “H”, the level of the output s2 of the input buffer 52 = “H”, and the NOR circuit 59 The level of the output s5 is “L”, but the level of the output s4 of the AND circuit 58 is “L”, the level of the output s7 of the NOR circuit 60 is “H”, and the level of the output s6 of the NOR circuit 61 is “L”. Since the state of "" is maintained, the transmission gate 54 remains on.

  As a result, the level v8 of the node 65 = “L” and the level of the output s9 of the NAND circuit 68 = “H” are maintained, but the level of the output s2 of the input buffer 53 = “H”. The level of the output s9 is “L” and the level of the detection signal sy is “L”.

  Thereafter, when the acknowledge signal ack1dx rises to “H” at time t2, the level of the output s1 of the input buffer 52 = “H”, the level of the output s4 of the AND circuit 58 = “H”, and the output s7 of the NOR circuit 60 Level = “L”, the level of the output s6 of the NOR circuit 61 = “H”, and the transmission gate 54 is turned off.

  In this case, the level v8 of the node 65 becomes indefinite because the transition of the output s1 of the input buffer 52 to “H” and the timing at which the transmission gate 54 is turned off are simultaneous. However, the level of the output s9 of the NAND circuit 68 = “H”, the level of the output s3 of the NAND circuit 67 = “L”, and the level of the detection signal sy = “L” are maintained.

  Thereafter, when the acknowledge signal ack1dz falls to “L” at time t3, the level of the output s2 of the input buffer 53 = “L”, the level of the output s3 of the NAND circuit 67 = “H”, and the level of the detection signal sy = "H". In this case, the level of the output s4 of the AND circuit 58 = “L”, but the level of the output s5 of the NOR circuit 59 = “L”, the level of the output s6 of the NOR circuit 61 = “H”, and the output of the NOR circuit 60 The level of s7 = “L” is maintained, and the transmission gate 54 maintains the off state. In this case, since the level v8 of the node 65 is indefinite and the level of the output s3 of the NAND circuit 67 is “H”, the level of the output s9 of the NAND circuit 68 is indefinite.

  Thereafter, when the acknowledge signal ack1dx falls to “L” at time t4, the level of the output s5 of the NOR circuit 59 = “H”, the level of the output s6 of the NOR circuit 61 = “L”, and the output of the NOR circuit 60 The level of s7 becomes “H”, and the transmission gate 54 is turned on. As a result, the level v8 of the node 65 = “L” and the level of the output s9 of the NAND circuit 68 = “H”, but the level of the output s2 of the input buffer 53 = “L” is maintained. The state where the level of the output s3 of the circuit 67 is “H” and the level of the detection signal sy is “H” is maintained.

  Thus, when the acknowledge signal ack1d output from the delay circuit 42 is latched by the D flip-flop 43 first, that is, when the rising transition of the acknowledge signal ack1dz is earlier than the rising transition of the acknowledge signal ack1dx, The detection signal sy becomes “L” in synchronization with the rising transition of the acknowledge signal ack1dz, and becomes “H” in synchronization with the falling transition of the acknowledge signal ack1dz.

  5 to 8 are waveform diagrams showing an operation example of the data receiving circuit 40 according to the first embodiment of the present invention. (A) is a system clock sck0 in the circuit module 1_0, and (B) is a circuit in the circuit module 1_0. An inversion system clock sck0x is shown.

  (C) is an acknowledge signal ack1 that has reached the circuit module 1_0, (D) is an acknowledge signal ack1d that is output from the delay circuit 42, (E) is an acknowledge signal ack1dx that is output from the D flip-flop 44, (F ) Is an acknowledge signal ack1dz output from the D flip-flop 43, (G) is a detection signal sy output from the detection circuit 46, (H) is an acknowledge signal ac1 output from the selector 47, and (I) is a D flip-flop 49. Indicates an acknowledge signal a1 output by

  (J) is the data signal data1_00 to data1_63 that has reached the circuit module 1_0, (K) is the data signal data1_00z to data1_63z output from the D flip-flops 45_00z to 45_63z, and (L) is the output from the D flip-flops 45_00x to 45_63x. Data signals data1_00x to data1_63x, (M) indicates data signals da1_00 to da1_63 output from the selectors 48_00 to 48_63, and (N) indicates data signals d1_00 to d1_63 output from the D flip-flops 50_00 to 50_63.

  In this example, data transmission is performed by burst transfer with a burst length = 2, and b0 and b1 indicate 64-bit data composed of data signals data1_00 to data1_63 each having a parallel 64-bit configuration. The H level width of the acknowledge signal ack1 is the length of two cycles of the system clock sck0, and the H level width and the L level width of the data signals data1_00 to data1_63 are the length of one cycle of the system clock sck0. ing.

  Here, in the initial state, as described above, the level of the acknowledge signal ack1 is set to “L”. Therefore, the level of the acknowledge signal ack1d is set to “L”, the level of the acknowledge signal ack1dz is set to “L”, The level of the knowledge signal ack1dx = “L”, the level of the detection signal sy = “L”, the level of the acknowledge signal ac1 = “L”, and the level of the acknowledge signal a1 = “L”.

  The acknowledge signal ack1d has the same or delayed phase as the most delayed data signal in the data signals data1_00 to data1_63 input via the input terminals 9_00 to 9_63, so that the data signals data1_00 to data1_63. Is transmitted earlier than the acknowledge signal ack1, and which of the D flip-flops 43 and 44 latches the acknowledge signal ack1d first, the data receiving circuit 40 according to the first embodiment of the present invention. Of receiving the acknowledge signal ack1 and the data signals data1_00 to data1_63 can be classified into four operation examples shown in FIGS.

  FIG. 5 shows a first operation example of the data receiving circuit 40 according to the first embodiment of the present invention. The circuit module 1_1 transmits the data signal data1_00 to data1_63 earlier than the acknowledge signal ack1, and the acknowledge signal ack1d is transmitted. This shows a case where the data signals data1_00 to data1_63 are latched by the D flip-flops 45_00z to 45_63z first 0.5 cycles before the D flip-flop 44 latches first.

  Specifically, the data signals data1_00 to data1_63 reach the circuit module 1_0 between times t5 and t6, and are first latched by the D flip-flops 45_00z to 45_63z at time t6, and the acknowledge signal ack1 is The circuit module 1_0 is reached between times t6 and t7, and the state where the circuit module 1_0 is already latched by the D flip-flop 44 at time t7 is shown.

  FIG. 6 shows a second operation example of the data receiving circuit 40 according to the first embodiment of the present invention. The circuit module 1_1 transmits the data signal data1_00 to data1_63 at the same speed as the acknowledge signal ack1, The signal ack1d is latched first by the D flip-flop 44, and the data signals data1_00 to data1_63 are latched first by the D flip-flops 45_00x to 45_63x.

  Specifically, the acknowledge signal ack1 and the data signal data1_00 to data1_63 both reach the circuit module 1_0 between times t6 and t7, and the acknowledge signal ack1d is first latched by the D flip-flop 44 at time t7. In addition, the data signals data1_00 to data1_63 indicate a state where the data signals are already latched by the D flip-flops 45_00x to 45_63x at time t7.

  Here, even if the acknowledge signal ack1d and the data signals data1_00 to data1_63 have the relationship shown in FIG. 5 or the relationship shown in FIG. 6, the acknowledge signal a1 and the reception signal are received at the same timing. If the data signals d1_00 to d1_63 can be transferred to the internal circuit, 0.5 cycles in which the D flip-flop 44 first latches the acknowledge signal ack1d in the data signals data1_00 to data1_63 by further increasing the speed of data transmission / reception. Even when the data signal previously latched by the D flip-flops 45_00z to 45_63z is included, the acknowledge signal a1 and the received data signals d1_00 to d1_63 can be synchronized.

  FIG. 7 shows a third operation example of the data receiving circuit 40 according to the first embodiment of the present invention. The circuit module 1_1 transmits the data signal data1_00 to data1_63 earlier than the acknowledge signal ack1, and the acknowledge signal ack1d is transmitted. This shows a case where the data signals data1_00 to data1_63 are latched first by the D flip-flops 45_00x to 45_63x 0.5 cycles before the D flip-flop 43 latches first.

  Specifically, the data signals data1_00 to data1_63 reach the circuit module 1_0 during the time t6 to t7, and are latched first by the D flip-flops 45_00x to 45_63x at the time t7, and the acknowledge signal ack1 is The circuit module 1_0 is reached between time t7 and time t8, and is in a state of being latched first by the D flip-flop 43 at time t8.

  FIG. 8 shows a fourth operation example of the data receiving circuit 40 according to the first embodiment of the present invention, in which the circuit module 1_1 transmits the data signal data1_00 to data1_63 at the same speed as the acknowledge signal ack1, The signal ack1d is latched first by the D flip-flop 43, and the data signals data1_00 to data1_63 are latched first by the D flip-flops 45_00z to 45_63z.

  Specifically, the acknowledge signal ack1 and the data signal data1_00 to data1_63 both reach the circuit module 1_0 between times t7 and t8, and the acknowledge signal ack1d is first latched by the D flip-flop 43 at time t8. In addition, the data signals data1_00 to data1_63 indicate a state where the data signals are already latched by the D flip-flops 45_00z to 45_63z at time t8.

  Here, even if the acknowledge signal ack1d and the data signals data1_00 to data1_63 have the relationship shown in FIG. 7 or the relationship shown in FIG. 8, the acknowledge signal a1 and the reception signal are received at the same timing. If the data signals d1_00 to d1_63 can be transferred to the internal circuit, 0.5 cycles in which the D flip-flop 43 first latches the acknowledge signal ack1d in the data signals data1_00 to data1_63 by further increasing the speed of data transmission / reception. Even when the data signal previously latched by the D flip-flops 45_00x to 45_63x is included, the acknowledge signal a1 and the received data signals d1_00 to d1_63 can be synchronized.

  That is, even if the acknowledge signal ack1d and the data signals data1_00 to data1_63 have the relationship shown in FIG. 5 or the relationship shown in FIG. 6, the acknowledge signal a1 and the received data have the same timing. If the signals d1_00 to d1_63 can be transferred to the internal circuit, the acknowledge signal ack1d and the data signals data1_00 to data1_63 may be in the relationship shown in FIG. 7 or in the relationship shown in FIG. Even if the acknowledge signal a1 and the received data signals d1_00 to d1_63 can be transferred to the internal circuit at the same timing, the earliest transmitted data in the data signals data1_00 to data1_63 is achieved by further increasing the speed of data transmission / reception. Signal and latest transmitted data Even if the skew can not be ignored between the signals is generated, so that it is possible to synchronize the acknowledge signal a1 and the received data signal D1_00～d1_63.

  First, the first operation example shown in FIG. 5 will be described. In the first operation example shown in FIG. 5, the acknowledge signal ack1 reaches the circuit module 1_0 between time t6 and t7 and is delayed by the delay circuit 42, but the acknowledge signal ack1d is received at time t6 to t7. Transition to “H” in between. As a result, the D flip-flop 44 latches the acknowledge signal ack1d at time t7, and the D flip-flop 43 latches the acknowledge signal ack1d at time t8.

  In this case, as shown in the example of FIG. 3, since the detection signal sy maintains “H”, the selector 47 selects the acknowledge signal ack1dx output from the D flip-flop 44, and the D flip-flop 49 The acknowledge signal ack1dx (ac1) output from the selector 47 is latched at time t8, and the acknowledge signal ack1dx (a1) is output as a reception signal of the acknowledge signal ack1.

  On the other hand, the data signals data1_00 to data1_63 have reached the circuit module 1_0 between times t5 and t6. As a result, the D flip-flops 45_00z to 45_63z latch the data signals data1_00 to data1_63 at time t6, and the D flip-flops 45_00x to 45_63x latch the data signals data1_00 to data1_63 at time t7.

  Since the detection signal sy is “H”, the selectors 48_00 to 48_63 select the data signals data1_00x to data1_63x output from the D flip-flops 45_00x to 45_63x, and the D flip-flops 50_00 to 50_63 select the selectors 48_00 to 48_00. Data signals data1_00x to data1_63x (data1_00 to data1_63) output by 48_63 are latched at time t8, and the data signals data1_00x to data1_63x (d1_00 to d1_63) are transferred to the internal circuit as reception signals of the data signals data1_00 to data1_63.

  As described above, the data signals data1_00 to data1_63 reach the circuit module 1_0 during the time t5 to t6, and are first latched by the D flip-flops 45_00z to 45_63z at the time t6, and the acknowledge signal ack1 is When the circuit module 1_0 is reached between t6 and t7 and is first latched by the D flip-flop 44 at time t7, the acknowledge signal ack1dx (a1) and the data signal data1_00x are set with the time t8 as the transfer start time. ~ Data1_63x (d1_00 to d1_63) can be transferred to the internal circuit in a cycle-synchronized manner.

  Next, a second operation example shown in FIG. 6 will be described. In the second operation example shown in FIG. 6, the acknowledge signal ack1 reaches the circuit module 1_0 between time t6 and t7 and is delayed by the delay circuit 42, but the acknowledge signal ack1d is received at time t6 to t7. Transition to “H” in between. As a result, as in the case of FIG. 5, the D flip-flop 44 latches the acknowledge signal ack1d at time t7, and the D flip-flop 43 captures the acknowledge signal ack1d at time t8.

  Therefore, since the detection signal sy output from the detection circuit 46 is maintained at “H”, the selector 47 selects the acknowledge signal ack1dx output from the D flip-flop 44, and the D flip-flop 49 is output from the selector 47. The acknowledge signal ack1dx (ac1) to be output is latched at time t8, and the acknowledge signal ack1dx (a1) is output as a reception signal of the acknowledge signal ack1.

  On the other hand, the data signals data1_00 to data1_63 have reached the circuit module 1_0 between times t6 and t7. As a result, the D flip-flops 45_00x to 45_63x latch the data signals data1_00 to data1_63 at time t7, and the D flip-flops 45_00z to 45_63z latch the data signals data1_00 to data1_63 at time t8.

  In this case, since the detection signal sy is “H”, the selectors 48_00 to 48_63 select the data signals data1_00x to data1_63x output from the D flip-flops 45_00x to 45_63x, and the D flip-flops 50_00 to 50_63 The data signals data1_00x to data1_63x (data1_00 to data1_63) output by the selectors 48_00 to 48_63 are latched at time t8, and the data signals data1_00x to data1_63x (d1_00 to d1_63) are transferred to the data signal data1_00 to the data1_63 as a reception signal of the internal signal 1_63. become.

  As described above, the acknowledge signal ack1 and the data signal data1_00 to data1_63 reach the circuit module 1_0 during the time t6 to t7, and the acknowledge signal ack1 is first latched by the D flip-flop 44 at time t7, and the data When the signals data1_00 to data1_63 are first latched by the D flip-flops 45_00x to 45_63x at time t7, the acknowledge signal ack1dx (a1) and the data signals data1_00x to data1_63x (d1_00 to d1_00 to d0_0) are set with the transfer start time t8. d1_63) can be cycle-synchronized and transferred to the internal circuit.

  That is, according to the data receiving circuit 40 of the first embodiment of the present invention, even if the acknowledge signal ack1d and the data signals data1_00 to data1_63 have the relationship shown in FIG. 5, they have the relationship shown in FIG. Even in this case, the received data signals data1_00x to data1_63x can be transferred to the internal circuit at the same timing.

  Therefore, by further increasing the speed of data transmission / reception, the D flip-flops 45_00z to 45_63z first latch in the data signals data1_00 to data1_63 0.5 cycles before the D flip-flop 44 latches the acknowledge signal ack1d first. Even when the data signal is included, the acknowledge signal a1 and the received data signal d1_00 to d1_63 can be synchronized.

  Next, a third operation example shown in FIG. 7 will be described. In the third operation example shown in FIG. 7, the acknowledge signal ack1 reaches the circuit module 1_0 between times t7 and t8 and is delayed by the delay circuit 42, but the acknowledge signal ack1 is received at times t7 to t8. Transition to “H” in between. As a result, the D flip-flop 43 latches the acknowledge signal ack1d at time t8, and the D flip-flop 44 latches the acknowledge signal ack1d at time t9.

  In this case, as shown in the example of FIG. 4, the detection signal sy becomes “L” in synchronization with the rising transition of the acknowledge signal ack1dz, and becomes “H” in synchronization with the falling transition of the acknowledge signal ack1dz. Therefore, the selector 47 selects the acknowledge signal ack1dz output from the D flip-flop 43, and the D flip-flop 49 latches the acknowledge signal ack1dz (ac1) output from the selector 47 at time t10, and the acknowledge signal. ack1dz (a1) is output as the received signal of the acknowledge signal ack1.

  On the other hand, the data signals data1_00 to data1_63 have reached the circuit module 1_0 between times t6 and t7. As a result, the D flip-flops 45_00x to 45_63x latch the data signals data1_00 to data1_63 at time t7, and the D flip-flops 45_00z to 45_63z latch the data signals data1_00 to data1_63 at time t8.

  In this case, since the detection signal sy is “L”, the selectors 48_00 to 48_63 select the data signals data1_00z to data1_63z output from the D flip-flops 45_00z to 45_63z, and the D flip-flops 50_00 to 50_63 The data signals data1_00z to data1_63z (data1_00 to data1_63) output from the selectors 48_00 to 48_63 are latched at time t10, and the data signals data1_00z to data1_63z (d1_00 to d1_63) are transferred to the data signal data1_00 to the data1_63 as a reception signal of the internal signal 1_63. become.

  As described above, both the acknowledge signal ack1 and the data signal data1_00 to data1_63 reach the circuit module 1_0 during the time t7 to t8, and the acknowledge signal ack1 is first latched by the D flip-flop 43 at the time t8. When the data signals data1_00 to data1_63 are first latched by the D flip-flops 45_00x to 45_63x at time t7, the acknowledge signal ack1dz (a1) and the data signals data1_00z to data1_63z (d1_00) are set with the time t10 as the transfer start time. ˜d1 — 63) can be transferred to the internal circuit in a cycle-synchronized manner.

  Next, a fourth operation example shown in FIG. 8 will be described. In the fourth operation example shown in FIG. 8, the acknowledge signal ack1 reaches the circuit module 1_0 between times t7 and t8 and is delayed by the delay circuit 42, but the acknowledge signal ack1d is received at the times t7 to t8. Transition to “H” in between. As a result, as in the case shown in FIG. 7, the D flip-flop 43 latches the acknowledge signal ack1d in synchronization with time t8, and the D flip-flop 44 latches the acknowledge signal ack1d at time t9. Become.

  Therefore, since the detection signal sy becomes “L” in synchronization with the rising transition of the acknowledge signal ack1dz and becomes “H” in synchronization with the falling transition of the acknowledge signal ack1dz, the selector 47 receives the acknowledge signal. ack1dz is selected, and the D flip-flop 49 latches the acknowledge signal ack1dz (ac1) output from the selector 47 at time t10, and outputs the acknowledge signal ack1dz (a1) as a reception signal of the acknowledge signal ack1. Become.

  On the other hand, the data signals data1_00 to data1_63 have reached the circuit module 1_0 between times t7 and t8. As a result, the D flip-flops 45_00z to 45_63z latch the data signals data1_00 to data1_63 at time t8, and the D flip-flops 45_00x to 45_63x latch the data signals data1_00 to data1_63 at time t9.

  In this case, since the detection signal sy is “L”, the selectors 48_00 to 48_63 select the data signals data1_00z to data1_63z output from the D flip-flops 45_00z to 45_63z, and the D flip-flops 50_00 to 50_63 The data signals data1_00z to data1_63z (data1_00 to data1_63) output from the selectors 48_00 to 48_63 are latched at time t10, and the data signals data1_00z to data1_63z (d1_00 to d1_63) are transferred to the data signal data1_00 to the data1_63 as a reception signal of the internal signal 1_63. become.

  As described above, both the acknowledge signal ack1 and the data signal data1_00 to data1_63 reach the circuit module 1_0 during the time t7 to t8, and the acknowledge signal ack1 is first latched by the D flip-flop 44 at the time t8. When the data signals data1_00 to data1_63 are first latched by the D flip-flops 45_00z to 45_63z at time t8, the acknowledge signal ack1dz (a1) and the data signals data1_00z to data1_63z (d1_00) are set with the time t10 as the transfer start time. ˜d1 — 63) can be transferred to the internal circuit in a cycle-synchronized manner.

  That is, according to the data receiving circuit 40 of the first embodiment of the present invention, even when the acknowledge signal ack1d and the data signals data1_00 to data1_63 have the relationship shown in FIG. 7, they have the relationship shown in FIG. Even in this case, the received data signals data1_00z to data1_63z can be transferred to the internal circuit at the same timing.

  Therefore, by further increasing the speed of data transmission / reception, the D flip-flops 45_00x to 45_63x first latch in the data signals data1_00 to data1_63 0.5 cycles before the D flip-flop 43 latches the acknowledge signal ack1d first. Even when the data signal is included, the acknowledge signal a1 and the received data signal d1_00 to d1_63 can be synchronized.

  That is, in the data receiving circuit 40 according to the first embodiment of the present invention, the acknowledge signal ack1d is the same or delayed in phase by the delay circuit 42 with respect to the most delayed data signal in the data signals data1_00 to data1_63. Of the first flip-flop 43, 45_00z to 45_63z and the second flip-flop 44, 45_00x to 45_63x, the acknowledge signal ack1d is fetched first. The acknowledge signal and the data signal output from the capture circuit are synchronized.

  Here, when the D flip-flop 43 latches the acknowledge signal ack1d first, the selectors 47 and 48_00 to 48_63 output the acknowledge signal ack1dz output from the D flip-flop 43 and the D flip-flops 45_00z to 45_63z. Since the control is performed to select the data signals data1_00z to data1_63z, the acknowledge signal ac1 and the data signals da1_00 to da1_63 output from the selectors 47 and 48_00 to 48_63 are synchronized. The acknowledge signal a1 and the data signals d1_00 to d1_63 output from 50_00 to 50_63 are synchronized.

  On the other hand, when the D flip-flop 44 latches the acknowledge signal ack1d first, the selectors 47 and 48_00 to 48_63 are configured so that the acknowledge signal ack1dx output from the D flip-flop 44 and the D flip-flops 45_00x to 45_63x are Since the control is performed so as to select the data signals data1_00x to data1_63x to be output, the acknowledge signal ac1 and the data signals da1_00 to da1_63 output by the selectors 47 and 48_00 to 48_63 are synchronized. 49, 50_00 to 50_63, the acknowledge signal a1 and the data signal d1_00 to d1_63 are synchronized.

  In this way, whether the acknowledge signal ack1d and the data signals data1_00 to data1_63 have the relationship shown in FIG. 5 or the relationship shown in FIG. 6, the acknowledge signal ack1dx is the same timing. And the data signals data1_00x to data1_63x can be transferred to the internal circuit, and even if the acknowledge signal ack1d and the data signals data1_00 to data1_63 have the relationship shown in FIG. 7, they have the relationship shown in FIG. Even in this case, the acknowledge signal ack1dz and the data signals data1_00z to data1_63z can be transferred to the internal circuit at the same timing.

  Therefore, according to the data receiving circuit 40 of the first embodiment of the present invention, with an increase in the speed of data transmission / reception between the circuit modules 1_0 and 1_1, the skew between the system clocks sck0 and sck1 and the data signal data1_00 to data1_63. Even when the skew cannot be ignored, it is possible to synchronize the reception acknowledge signal a1 and the reception data signals d1_00 to d1_63, and further increase the speed of data transmission / reception between the circuit modules 1_0 and 1_1. You can plan. For example, the transmission / reception transfer rate per bit of data can be increased to about 200 Mbps, and the speed can be increased by about twice as compared with the case of using the conventional data receiving circuits 25 and 36 shown in FIG. .

  In the data receiving circuit 40 according to the first embodiment of the present invention, D flip-flops 49 and 50_00 to 50_63 are provided. Even if these D flip-flops 49 and 50_00 to 50_63 are not present, FIGS. In this example, the acknowledge signal ack1dx (a1) and the data signals data1_00x to data1_63x (d1_00 to d1_63) can be cycle-synchronized and transferred to the internal circuit using the time t8 as the transfer start time. In the example, since the acknowledge signal ack1dx (a1) and the data signals data1_00x to data1_63x (d1_00 to d1_63) can be cycle-synchronized and transferred to the internal circuit with the time t10 as the transfer start time, the D flip-flops 49, 50_00 ~ 50_63 It may not be provided.

(Second Embodiment)
FIG. 9 is a circuit diagram showing a state in which the data receiving circuit 71 according to the second embodiment of the present invention is mounted on the circuit module 1_0. The data receiving circuit 71 according to the second embodiment of the present invention includes a variable delay circuit 72 instead of the delay circuit 42 shown in FIG. 1 and a delay value control circuit 73 that controls the delay value of the variable delay circuit 72. Others are the same as those of the data receiving circuit 40 according to the first embodiment of the present invention shown in FIG. The data receiving circuit 71 of the second embodiment of the present invention is also mounted on the circuit module 1_1.

  FIG. 10 is a circuit diagram showing a configuration of the variable delay circuit 72. In FIG. 10, 75 is a buffer with a delay value of Ta [sec], 76 is a buffer with a delay value of 2 × Ta [sec], 77 is a buffer with a delay value of 4 × Ta [sec], and 78 is a delay. This is a buffer whose value is 8 × Ta [sec].

  Reference numeral 79 denotes an incremental counter (hexadecimal counter) that counts the incremental pulse INC1 output from the delay value control circuit 73 and outputs count values c3 (most significant bit), c2, c1, and c0 (least significant bit).

  Reference numeral 80 denotes a selector for selecting the acknowledge signal ack1 or the output of the buffer 75. When the count value c0 is given as a selection control signal, and the count value c0 = “0”, the acknowledge signal ack1 is selected and counted. When the value c0 = "1", the output of the buffer 75 is selected.

  Reference numeral 81 denotes a selector for selecting the output of the selector 80 or the output of the buffer 76, and the count value c1 is given as a selection control signal. When the count value c1 = "0", the output of the selector 80 is selected and counted. When the value c1 = "1", the output of the buffer 76 is selected.

  Reference numeral 82 denotes a selector for selecting the output of the selector 81 or the output of the buffer 77, and the count value c2 is given as a selection control signal. When the count value c2 = "0", the output of the selector 81 is selected and counted. When the value c2 = "1", the output of the buffer 77 is selected.

  Reference numeral 83 denotes a selector for selecting the output of the selector 82 or the output of the buffer 78, and the count value c3 is given as a selection control signal. When the count value c3 = "0", the output of the selector 82 is selected and counted. When the value c3 = “1”, the output of the buffer 78 is selected.

  FIG. 11 is a table showing the function of the variable delay circuit 72. The total number of incremental pulses INC1 output from the delay value control circuit 73, the count values c3, c2, c1, c0 of the incremental counter 79, and the variable delay circuit. The relationship with 72 delay values is shown. That is, the variable delay circuit 72 changes the delay value by incrementing the count values c3, c2, c1, and c0 of the incremental counter 79 every time the incremental pulse INC1 output from the delay value control circuit 73 is input. The initial value of the delay value is 0 [sec] and the variable range is 0 to 15 Ta [sec].

  FIG. 12 is a circuit diagram showing a configuration of the delay value control circuit 73. In FIG. 12, reference numeral 85 denotes a data expected value determination unit that determines whether or not the data signals d1_00 to d1_63 output from the D flip-flops 50_00 to 50_63 match an expected value and outputs a determination signal “judge”.

  An AND circuit 86 AND-processes the acknowledge signal a1 output from the D flip-flop 49 and the delay value setting mode signal, and 87 delays the output p1 of the AND circuit 86 until a determination result is output from the data expected value determination unit 85. This is a data expectation value determination wait delay unit.

  88 is a pulse generator, 89 to 91 are inverters constituting an inversion delay circuit that inverts and delays the output p2 of the data expectation value determination wait delay unit 87, and 92 is an output p2 of the data expectation value determination wait delay unit 87 and the inverter This is an AND circuit that AND-processes the output p3 of 91. Reference numeral 93 denotes an AND circuit that AND-processes the output p4 of the AND circuit 92 and the determination signal “judge” output from the data expected value determination unit 85 and outputs an incremental pulse INC1.

  FIG. 13 is a table showing operation truth values of the data expected value determination unit 85. That is, the data expectation value determination unit 85 sets the level of the determination signal “judge” = “L” when the data signals d1_00 to d1_63 are all “H” or “L”, and selects one of the data signals d1_00 to d1_63. If even one bit has a different level from other bits, the level of the judgment signal “judge” is set to “H”.

  14 is a waveform diagram showing a part of the operation of the delay value control circuit 73 in the normal operation mode, FIG. 15 is a waveform diagram showing a part of the operation of the delay value control circuit 73 in the delay value setting mode, and FIG. Acknowledge signals a1 and (B) to be output are data signals d1_00 to d1_63 output from the D flip-flops 50_00 to 50_63, (C) is a determination signal judge output from the data expectation value determination unit 85, and (D) is a delay value setting. (E) is the output p1 of the AND circuit 86, (F) is the output p2 of the data expectation value determination wait delay unit 87, (G) is the output p3 of the inverter 91, and (H) is the output p4 of the AND circuit 92. , (I) shows the output of the AND circuit 93 (incremental pulse INC1).

  As shown in FIG. 14, in the normal operation mode, the level of the delay value setting mode signal is fixed to “L”. As a result, the level of the output p1 of the AND circuit 86 is “L”, the level of the output p2 of the data expectation value determination wait delay unit 87 is “L”, the level of the output p3 of the inverter 91 is “H”, The level of the output p4 is fixed to “L” and the output level of the AND circuit 93 is fixed to “L”, and the incremental pulse INC1 is not generated.

  On the other hand, in the delay value setting mode, all “L” (or “H”) data signals data1_00 to data1_63 are transmitted from the circuit module 1_1 as data signals for delay value setting, and the delay value of the variable delay circuit 72 is adjusted. Thereafter, all “H” (or “L”) data signals data1_00 to data1_63 are transmitted from the circuit module 1_1 as the delay value setting data signals, and the delay value of the variable delay circuit 72 is adjusted. In the figure, an example is shown in which the data signals data1_00 to data1_63 are all transmitted from the circuit module 1_1 and the delay value of the variable delay circuit 72 is adjusted.

  As shown in FIG. 15, in the delay value setting mode, the level of the delay value setting mode signal is fixed to “H”. As a result, for example, when the acknowledge signal a1 rises to “H” at time t11. The output p1 of the AND circuit 86 rises to “H”, and after the delay time of the data expectation value determination wait delay unit 87 has elapsed, the output p2 of the data expectation value determination wait delay unit 87 rises to “H”. After the total delay time of ˜91 has elapsed, the output p3 of the inverter 91 falls to “L”. As a result, a pulse 95 is generated from the AND circuit 92.

  In this case, when the circuit module 1_1 transmits all the “H” data signals data1_00 to data1_63 as the delay value setting data signals data1_00 to data1_63, any of the data signals d1_00 to d1_63 input to the data expected value determination unit 85 If only one bit is “L”, the level of the determination signal “judge” becomes “H”, and the pulse 95 output from the AND circuit 92 is output from the AND circuit 93 as the incremental pulse INC1.

  Thereafter, when the acknowledge signal a1 falls to “L” at time t12, the output p1 of the AND circuit 86 falls to “L”, and the output p2 of the data expectation value determination wait delay unit 87 rises to “L”. The output p3 of the inverter 91 rises to “H”.

  Thereafter, when the acknowledge signal a1 rises to “H” at time t13, the output p1 of the AND circuit 86 rises to “H”, and after the delay time of the data expectation value judgment wait delay unit 87 has elapsed, the data expectation value judgment wait The output p2 of the delay unit 87 rises to “H”, and after the total delay time of the inverters 89 to 91 has elapsed, the output p3 of the inverter 91 falls to “L”. As a result, a pulse 97 is generated from the AND circuit 92.

  In this case, when the circuit module 1_1 transmits all “H” data signals data1_00 to data1_63 as the delay value setting data signals data1_00 to data1_63, all of the data signals d1_00 to d1_63 input to the data expected value determination unit 85 are transmitted. Is “H”, that is, when the synchronization of the data signals d1_00 to d1_63 is successful, the level of the determination signal “judge” becomes “L”, and the pulse 97 output from the AND circuit 92 is output from the AND circuit 93. It is not output as the incremental pulse INC1.

  Thereafter, when the acknowledge signal a1 falls to “L” at time t14, the output p1 of the AND circuit 86 falls to “L”, and the output p2 of the data expected value determination wait delay unit 87 falls to “L”. The output p3 of the inverter 91 rises from “L” to “H”.

  FIG. 16 is a flowchart showing a delay value setting procedure of the variable delay circuit 72. In the delay value setting mode of the variable delay circuit 72, first, the delay value setting mode signal is set to “H” (step N1). Next, the circuit module 1_1 resets all the data signals data1_00 to data1_63 to “L” (step N2), and transmits the acknowledge signal ack1 and the data signals data1_00 to data1_63 in the next cycle (step N3).

  The circuit module 1_0 receives the data signals data1_00 to data1_63, all of which are transmitted from the circuit module 1_1, performs data expectation value determination in the delay value control circuit 73 (step N4), and D flip-flops 50_00 to 50_63 When all of the data signals d1_00 to d1_63 output from are not “L”, an incremental pulse INC1 is generated from the delay value control circuit 73 to increment the delay value of the variable delay circuit 72 (step N5), and the process returns to step N2. .

  When the reception of all “L” data signals data1_00 to data1_63 is successful, that is, when the synchronization of all “L” data signals d1_00 to d1_63 is successful, the circuit module 1_1 transmits all the data signals data1_00 to data1_63 to “ It is reset to H ″ (step N6), and in the next cycle, the acknowledge signal ack1 and the data signals data1_00 to data1_63 are transmitted (step N7).

  The circuit module 1_0 receives all “H” data signals data1_00 to data1_63 transmitted from the circuit module 1_1, performs data expected value determination in the delay value control circuit 73 (step N8), and the D flip-flops 50_00 to 50_63 If all the output data signals d1_00 to d1_63 are not “H”, an incremental pulse is generated from the delay value control circuit 73 to increment the delay value of the variable delay circuit 72 (step N9), and the process returns to step N6. When the reception of all “H” data signals data1_00 to data1_63 is successful, that is, when the synchronization of all “H” data signals d1_00 to d1_63 is successful, the delay value setting of the variable delay circuit 72 is terminated.

  In the data receiving circuit 71 of the second embodiment of the present invention, a variable delay circuit 72 is provided instead of the delay circuit 42 included in the data receiving circuit 40 of the first embodiment of the present invention, and the delay value of the variable delay circuit 72 is set. Since the delay value control circuit 73 to be controlled is provided and the others are configured in the same manner as the data receiving circuit 40 of the first embodiment of the present invention, the data receiving circuit 71 of the second embodiment of the present invention is used. For example, in the same manner as the data receiving circuit of the first embodiment of the present invention, the skew between the system clocks sck0 and sck1 and the skew between the data signals data1_00 to data1_63 as the data transmission / reception between the circuit modules 1_0 and 1_1 increases. Even if the signal cannot be ignored, the received data signal can be synchronized, and the circuit modules 1_0 and 1_1 can be synchronized. It is possible to further speed up over data transmission and reception.

  In the data receiving circuit 71 according to the second embodiment of the present invention, the delay value control circuit 73 causes the phase of the acknowledge signal ack1d output from the variable delay circuit 72 to be the most delayed data in the data signals data1_00 to data1_63. The delay value of the variable delay circuit 72 required to be the same or delayed with respect to the signal can be automatically set.

  Therefore, the skew between the system clocks sck0 and sck1 and the data signal output first (data signal with the most advanced phase) in the data signals data1_00 to data1_63 and the data signal output with the latest (the phase is most delayed). It is not necessary to calculate the skew between the data signals), and the design of the data receiving circuit can be facilitated.

  FIG. 17 is a waveform diagram for explaining the problems of the data receiving circuit 71 according to the second embodiment of the present invention. (A) shows the system clock sck0 in the circuit module 1_0, and (B) shows the inverted system clock sck0x in the circuit module 1_0.

  (C) is an acknowledge signal ack1 reaching the circuit module 1_0, (D) is an acknowledge signal ack1d output from the variable delay circuit 72, (E) is an acknowledge signal ack1dx output from the D flip-flop 44, ( F) is an acknowledge signal ack1dz output from the D flip-flop 43, (G) is a detection signal sy output from the detection circuit 46, (H) is an acknowledge signal ac1 output from the selector 47, and (I) is a D flip-flop. 49 shows an acknowledge signal a1 output by 49.

  (J) is the data signal data1_00 to data1_63 that has reached the circuit module 1_0, (K) is the data signal data1_00z to data1_63z output from the D flip-flops 45_00z to 45_63z, and (L) is the output from the D flip-flops 45_00x to 45_63x. Data signals data1_00x to data1_63x, (M) indicates data signals da1_00 to da1_63 output from the selectors 48_00 to 48_63, and (N) indicates data signals d1_00 to d1_63 output from the D flip-flops 50_00 to 50_63.

  When the clock cycle time is shortened by further increasing the speed of data transmission / reception between the circuit modules 1_0 and 1_1, for example, as shown in FIG. 17, the earliest data signal in the data signals data1_00 to data1_63 When the latch is first latched by the D flip-flops 45_00z to 45_63z at t16, the acknowledge signal ack1d may not be latched first by the D flip-flop 44 at time t17 after 0.5 cycle.

  In this case, the acknowledge signal ack1d is latched by the D flip-flop 43 for the first time after waiting for the rising of the system clock sck0 at time t18 after another 0.5 cycle. N), a one-cycle data shift occurs between the leading data b0 and the acknowledge signal a1 in the circuit module 1_0, and the acknowledge signal a1 and the data signals d1_00 to d1_63 cannot be synchronized. become. A data receiving circuit according to the third embodiment of the present invention has solved such problems.

(Third embodiment)
FIG. 18 is a circuit diagram showing a state in which the data receiving circuit 95 according to the third embodiment of the present invention is mounted on the circuit module 1_0. The data receiving circuit 95 according to the third embodiment of the present invention outputs the variable delay circuit 96 that delays the system clock sck0, the delay value control circuit 97 that controls the delay value of the variable delay circuit 96, and the variable delay circuit 96. An inverter 98 that inverts the delayed system clock sckd0 and outputs the inverted delayed system clock sckd0x is provided.

  The delayed system clock sckd0 is supplied to the D flip-flops 43, 45_00z to 45_63z, 49, 50_00 to 50_63, and the inverted delayed system clock sckd0x is supplied to the D flip-flops 44, 45_00x to 45_63x. The configuration is the same as that of the data receiving circuit 71 of the second embodiment of the invention. The data receiving circuit 95 according to the third embodiment of the present invention is also mounted on the circuit module 1_1.

  FIG. 19 is a circuit diagram showing a configuration of the variable delay circuit 96. In FIG. 19, 100 is a buffer with a delay value of Tb [sec], 101 is a buffer with a delay value of 2 × Tb [sec], 102 is a buffer with a delay value of 4 × Tb [sec], and 103 is a delay. This is a buffer whose value is 8 × Tb [sec].

  Reference numeral 104 denotes an incremental counter (hexadecimal counter) that counts the incremental pulse INC2 output from the delay value control circuit 97 and outputs count values e3 (most significant bit), e2, e1, and e0 (least significant bit).

  A selector 105 selects the system clock sck0 or the output of the buffer 100. The count value e0 is given as a selection control signal. When the count value e0 = “0”, the system clock sck0 is selected and the count value e0 is selected. When “= 1”, the output of the buffer 100 is selected.

  Reference numeral 106 denotes a selector that selects the output of the selector 105 or the output of the buffer 101. The count value e1 is given as a selection control signal. When the count value e1 = “0”, the output of the selector 105 is selected. When the value e1 = “1”, the output of the buffer 101 is selected.

  Reference numeral 107 denotes a selector for selecting the output of the selector 106 or the output of the buffer 102. When the count value e2 is given as a selection control signal, and the count value e2 = “0”, the output of the selector 106 is selected and counted. When the value e2 = “1”, the output of the buffer 102 is selected.

  Reference numeral 108 denotes a selector for selecting the output of the selector 107 or the output of the buffer 103. When the count value e3 is given as a selection control signal, and the count value e3 = “0”, the output of the selector 107 is selected and counted. When the value e3 = “1”, the output of the buffer 103 is selected.

  FIG. 20 is a table showing the function of the variable delay circuit 96. The total number of incremental pulses INC2 output from the delay value control circuit 97, the count values e3, e2, e1, e0 of the incremental counter 104, and the variable delay circuit. The relationship with 96 delay values is shown. That is, the variable delay circuit 96 increments the count values e3, e2, e1, and e0 of the incremental counter 104 and changes the delay value every time the incremental pulse INC2 output from the delay value control circuit 97 is input. The initial value of the delay value is 0 [sec], and the variable range is 0 to 15 Tb [sec].

  FIG. 21 is a circuit diagram showing a configuration of the delay value control circuit 97. In FIG. 21, reference numerals 110 to 112 denote inverters constituting an inverting delay circuit that inverts and delays the count value c3 output from the delay value control circuit 73, and 113 denotes an incremental pulse by performing NOR processing on the count value c3 and the output q1 of the inverter 112. It is a NOR circuit that outputs INC2.

  FIG. 22 is a waveform diagram showing the operation of the delay value control circuit 97, where (A) shows the incremental pulse INC1 output from the delay value control circuit 73, and (B) shows the count value c0 of the incremental counter 79 of the variable delay circuit 72. c3, (C) is the output q1 of the inverter 112 of the delay value control circuit 97, (D) is the incremental pulse INC2 output from the delay value control circuit 97, and (E) is the count value e0 of the incremental counter 104 of the variable delay circuit 96. Is shown.

  That is, the delay value control circuit 97 receives the count value c3 output from the incremental counter 79 of the variable delay circuit 72, and outputs an incremental pulse INC2 every time the count value c3 changes from “1” to “0”. It is.

  FIG. 23 is a flowchart showing a delay value setting procedure of the variable delay circuits 72 and 96 in the data receiving circuit 95 according to the third embodiment of the present invention. That is, in the delay value setting mode of the variable delay circuits 72 and 96, first, the delay value setting mode signal is set to “H” (step W1). Next, the circuit module 1_1 resets all the data signals data1_00 to data1_63 to “L” (step W2), and transmits the acknowledge signal ack1 and the data signals data1_00 to data1_63 in the next cycle (step W3).

  The circuit module 1_0 receives all “L” data signals data1_00 to data1_63 transmitted from the circuit module 1_1, performs data expectation value determination in the delay value control circuit 73 (step W4), and the D flip-flops 50_00 to 50_63 When all the output data signals d1_00 to d1_63 are not “L”, the delay value control circuit 73 generates an incremental pulse INC1 and increments the delay value of the variable delay circuit 72 (step W5).

  Next, it is determined whether or not the count value c3c2c1c0 of the incremental counter 79 has returned to “0000” (step W6). If not, that is, if the count value c3c2c1c0 is any of “0001” to “1111”. Returns to step W2. On the other hand, when the count value c3c2c1c0 returns to “0000”, the delay value control circuit 97 generates an incremental pulse INC2 to increment the delay value of the variable delay circuit 96 (step W7). Return.

  When the circuit module 1_0 successfully receives all the “L” data signals data1_00 to data1_63, that is, when all the “L” data signals d1_00 to d1_63 are successfully synchronized, the circuit module 1_1 receives the data signals data1_00 to data1_00. Data1_63 is all reset to “H” (step W8), and in the next cycle, the acknowledge signal ack1 and the data signal data1_00 to data1_63 are transmitted (step W9).

  The circuit module 1_0 receives all “H” data signals data1_00 to data1_63 transmitted from the circuit module 1_1, performs data expected value determination in the delay value control circuit 73 (step W10), and the D flip-flops 50_00 to 50_63 If all the output data signals d1_00 to d1_63 are not “H”, the delay value control circuit 73 generates an incremental pulse INC1 and increments the delay value of the variable delay circuit 72 (step W11).

  Next, it is determined whether or not the count value c3c2c1c0 of the incremental counter 79 has returned to “0000” (step W11). If not, that is, if the count value c3c2c1c0 is any of “0001” to “1111”. Returns to step W8. On the other hand, when the count value c3c2c1c0 returns to “0000”, an incremental pulse INC2 is generated from the delay value control circuit 97 to increment the delay value of the variable delay circuit 96 (step W13). Return.

  When the circuit module 1_0 has successfully received all the “H” data signals data1_00 to data1_63, ie, has successfully synchronized all the “H” data signals d1_00 to d1_63, the delay values of the variable delay circuits 72 and 96 are as follows. Finish the setting.

  That is, in the data receiving circuit 95 according to the third embodiment of the present invention, if the acknowledge signal a1 and the received data signals d1_00 to d1_63 are successfully synchronized by adjusting the delay value of the variable delay circuit 72, the variable delay circuit 96 Although the delay value is left as the initial value, if the synchronization of the acknowledge signal a1 and the received data signals d1_00 to d1_63 is not successful by adjusting the delay value of the variable delay circuit 72, the delay value of the variable delay circuit 96 is changed. Adjusted.

  FIG. 24 is a waveform diagram showing an operation example of the data receiving circuit 95 according to the third embodiment of the present invention, and shows that the state shown in FIG. 17 is avoided. (A) shows the system clock sck0 in the circuit module 1_0, (B) shows the delayed system clock sckd0 in the circuit module 1_0, and (C) shows the inverted delayed system clock sckd0x.

  (D) is an acknowledge signal ack1 reaching the circuit module 1_0, (E) is an acknowledge signal ack1d output from the variable delay circuit 72, (F) is an acknowledge signal ack1dx output from the D flip-flop 44, ( G) is an acknowledge signal ack1dz output from the D flip-flop 43, (H) is a detection signal sy output from the detection circuit 46, (I) is an acknowledge signal ac1 output from the selector 47, and (J) is a D flip-flop. 49 shows an acknowledge signal a1 output by 49.

  (K) is a data signal data1_00 to data1_63 that has reached the circuit module 1_0, (L) is a data signal data1_00z to data1_63z output from the D flip-flops 45_00z to 45_63z, and (M) is a data output from the D flip-flops 45_00x to 45_63x. Data signals data1_00x to data1_63x, (N) indicates data signals da1_00 to da1_63 output from the selectors 48_00 to 48_63, and (O) indicates data signals d1_00 to d1_63 output from the D flip-flops 50_00 to 50_63.

  According to the data receiving circuit 95 of the third embodiment of the present invention, the delay values of the delay system clock sckd0 and the inverted delay system clock sckd0x can be adjusted by the variable delay circuit 96, so that the data transmission / reception can be further speeded up. For example, when the earliest data signal in the data signals data1_00 to data1_63 is first latched by the D flip-flops 45_00z to 45_00z at time t16, as shown in FIG. In the second aspect of the present invention, there is a case where the acknowledge signal ack1d cannot be latched first by the D flip-flop 44 at time t17 after 0.5 cycle, and the received data signal cannot be synchronized. The data receiving circuit 71 of the embodiment is The problem which it has can be solved.

  That is, when adjusting the delay value of the variable delay circuit 96 and adjusting the delay values of the delay system clock sckd0 and the inverted delay system clock sckd0x as shown in FIGS. 44 latches the acknowledge signal ack1d at time t17 ′, and the D flip-flop 43 can latch the acknowledge signal ack1d at time t18 ′.

  In this case, as shown in the example of FIG. 3, since the detection signal sy maintains “H”, the selector 47 selects the acknowledge signal ack1dx output from the D flip-flop 44, and the D flip-flop 49 The acknowledge signal ack1dx (ac1) output from the selector 47 is latched at time t18 ′, and the acknowledge signal ack1dx (a1) is output as a reception signal of the acknowledge signal ack1.

  On the other hand, the data signals data1_00 to data1_63 reach the circuit module 1_0 between times t15 and t16. As a result, the D flip-flops 45_00z to 45_63z latch the data signals data1_00 to data1_63 at time t16 ′, and the D flip-flops 45_00x to 45_63x latch the data signals data1_00 to data1_63 at time t17 ′.

  Since the detection signal sy is “H”, the selectors 48_00 to 48_63 select the data signals data1_00x to data1_63x output from the D flip-flops 45_00x to 45_63x, and the D flip-flops 50_00 to 50_63 select the selector 48_00. The data signals data1_00x to data1_63x (data1_00 to da1_63) output by the 48_63 are latched at time t18 ′, and the data signals data1_00x to data1_63x (d1_00 to d1_63) are transferred to the internal circuit as reception signals of the data signals data1_00 to data1_63. .

  As described above, the data signals data1_00 to data1_63 reach the circuit module 1_0 during the time t15 to t16, and are first latched by the D flip-flops 45_00z to 45_63z at the time t16 ′, and the acknowledge signal ack1 is Even when the circuit module 1_0 has been reached between time t16 and t17, the delay value of the variable delay circuit 96 is adjusted so that the acknowledge signal ack1d is first latched by the D flip-flop 44 at time t17 ′. In this case, the acknowledge signal ack1dx (a1) and the data signals data1_00x to data1_63x (d1_00 to d1_63) can be cycle-synchronized and transferred to the internal circuit using the time t18 ′ as the transfer start time.

  The data receiving circuit 95 according to the third embodiment of the present invention includes a variable delay circuit 96, a delay value control circuit 97, and an inverter 98, and the other configurations are the same as those of the data receiving circuit 71 according to the second embodiment of the present invention. Therefore, according to the data receiving circuit 95 of the third embodiment of the present invention, similarly to the data receiving circuit 71 of the second embodiment of the present invention, the speed of data transmission / reception between the circuit modules 1_0 and 1_1 is increased. Accordingly, even when the skew between the system clocks sck0 and sck1 and the skew between the data signals data1_00 to data1_63 cannot be ignored, the received data signal can be synchronized, and the circuit modules 1_0 and 1_1 can be synchronized. Further speeding up of data transmission / reception can be achieved.

  In the data receiving circuit 95 according to the third embodiment of the present invention, the acknowledge signal output from the variable delay circuit 72 by the delay value control circuit 73 is the same as the data receiving circuit 71 according to the second embodiment of the present invention. The delay value of the variable delay circuit 72 required to make the phase of ack1d the same or delayed with respect to the most delayed data signal in the data signals data1_00 to data1_63 can be automatically set.

  Therefore, the skew between the system clocks sck0 and sck1 and the data signal output first (data signal with the most advanced phase) in the data signals data1_00 to data1_63 and the data signal output with the latest (the phase is most delayed). It is not necessary to calculate the skew between the data signals), and the design of the data receiving circuit can be facilitated.

  Further, since the variable delay circuit 96, the delay value control circuit 97, and the inverter 98 are provided, the clock cycle time is shortened by further increasing the speed of data transmission / reception between the circuit modules 1_0 and 1_1. For example, as shown in FIG. As described above, when the earliest data signal in the data signals data1_00 to data1_63 is latched first by the D flip-flops 45_00z to 45_63z, the acknowledge signal ack1d is first sent by the D flip-flop 44 after 0.5 cycles. Even when the latch cannot be performed, the acknowledge signal a1 and the data signals d1_00 to d1_63 can be synchronized. With this feature, the speed of data transmission / reception can be doubled as compared with the case of using the data receiving circuit 71 of the second embodiment of the present invention.

  In the circuit modules shown in FIG. 1, FIG. 9, and FIG. 18, an output terminal for request signal req0, an output terminal for acknowledge signal ack0, an output terminal for data signals data0_00 to data0_63, and a request signal req1. The input terminal for the acknowledge signal ack1 and the input terminal for the data signal data1_00 to data1_63 are provided, but an input / output terminal is provided instead of the output terminal and the input terminal. Also good. FIG. 25, FIG. 26, and FIG. 27 show a part in such a case.

  25, 26, and 27, 115 is an input / output terminal for acknowledge signals ack0 and ack1, 116_00 is an input / output terminal for data signals data0_00 and data1_00, and input / output for request signals req0 and req1. Terminals, input / output terminals for acknowledge signals ack0 and ack1, input / output terminals for data signals data0_01 and data1_01 to input / output terminals for data signals data0_63 and data1_63 are not shown. 117 and 118_00 are input buffers, 119 and 120_00 are output buffers, and 121, 122, 123_00 and 124_00 are D flip-flops.

  Here, when arranging the data receiving circuit of the present invention, the data receiving circuit of the present invention includes at least the following data receiving circuit.

  (Appendix 1) A data receiving circuit for receiving a plurality of data signals transmitted in parallel and an acknowledge signal necessary for recognizing the plurality of data signals, wherein the plurality of data signals are delayed by the acknowledge signal. A delay circuit that outputs a delayed acknowledge signal having the same phase or a delayed phase with respect to the most delayed data signal, and a first clock that captures the delayed acknowledge signal and the plurality of data signals with a first clock. A capture circuit; a second capture circuit that captures the delayed acknowledge signal and the plurality of data signals with a second clock having a phase opposite to that of the first clock; and Among them, the acknowledge signal and a plurality of data signals output from the capture circuit that previously fetched the delayed acknowledge signal are treated as valid signals. Data receiving circuit for.

  (Supplementary Note 2) An acknowledge signal output from the first and second capture circuits is input, and which of the first and second capture circuits captures the acknowledge signal output from the delay circuit first. A detection circuit to be detected and an acknowledge signal and a plurality of data signals output from the first acquisition circuit or an acknowledge signal and a plurality of data signals output from the second acquisition circuit are controlled by the detection circuit The data receiving circuit according to claim 1, further comprising a selection circuit that performs the selection.

  (Supplementary note 3) The data receiving circuit according to supplementary note 2, further comprising a third capture circuit that captures an acknowledge signal and a plurality of data signals output from the selection circuit at the first clock.

  (Additional remark 4) The said delay circuit is a variable delay circuit, It has a delay value control circuit which controls the delay value of the said delay circuit, The data receiving circuit of Additional remark 1, 2 or 3 characterized by the above-mentioned.

  (Supplementary Note 5) The delay value control circuit outputs a first incremental pulse as a delay value control signal for controlling a delay value of the delay circuit, and the delay circuit counts the number of the first incremental pulses. The data receiving circuit according to claim 4, further comprising: a first incremental counter; and a first variable delay unit whose delay value is controlled by an output of the first incremental counter.

  (Supplementary Note 6) The delay value control circuit is configured such that, when the delay value setting mode of the delay circuit is in the delay value setting mode, the plurality of data for setting the delay value is synchronized until the synchronization of the received data signals for setting the delay value becomes normal. 6. The data receiving circuit according to appendix 5, wherein the first incremental pulse is output every time a signal is received.

  (Supplementary note 7) The data reception circuit according to Supplementary note 4, 5 or 6, further comprising a clock delay circuit that uses the first clock as a clock having a phase delayed from the transmission clock on the transmission side.

  (Supplementary note 8) The data receiving circuit according to supplementary note 7, wherein the clock delay circuit is a variable delay circuit and includes a clock delay value control circuit for controlling a delay value of the clock delay circuit.

  (Supplementary Note 9) The clock delay value control circuit outputs a second incremental pulse as a delay value control signal for controlling a delay value of the clock delay circuit, and the clock delay circuit counts the number of the second incremental pulses. 9. The data receiving circuit according to claim 8, further comprising: a second incremental counter for counting the delay time; and a second variable delay unit whose delay value is controlled by an output of the second incremental counter.

  (Supplementary Note 10) In the clock delay value control circuit, when the delay value setting mode of the delay circuit is set, the synchronization of the received plurality of data signals for setting the delay value does not become normal due to the adjustment of the delay value of the delay circuit. The data receiving circuit according to appendix 9, wherein the delay value of the clock delay circuit is adjusted to a value other than the initial value.

It is a circuit diagram which shows the state which mounted the data receiving circuit of 1st Embodiment of this invention in the circuit module. It is a circuit diagram which shows the structure of the detection circuit with which the data receiving circuit of 1st Embodiment of this invention is provided. It is a wave form diagram which shows the 1st operation example of the detection circuit with which the data reception circuit of 1st Embodiment of this invention is provided. It is a wave form diagram which shows the 2nd operation example of the detection circuit with which the data receiving circuit of 1st Embodiment of this invention is provided. It is a wave form diagram which shows the 1st operation example of the data receiver circuit of 1st Embodiment of this invention. It is a wave form diagram which shows the 2nd operation example of the data receiver circuit of 1st Embodiment of this invention. It is a wave form diagram which shows the 3rd operation example of the data receiver circuit of 1st Embodiment of this invention. It is a wave form diagram which shows the 4th operation example of the data receiver circuit of 1st Embodiment of this invention. It is a circuit diagram which shows the state which mounted the data receiving circuit of 2nd Embodiment of this invention in the circuit module. It is a circuit diagram which shows the structure of the variable delay circuit for the acknowledge signal delay with which the data receiver circuit of 2nd Embodiment of this invention is provided. It is a table | surface figure which shows the function of the variable delay circuit for the acknowledge signal delay with which the data receiving circuit of 2nd Embodiment of this invention is provided. It is a circuit diagram which shows the structure of the delay value control circuit which controls the variable delay circuit for the acknowledge signal delay with which the data receiving circuit of 2nd Embodiment of this invention is provided. It is a table | surface figure which shows the operation | movement truth value of the data expected value determination part in the delay value control circuit which controls the variable delay circuit for an acknowledge signal delay with which the data receiving circuit of 2nd Embodiment of this invention is provided. It is a wave form diagram which shows the operation | movement at the time of a normal operation mode of the delay value control circuit which controls the variable delay circuit for an acknowledge signal delay with which the data receiver circuit of 2nd Embodiment of this invention is provided. It is a wave form diagram which shows a part of operation | movement at the time of the delay value setting mode of the delay value control circuit which controls the variable delay circuit for the acknowledge signal delay with which the data receiving circuit of 2nd Embodiment of this invention is provided. It is a flowchart which shows the delay value setting procedure of the variable delay circuit for the acknowledge signal delay in the data receiver circuit of 2nd Embodiment of this invention. It is a wave form diagram for demonstrating the problem which the data receiving circuit of 2nd Embodiment of this invention has. It is a circuit diagram which shows the state which mounted the data receiving circuit of 3rd Embodiment of this invention in the circuit module. It is a circuit diagram which shows the structure of the variable delay circuit for system clock delay with which the data receiver circuit of 3rd Embodiment of this invention is provided. It is a table | surface figure which shows the function of the variable delay circuit for system clock delay with which the data receiver circuit of 3rd Embodiment of this invention is provided. It is a table | surface figure which shows the structure of the delay value control circuit which controls the variable delay circuit for system clock delay with which the data receiver circuit of 3rd Embodiment of this invention is provided. It is a wave form diagram which shows operation | movement of the delay value control circuit which controls the delay value of the variable delay circuit for system clock delay with which the data receiver circuit of 3rd Embodiment of this invention is provided. It is a flowchart which shows the delay value setting procedure of the variable delay circuit in the data receiver circuit of 3rd Embodiment of this invention. It is a wave form diagram which shows the operation example of the data receiver circuit of 3rd Embodiment of this invention. It is a circuit diagram which shows the example which provides an input / output terminal in the circuit module which mounts the data receiver circuit of 1st Embodiment of this invention. It is a circuit diagram which shows the example which provides an input / output terminal in the circuit module which mounts the data receiver circuit of 2nd Embodiment of this invention. It is a circuit diagram which shows the example which provides an input / output terminal in the circuit module which mounts the data receiver circuit of 3rd Embodiment of this invention. It is a circuit diagram which shows the example of a connection of the common clock synchronous type circuit module which transmits / receives data. FIG. 29 is a circuit diagram showing a conventional configuration example of a part of the internal circuit of the circuit module shown in FIG. 28. FIG. 30 is a waveform diagram showing an example of data transmission / reception operation between the circuit modules shown in FIG. 29. FIG. 30 is a waveform diagram for explaining problems that the data receiving circuit shown in FIG. 29 has for further speeding up data transmission and reception.

Explanation of symbols

1_0, 1_1 ... circuit module 2 ... bus 3, 4, 5_00, 5_63 ... output terminal 6, 7, 8, 9_00, 9_63 ... input terminal 10, 11, 12_00, 12_63 ... output terminal 13, 14, 15, 16_00, 16_63 ... Input terminal 18 ... System clock generation circuit 19 ... PLL block 20 ... Feedback delay circuit 21 ... Data transmission circuit 22, 23, 24_00 ... D flip-flop 25 ... Data reception circuit 26, 27, 28_00 ... D flip-flop 29 ... System clock Generation circuit 30 ... PLL block 31 ... Feedback delay circuit 32 ... Data transmission circuit 33, 34, 35_00 ... D flip-flop 36 ... Data reception circuit 37, 38, 39_00 ... D flip-flop 41 ... Data of the first embodiment of the present invention Receive times 42 ... delay circuit 43, 44 ... D flip-flop 45_00z, 45_00x, 45_63z, 45_63x ... D flip-flop 46 ... detection circuit 47, 48_00, 48_63 ... selector 49, 50_00, 50_63 ... D flip-flop 52, 53 ... input buffer 54 ... Transmission gate 55 ... P channel MOS transistor 56 ... N channel MOS transistor 57 ... Transmission gate control circuit 58 ... AND circuit 59 to 61 ... NOR circuit 62 ... Latch part 63, 64 ... Inverter 65 ... Node 66 ... Transition detection part 67, 68 ... Inverter 69 ... Output buffer 71 ... Data receiving circuit 72 of the second embodiment of the present invention 72 ... Variable delay circuit 73 ... Delay value control circuit 75-78 ... Buffer 79 ... Incremental counter 80-83 ... Selector 85 ... Data expectation value judgment unit 86 ... AND circuit 87 ... Data expectation value judgment wait delay unit 88 ... Pulse generation unit 89 to 91 ... Inverter 92, 93 ... AND circuit 96 ... Variable delay circuit 97 ... Delay value control circuit 98 ... Inverter 100 ˜103 ... buffer 104 ... incremental counter 105-108 ... selector 110-112 ... inverter 113 ... NOR circuit 115, 116_00 ... input / output terminals 117,118_00 ... input buffer 119,120_00 ... output buffers 121,122,123_00,124_00 ... D flip flop

Claims (5)

A data receiving circuit for receiving a plurality of data signals transmitted in parallel and an acknowledge signal necessary for recognizing the plurality of data signals,
A delay circuit that delays the acknowledge signal and outputs a delayed acknowledge signal that is the same or delayed in phase with respect to the most delayed data signal in the plurality of data signals;
A first capture circuit that captures the delayed acknowledge signal and the plurality of data signals with a first clock;
A second capture circuit that captures the delayed acknowledge signal and the plurality of data signals with a second clock having a phase opposite to that of the first clock;
A data receiving circuit characterized in that an acknowledge signal and a plurality of data signals output from the fetch circuit that fetches the delayed acknowledge signal first among the first and second fetch circuits are treated as valid signals. A detection circuit for inputting an acknowledge signal output from the first and second capture circuits and detecting which of the first and second capture circuits previously captures the acknowledge signal output from the delay circuit. When,
A selection circuit that is controlled by the detection circuit and selects an acknowledge signal and a plurality of data signals output from the first capture circuit or an acknowledge signal and a plurality of data signals output from the second capture circuit; The data receiving circuit according to claim 1. The delay circuit is a variable delay circuit,
3. The data receiving circuit according to claim 1, further comprising a delay value control circuit for controlling a delay value of the delay circuit. The delay value control circuit outputs an incremental pulse as a delay value control signal for controlling a delay value of the delay circuit,
4. The data receiving circuit according to claim 3, wherein the delay circuit includes an incremental counter that counts the number of the incremental pulses, and a variable delay unit in which a delay value is controlled by an output of the incremental counter. 5. The data receiving circuit according to claim 3, further comprising a clock delay circuit that uses the first clock as a clock that is delayed in phase from the transmitting clock on the transmitting side.

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