JPH0563365A - Structure of sintered multilayer board - Google Patents
Structure of sintered multilayer boardInfo
- Publication number
- JPH0563365A JPH0563365A JP22301191A JP22301191A JPH0563365A JP H0563365 A JPH0563365 A JP H0563365A JP 22301191 A JP22301191 A JP 22301191A JP 22301191 A JP22301191 A JP 22301191A JP H0563365 A JPH0563365 A JP H0563365A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- pattern
- printed circuit
- density
- sintered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、混成集積回路等を形成
する焼結多層基板の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a sintered multi-layer substrate for forming a hybrid integrated circuit or the like.
【0002】[0002]
【従来の技術】図3に示すように、従来から、混成集積
回路等に、所定の印刷回路1を設けた複数の基板2,2
を積層して焼結した多層基板3が用いられている。基板
2の材質としては、高温で焼成するアルミナ基板や低温
で焼成するセラミック基板等が用いられている。2. Description of the Related Art Conventionally, as shown in FIG. 3, a plurality of substrates 2 and 2 provided with a predetermined printed circuit 1 on a hybrid integrated circuit or the like.
A multilayer substrate 3 is used which is obtained by stacking and sintering. As the material of the substrate 2, an alumina substrate that is fired at a high temperature, a ceramic substrate that is fired at a low temperature, or the like is used.
【0003】この中で、低温焼成型の基板、例えばグリ
ーンシートなどのセラミック基板は、高温焼成型のもの
に比べて焼き上がりの収縮率が安定しているという長所
を有している。Among these, low temperature firing type substrates, for example, ceramic substrates such as green sheets, have the advantage that the shrinkage rate after baking is more stable than high temperature firing type substrates.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、基板の
内層に形成される印刷回路1のパターン密度に大きな差
があり、例えば図3におけるA部のようにパターンが形
成されない部分、あるいはパターンが形成されていても
粗い部分があると、該部分とパターンが多数形成されて
いる部分とで、焼き上がり時の収縮率にバラツキを生じ
ることがあり、寸法精度が損なわれて不良品となること
があった。However, there is a large difference in the pattern densities of the printed circuits 1 formed on the inner layer of the substrate. For example, a portion where the pattern is not formed or a pattern is formed like the portion A in FIG. However, if there is a rough portion, the shrinkage ratio at the time of baking may vary between the portion and the portion where a large number of patterns are formed, and the dimensional accuracy may be impaired, resulting in a defective product. It was
【0005】そこで本発明は、上記収縮率のバラツキを
無くして寸法精度に優れた焼結多層基板を得ることがで
きる構造を提供することを目的としている。Therefore, an object of the present invention is to provide a structure capable of obtaining a sintered multilayer substrate excellent in dimensional accuracy by eliminating the above-mentioned variation in shrinkage ratio.
【0006】[0006]
【課題を解決するための手段】上記した目的を達成する
ため、本発明の焼結多層基板の構造は、表面に所定の印
刷回路を設けた複数の基板を積層して焼結した多層基板
において、前記基板の印刷回路のパターン密度が粗な部
分に、印刷回路形成材料と同一の材料を用いた捨てパタ
ーンを設けたことを特徴としている。In order to achieve the above object, the structure of a sintered multilayer substrate of the present invention is a multilayer substrate obtained by stacking and sintering a plurality of substrates having a predetermined printed circuit on the surface thereof. It is characterized in that a discard pattern made of the same material as the printed circuit forming material is provided in a portion of the substrate where the printed circuit has a rough pattern density.
【0007】[0007]
【作 用】上記構成によれば、基板表面のパターン密度
を平均化でき、焼き上がり時の収縮率のバラツキを無く
すことができる。[Operation] According to the above configuration, it is possible to average the pattern density on the substrate surface and eliminate variations in shrinkage rate during baking.
【0008】[0008]
【実施例】以下、本発明を、図1及び図2に示す一実施
例に基づいて、さらに詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to an embodiment shown in FIGS.
【0009】この多層基板11は、従来と同様の手順で
各基板12,12の表面に所定の印刷回路13を形成
し、これを積層して圧着しながら焼成したものである。This multi-layer substrate 11 is formed by forming a predetermined printed circuit 13 on the surface of each substrate 12, 12 in the same procedure as in the conventional method, stacking the printed circuits 13 and baking them while pressure bonding.
【0010】そして、各基板12における回路パターン
が形成されない部分あるいは回路パターンが形成されて
いても粗い部分には、ダミー回路としての捨てパターン
14が設けられている。この捨てパターン14は、印刷
回路13を形成する材料と同一の材料を用いて、印刷回
路13のパターン印刷と同時に印刷されて形成されたも
のである。A discard pattern 14 as a dummy circuit is provided on a portion of each substrate 12 where the circuit pattern is not formed, or on a rough portion where the circuit pattern is formed. The discard pattern 14 is formed by printing the pattern of the printed circuit 13 simultaneously with the same material as that of the printed circuit 13.
【0011】上記捨てパターン14を設ける位置や密度
等は、基板12に設けられる印刷回路13の状態に応じ
て適宜設定することができる。即ち、捨てパターン14
は、基板12上に平均的にパターンが分布するように設
定することが好ましいが、収縮率のバラツキによる寸法
誤差が所定の範囲内に納まるように、位置や密度,太
さ,方向等を設定すれば良い。The position, density, etc. of the discard pattern 14 can be appropriately set according to the state of the printed circuit 13 provided on the substrate 12. That is, the discard pattern 14
Is preferably set so that the pattern is evenly distributed on the substrate 12, but the position, density, thickness, direction, etc. are set so that the dimensional error due to the variation of the shrinkage ratio falls within a predetermined range. Just do it.
【0012】このように基板12の印刷回路13のパタ
ーン密度が粗な部分に捨てパターン14を設けることに
より、焼成時の基板12の収縮率を略一定にすることが
でき、焼き上がり時の収縮率のバラツキを少なくして寸
法精度を向上させることができる。As described above, by providing the discard pattern 14 in the portion of the printed circuit 13 of the substrate 12 where the pattern density is rough, the shrinkage rate of the substrate 12 during firing can be made substantially constant, and the shrinkage during firing can be reduced. The dimensional accuracy can be improved by reducing the variation in the rate.
【0013】なお、積層される各基板のパターン密度が
大きく異なる場合には、最もパターンが密に形成されて
いる基板のパターン密度に対応するように他の基板に捨
てパターンを設けることにより、積層焼結される各基板
のパターン密度を平均化させて、基板間の収縮率のバラ
ツキも防止することができる。When the pattern densities of the substrates to be laminated are greatly different, the other substrate is provided with a discard pattern so as to correspond to the pattern density of the substrate on which the pattern is most densely formed. The pattern density of each substrate to be sintered can be averaged to prevent variation in shrinkage ratio between the substrates.
【0014】[0014]
【発明の効果】以上説明したように、本発明によれば、
基板表面のパターン密度を平均化することにより、焼き
上がり時の収縮率のバラツキを少なくすることができる
ので、寸法精度に優れた焼結多層基板を得ることがで
き、歩留まりの向上による製造コストの低減を図ること
ができる。As described above, according to the present invention,
By averaging the pattern density on the substrate surface, it is possible to reduce the variation in shrinkage rate during baking, so that it is possible to obtain a sintered multilayer substrate with excellent dimensional accuracy, and to improve the manufacturing cost due to improved yield. Reduction can be achieved.
【図1】 本発明の一実施例を示す焼結多層基板の断面
図である。FIG. 1 is a cross-sectional view of a sintered multilayer substrate showing an embodiment of the present invention.
【図2】 同じく基板面の平面図である。FIG. 2 is likewise a plan view of the substrate surface.
【図3】 従来の焼結多層基板の一例を示す断面図であ
る。FIG. 3 is a sectional view showing an example of a conventional sintered multilayer substrate.
11…多層基板 12…基板 13…印刷回路
14…捨てパターン11 ... Multilayer substrate 12 ... Substrate 13 ... Printed circuit
14 ... Discard pattern
Claims (1)
板を積層して焼結した多層基板において、前記基板の印
刷回路のパターン密度が粗な部分に、印刷回路形成材料
と同一の材料を用いた捨てパターンを設けたことを特徴
とする焼結多層基板の構造。1. A multilayer substrate obtained by laminating and sintering a plurality of substrates each having a predetermined printed circuit on the surface thereof, the same material as the printed circuit forming material being provided in a portion where the pattern density of the printed circuit of the substrate is rough. A structure of a sintered multi-layer substrate, characterized by being provided with a discard pattern using.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22301191A JPH0563365A (en) | 1991-09-03 | 1991-09-03 | Structure of sintered multilayer board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22301191A JPH0563365A (en) | 1991-09-03 | 1991-09-03 | Structure of sintered multilayer board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0563365A true JPH0563365A (en) | 1993-03-12 |
Family
ID=16791437
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22301191A Pending JPH0563365A (en) | 1991-09-03 | 1991-09-03 | Structure of sintered multilayer board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0563365A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014053575A (en) * | 2012-09-10 | 2014-03-20 | Ngk Insulators Ltd | Circuit board for peripheral circuit of large capacity module, and manufacturing method of circuit board |
JP2016213332A (en) * | 2015-05-11 | 2016-12-15 | パナソニックIpマネジメント株式会社 | Common mode noise filter |
-
1991
- 1991-09-03 JP JP22301191A patent/JPH0563365A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014053575A (en) * | 2012-09-10 | 2014-03-20 | Ngk Insulators Ltd | Circuit board for peripheral circuit of large capacity module, and manufacturing method of circuit board |
JP2016213332A (en) * | 2015-05-11 | 2016-12-15 | パナソニックIpマネジメント株式会社 | Common mode noise filter |
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