JPH056334A - Bus control device - Google Patents

Abstract

PURPOSE:To improve the using efficiency of a bus by generating a bus use permission signal corresponding to the bus use requesting quantity of each data transfer device. CONSTITUTION:A bus control device 1 permitting the use of a data bus to each data transfer device is provided with a priority order storing table 1114 storing plural priority order sorts corresponding to the data transfer devices, a counter 112 formed correspondingly to each corresponding data transfer device, an adder 1111 corresponding to each data transfer device to add '1' to the counter 1112 when a data transfer request is generated from the corresponding data transfer device, an address generating circuit 1113 for selecting one of the priority sorts from the table 1114 while referring the value of the counter 1112, a selecting circuit 12 for selecting a data transfer device in accordance with the priority order selected by the circuit 1113, a subtractor 1115 for subtracting '1' from the counter 1112 corresponding to the data transfer device selected by the circuit 12, and a bus use permission signal generating circuit 13 for permitting the use of the data bus 3 to the data transfer device selected by the circuit 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus structure communication type information processing apparatus, and more particularly to a bus control apparatus for giving a bus transfer right to a data transfer apparatus.

[0002]

2. Description of the Related Art Conventionally, in this type of bus control device, the following methods can be mentioned as a method of controlling a bus use permission signal.

1. The data transfer devices are sequentially selected at fixed time intervals and the bus use right is given.

2. A priority is given to each data transfer device, and a bus use right is given in accordance with the priority in response to a request from the data transfer device.

[0005]

In the above method 1, since the bus use right is given regardless of the presence or absence of the bus use request from the data transfer device, that is, to the data transfer device not requesting the bus use. However, since the bus use right is given, in a system in which the frequency and importance of the bus use of the data transfer device are unbalanced, the bus use efficiency of the data transfer device having a high demand for the bus is reduced.

Further, the above method 2 has a drawback that the data transfer device cannot issue the next request until the bus control device receives the signal of the bus use request from the data transfer device. Further, a signal response is required between the data transfer device and the selection circuit in the bus control device for priority determination, and the bus cannot be used during that time, resulting in a drop in bus usage efficiency.

[0007]

An apparatus according to the present invention is connected to a plurality of data transfer devices via a data bus, and responds to a data transfer request from the data transfer device by providing a data bus to the data transfer device. In the bus control device that permits the use of the data transfer device, a priority holding table that holds a plurality of priorities corresponding to the data transfer device, a counter provided corresponding to the data transfer device, An adder corresponding to the data transfer device that adds "1" to the counter when a data transfer request is generated, and an address generation circuit corresponding to the data transfer device that selects the priority from the priority holding table by referring to the value of the counter A selection circuit for selecting a data transfer device according to the priority order selected by the address generation circuit; and a selection circuit selected by the selection circuit. A subtracter corresponding to the data transfer device for subtracting "1" from the counter corresponding to the data transfer device, and a bus use permission signal generation circuit for permitting the data transfer device selected by the selection circuit to use the data bus. It is characterized by having.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a bus control device, and 21
2n is a data transfer device, 3 is a data bus, 181
-18n is a bus use permission signal, 217-2n7 is a bus use request signal, and 19 is received data 218-2n8.
Indicates transmission data.

In the bus controller 1, 111 to 11n
Is a priority order determination circuit for determining the priority order for each data transfer device, 12 is a selection circuit for selecting the bus use request source data transfer device according to the priority order given by the priority order determination circuits 111 to 11n, and 13 is selected Reference numeral 14 denotes a bus use permission signal generation circuit for generating a bus use permission signal to the data transfer device according to the result of the circuit 12, and reference numeral 14 denotes a data reception buffer.

In the priority determining circuits 111 to 1n1, 1111 to 11n1 are adders, and 1112 to 11n.
Reference numeral 2 is a counter for calculating the number of bus use requests in the use permission waiting state, and 1113 to 11n3 are address generation circuits for generating table addresses by referring to the counter values.
Reference numerals 1114 to 11n4 denote priority order holding tables for holding a plurality of priority orders of the data transfer devices.
Indicate subtractors, respectively.

In the data transfer devices 21 to 2n, 21
1 to 2n1 are data transmission circuits, 212 to 2n2 are bus use request signal generation circuits for generating bus use request signals,
213 to 2n3 are data transmission buffers and 214 to 2n.
4 is a data transmission buffer 213-
Data transfer control circuits for controlling 2n3 are shown respectively.

The data transfer devices 21 to 2n store the information in the data transmission buffers 213 to 2n3 when a use condition occurs in the data bus in the data transmission circuits 211 to 2n1 and use the bus for the bus control device 1. Bus use request signal 217 from request signal generation circuits 212 to 2n2
Request use of data bus via ~ 2n7. By this request, the adders 1111 to 11n1 cause the counter 1112 to
"1" is added to 11n2.

By referring to the values of the counters 1112 to 11n2, the address generation circuits 1113 to 11n3 generate table addresses 1117 to 11n7, and the priority levels 151 to 15 from the priority level holding tables 1114 to 11n4.
Output n.

The selection circuit 12 uses the priority holding table 1
The bus transfer enable signal generating circuit 1 is selected by referring to the outputs 114 to 11n4 to select the data transfer device having the highest priority.
3 to generate bus use permission signals 181 to 18n.

Upon receipt of the bus use permission signal, the data transfer device transfers the contents of the data transmission buffers 213 to 2n3 to the data reception buffer 14 via the data bus 3 by the data transfer control circuits 214 to 2n4.

Further, the bus use permission signal generating circuit 13 is
The counters 1112 to 11n2 corresponding to the data transfer device previously selected by the counter subtraction signals 171 to 17n are subtracted by "1" using the subtractors 1115 to 11n5, and the operation is completed.

As a result of the above operation, the counters 1112 to 11n2 in the bus control unit 1 are set to the data transfer units 21 to 2 respectively.
The number of data transfer requests from n is stored. Using the contents of this counter, the priority holding table 11
14 to 11n4 are read, and the selection circuit 12 determines the priority based on the read result, and the priority holding table 1114.
The use of the bus can be permitted according to the set values of 11n4.

Further, since the number of bus use requests from each of the data transfer devices 21 to 2n is counted in the bus control device 1, the bus control device 1 continuously issues a bus use permission to the data transfer devices 21 to 2n. The data transfer devices 21 to 2n can make a bus use request without waiting for the bus use permission.

In FIG. 1, data transfer is performed from the data transfer devices 21 to 2n to the bus control device 1, but the reverse can be easily realized by the same method.

[0022]

As described above, according to the present invention, the bus controller waits for the counter for calculating the number of requests for bus use for each data transfer device and the priority holding table indexed by the coefficient value of the counter. A bus permission signal can be generated according to the bus usage request amount of each data transfer device, and an efficient bus control device can be configured.

Further, since the counter in the bus control device holds the bus usage request amount of the data transfer device, the data transfer device can report all occurrences of the bus usage request, and the bus usage in the data transfer device can be reported. The request signal generation circuit can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 Bus control device 111-11n Priority determination circuit 1111-11n1 Adder 1112-11n2 Counter 1113-11n3 Address generation circuit 1114-11n4 Priority holding table 1115-11n5 Subtractor 1116-11n6 Counter value 1117-11n7 Table address 12 selection Circuit 13 Bus use permission signal generation circuit 14 Data reception buffer 151 to 15n Priority 16 Selection result 171 to 17n Counter subtraction signal 181 to 18n Bus use permission signal 19 Received data 21 to 2n Data transfer device 211 to 2n1 Data transmission circuit 212 to 2n2 bus use request signal generation circuit 213-2n3 data transmission buffer 214-2n4 data transfer control circuit 215-2n5 data transmission signal 216-2n6 transmission data 217 2n7 bus request signal 218~2n8 transmission data 219~2n9 data transfer control signal 3 data bus

Claims (1)

Claim: What is claimed is: 1. A plurality of data transfer devices are connected via a data bus, and the data transfer device is permitted to use the data bus in response to a data transfer request from the data transfer device. In the bus controller, a priority holding table for holding a plurality of priorities corresponding to the data transfer device, a counter provided corresponding to the data transfer device, and a data transfer request generation from the data transfer device. An adder corresponding to the data transfer device for adding "1" to the counter at times, an address generation circuit corresponding to the data transfer device for selecting the priority from the priority holding table by referring to the value of the counter, and the address A selection circuit for selecting a data transfer device according to the priority order selected by the generation circuit, and a data transfer device selected by the selection circuit. And a subtracter corresponding to the data transfer device for subtracting "1" from the counter corresponding to the above, and a bus use permission signal generation circuit for permitting the data transfer device selected by the selection circuit to use the data bus. And bus control device.