JPH0560855A - Transmission pules control circuit - Google Patents

Abstract

PURPOSE:To prevent an antenna module control signal from staying ON by resetting the antenna module control signal properly when a pulse width modification signal is output. CONSTITUTION:A transmission pulse control circuit allows a pulse modification signal to be fed to a one-shot circuit 15, a pulse with a proper length to be output only when the pulse width modification signal is output, the pulse to be multiplied by a signal with a proper timing from a pulse width latch 5 and a pulse period latch 8, and then the antenna module control signal to be reset immediately after a transmission pulse is output. Only when the pulse width modification signal is input, the antenna module control signal is reset at a proper timing and control is made so that a pulse can be transmitted properly when the pulse width modification signal is input, thus avoiding generation of an antenna module control failure and hence preventing the antenna module control signal ON from staying at, ON-situation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radar transmission pulse control circuit using a module antenna.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a configuration of a conventional transmission pulse control circuit. In the figure, 1 is a bus transceiver which sends the transmission pulse width data from the signal processor to the register by a write latch, and 2 is a latch for the transmission pulse width data from the bus transceiver to the pulse width counter by the pulse width change trigger. When the load signal comes in, the register 3 outputs the data from the register and starts counting, while the pulse width counter 4 which outputs the carry signal to its own load signal and pulse period counter, 4 becomes the count value output from 3 A pulse width decoder for outputting a signal of a corresponding code, 5 is a pulse width latch for latching and outputting an input signal from 4 to a clock signal, 6 is a pulse cycle counter for counting 3 carry signals, and 7 is 6
A pulse period decoder that outputs a signal of a code corresponding to the count value that is output from 8; a pulse period latch that outputs the input signal from 7 by latching it with a clock signal;
9 selects an appropriate signal from the signals output from 5 and 8 according to the modulation code data from 2, and outputs the JK flip
A selector for outputting a signal to a flop, a 10 for determining the ON / OFF timing of the antenna module, and a JK flip-flop for outputting an appropriate control signal to the buffer, and a 11 for generating a pulse modulation signal by the signals of 3 and 6. A pulse modulation signal generator, 12 is an original oscillation circuit, and 13 is 12
A mixer which multiplies the carrier signal from (1) with a pulse modulation signal to code the signal, and 14 is a buffer having a detection circuit for detecting an antenna module control signal abnormality.

Next, the operation will be described. The transmit pulse width data input from the signal processor is inverted by the bus transceiver by the write latch and output to the register 2. The signal input to the register 2 is sent to the pulse width counter 3 when a pulse width changing trigger is applied. The pulse width counter 3 receives the pulse width data, starts counting for each clock, and sends the count value to the pulse width decoder 4. The pulse width decoder 4 selects a signal corresponding to the input count value and sends the signal to the pulse width latch 5. The pulse width latch 5 latches the signal from the pulse width decoder 4 into a clock signal and sends it to the selector 9. On the other hand, regarding the pulse cycle counter 6, the pulse cycle decoder 7, and the pulse cycle latch 8, the above-mentioned 3,
Although the operation is the same as 4 and 5, the pulse period counter 6 counts the carry signal of the pulse width counter 3. As described above, the selector 9 which receives the signals of the pulse width latch 5 and the pulse cycle latch 8 selects an appropriate signal from the signals sent from the pulse width latch 5 and the pulse cycle latch 8 according to the modulation code data output from the register 2. Select the signal, J
Send to K flip-flop. This signal causes the JK flip-flop to output O of the antenna module control signal.
The N / OFF timing is determined, and an appropriate control signal is output according to the pulse width. This signal is sent to the buffer circuit 14
To the antenna section, and after detecting abnormalities whether or not the antenna module is turned on more than necessary through the abnormality detection circuit, it is sent to the antenna section.
Used for FF control. On the other hand, the pulse-modulated signal output from the pulse-modulated-signal generator 11 upon receiving the data of the pulse width counter 3 and the pulse period counter 6 is
The carrier signal output from 2 is multiplied by the mixer 13 to pulse the carrier signal. The pulsed signal is output from the mixer 13, is driven by the buffer circuit 14, and is then sent to the antenna unit and amplified and output.

[0004]

The conventional transmission pulse control circuit is configured as described above, and when the pulse width change signal is input while the antenna module control signal is in the ON state, the antenna module control signal is The ON state may continue, and if the changed pulse width is long,
The abnormality detection circuit in the buffer may detect an abnormality, which may lead to system down. In addition, if the antenna module control signal is kept ON for a long time when not transmitting, there is a problem in that the receiver is likely to receive noise.

The present invention has been made to solve the above-mentioned problems, and when the pulse width change signal is output, the antenna module control signal is turned on by appropriately resetting the antenna module control signal. The purpose is to prevent the situation from continuing to occur.

[0006]

A transmission pulse control circuit according to the present invention passes a pulse change signal through a one-shot circuit, outputs a pulse of an appropriate length only when the pulse width change signal is output, and , The pulse width latch 5 and the signal from the pulse period latch 8 at appropriate timing are multiplied, and the antenna module control signal is reset immediately after the transmission pulse is output.

[0007]

The transmission pulse control circuit according to the present invention resets the antenna module control signal at an appropriate timing only when the pulse width change signal is input, and the pulse at the time when the pulse width change signal is input can be normally transmitted. To control. This makes it possible to avoid the occurrence of antenna module control abnormalities.

[0008]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 1 to 10 are the same as the above-mentioned conventional device. 15 is a one-shot circuit, 16 is an AND
It is a gate.

Next, the operation will be described. 1 to 9 in FIG.
Up to the above, the operation is similar to that of the conventional circuit. The pulse width changing signal is input to the register 2 and the one shot circuit 15 at the same time. The output is a pulse as shown in FIG. On the other hand, the pulse width counter 3 and the pulse cycle counter 6 count at the timing shown in FIG. At this time, the output signal of the one-shot circuit is ANDed with a part of the signals of the pulse width counter and the pulse cycle counter (see FIG. 2D) and input to the reset signal of the JK flip-flop. As a result, the pulse width change signal is output and the antenna module control signal is reset immediately after the transmission pulse is output. (See Figure 2 (e))

[0010]

Since the present invention is configured as described above, when the pulse width is updated by the pulse width changing signal, the antenna module control signal is once reset and the module continues to be in the ON state. To prevent
The abnormal state detection circuit can be operated without falling into an abnormal state.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a transmission pulse control circuit according to a first embodiment of the present invention.

FIG. 2 is a pulse modulation signal, pulse period counter, pulse width counter, one-shot circuit according to the first embodiment of the present invention,
It is a figure which shows an example of a reset signal and the timing of antenna module ON / OFF.

FIG. 3 is a diagram showing a configuration of a conventional transmission pulse control circuit.

FIG. 4 is a diagram showing an example of timings of a pulse modulation signal, an antenna module ON / OFF, and an antenna module control signal of a conventional device.

[Explanation of symbols]

 1 bus transceiver 2 register 3 pulse width counter 4 pulse width decoder 5 pulse width latch 6 pulse cycle counter 7 pulse cycle decoder 8 pulse cycle latch 9 selector 10 JK flip-flop 11 pulse modulation signal generator 12 oscillator circuit 13 mixer 14 Buffer 15 One-shot circuit 16 AND gate

Claims (1)

[Claims] 1. A bus transceiver for reading data from a signal processor while latching the data by a write latch,
The register that latches the input data by the pulse width change signal and sends the signal, counts the data from the register as the initial value, sends the count value to the decoder, and sends the carry signal to its own load signal and pulse period counter. A pulse width counter, a pulse width decoder that selects and outputs only a signal corresponding to the count value sent from the pulse width counter, and a pulse width latch that outputs the signal of the pulse width decoder by latching it into a clock signal, A pulse cycle counter that counts the carry signal from the pulse width counter and sends the count value to the pulse cycle decoder, and a pulse cycle decoder that selects and outputs only the signal corresponding to the count value sent from the pulse cycle counter. , The signal of the pulse period decoder is latched to the clock signal and sent out A selector that selects an appropriate signal from the signals output from the pulse width latch and the pulse period latch based on the pulse period latch and the pulse width data from the register, and the ON / OFF of the antenna module is controlled by the signal from the selector. JK that generates a signal
A flip-flop, a one-shot circuit that generates a pulse according to a pulse width changing signal, an AND gate that performs an AND of the output signal of the one shot circuit, the logic of an appropriate signal output from the pulse width latch, and the pulse period latch, A transmission pulse control circuit characterized in that the output of the AND gate is connected to the reset terminal of the JK flip-flop.