JPH0593774A - Amplifier gate drive control circuit - Google Patents

Abstract

PURPOSE:To obtain an amplifier gate drive control circuit which can prevent a gate drive signal from staying on when a transmission pulse width data is changed and a pulse width is updated and noise from being included in a receiver part. CONSTITUTION:A pulse width modification signal is passed through an one-shot circuit 16. AND operation is performed between a pulse period signal which is output from a latch and one part of a pulse width signal, and then a gate drive signal is reset once, thus enabling the gate drive signal to be output. When the pulse width is changed according to change in the pulse width, data can be output at a normal timing after the gate drive signal is reset once and the pulse width is changed, thus preventing noise from being included in a receiver part etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for constructing an amplifier gate drive control circuit for radar.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a configuration of a conventional amplifier gate drive control circuit section. In the figure, 1 is a bus transceiver which sends the transmission pulse width data from the signal processor to the register by a write latch, and 2 is a latch for the transmission pulse width data from the bus transceiver to the pulse width counter by the pulse width change trigger. Register 3, the pulse width counter that outputs the data from the register and starts counting when the load signal is input, while outputting the carry signal to its own load signal and pulse period counter,
4 is a pulse width decoder for outputting a code signal corresponding to the count value output from 3, 5 is a pulse width latch for latching the input signal from 4 to the clock signal and outputting, 6 is a carry signal of 3 Pulse cycle counter, 7 is a pulse cycle decoder that outputs a signal of a code corresponding to the count value output from 6, 8 is a pulse cycle latch that latches the input signal from 7 and outputs it as a clock signal, and 9 is 5 , A gate generator that determines the rise and fall of the gate drive signal by an appropriate signal among the signals output from 8 and 10 determines the timing of the gate drive signal by the output signal of 9 and amplifies an appropriate control signal. JK flip-flop output to the drive circuit, 11 is a pulse modulation signal generating pulse modulation signal by 3 and 6 signals Section, 12 is an oscillation circuit, 13 is an amplifier, 14 is a PIN switch that performs pulse modulation of the transmission wave by the signal of 11, and 15 is an amplifier drive that amplifies the transmission wave by the signal output from 10 and sends it to the antenna section Circuit.

Next, the operation will be described. The transmit pulse width data input from the signal processor is inverted by the bus transceiver by the write latch and output to the register 2. The signal input to the register 2 is sent to the pulse width counter 3 when a pulse width changing trigger is applied. The pulse width counter 3 receives the pulse width data, starts counting for each clock, and sends the count value to the pulse width decoder 4. The pulse width decoder 4 selects a signal corresponding to the input count value and sends the signal to the pulse width latch 5. The pulse width latch 5 latches the signal from the pulse width decoder 4 into the clock signal and sends a part of it to the gate generator 9. On the other hand, the pulse cycle counter 6, the pulse cycle decoder 7, and the pulse cycle latch 8 operate in the same manner as in 3, 4, and 5, but the pulse cycle counter 6 counts the carry signal of the pulse width counter 3. The gate generator 9 which receives the signals of the pulse width latch 5 and the pulse period latch 8 as described above sends the signals which are the rising edge and the falling edge of the gate drive signal to the JK flip-flop. The JK flip-flop outputs a gate drive signal at an appropriate timing by this signal, determines the ON / OFF timing of the amplifier drive circuit in the exciter, and outputs an appropriate control signal according to the pulse width. On the other hand, the pulse-modulated signal output from the pulse-modulated-signal generator 11 upon receiving the data of the pulse width counter 3 and the pulse period counter 6 is PI
The N switch 14 is controlled to determine the transmission pulse width. The signal output from the original oscillation circuit 12 and amplified by the amplifier 13 is chopped by the PIN switch 14 by the pulse modulation signal, then amplified by the amplifier drive circuit 15 and sent to the antenna section.

[0004]

The conventional amplifier gate drive control circuit is configured as described above, and when the pulse width changing signal is input while the gate drive signal is ON, the gate drive signal is turned ON. The condition may last long. As described above, if the gate drive signal is kept on for a long time when not transmitting, the amplifier drive circuit is turned on even when not transmitting, and noise is likely to be put on the receiver. ..

The present invention has been made to solve the above problems, and when the pulse width change signal is output, the gate drive signal is appropriately reset and controlled so that the gate drive signal is in the ON state. The purpose is to prevent it from continuing to become.

[0006]

An amplifier gate drive control circuit according to the present invention passes a pulse change signal through a one-shot circuit, outputs a pulse of an appropriate length only when the pulse width change signal is output, and outputs the pulse. And a signal of appropriate timing from the pulse width latch 5 and the pulse period latch 8 are multiplied, and the gate drive signal is reset immediately after the transmission pulse is output.

[0007]

The amplifier gate drive control circuit according to the present invention resets the gate drive signal at an appropriate timing only when the pulse width change signal is input, and the pulse at the time when the pulse width change signal is input can be normally transmitted. To control. This makes it possible to prevent the gate drive signal from being kept in the ON state for a long time.

[0008]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to FIG.
In FIG. 1, 1 to 15 are the same as the above-mentioned conventional device. Reference numeral 16 is a one-shot circuit, and 17 is an AND gate.

Next, the operation will be described. 1 to 1 in FIG.
Up to 5, the operation is similar to that of the conventional circuit. The pulse width changing signal is input to the register 2 and the one shot circuit 16 at the same time. The output is a pulse as shown in FIG. On the other hand, the pulse width counter 3 and the pulse cycle counter 6 count at the timing shown in FIG.
At this time, the output signal of the one-shot circuit is ANDed with a part of the signals of the pulse width counter and the pulse cycle counter (see FIG. 2D) and input to the reset signal of the JK flip-flop. As a result, the pulse width changing signal is output and the gate drive signal is reset immediately after the transmission pulse is output. (See Figure 2 (e))

[0010]

Since the present invention is configured as described above, when the pulse width is updated by the pulse width changing signal, the gate drive signal is reset once and the gate drive signal is turned on. To prevent it from continuing
It is possible to prevent noise from being applied to the receiver during reception.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an amplifier gate drive control circuit according to a first embodiment of the present invention.

FIG. 2 is a pulse modulation signal, pulse period counter, pulse width counter, one-shot circuit according to the first embodiment of the present invention,
It is a figure which shows an example of the timing of a reset signal and a gate drive signal.

FIG. 3 is a diagram showing a configuration of a conventional amplifier gate drive control circuit.

FIG. 4 is a diagram showing an example of timings of a pulse modulation signal and a gate drive signal of a conventional device.

[Explanation of symbols]

 1 Bus Transceiver 2 Register 3 Pulse Width Counter 4 Pulse Width Decoder 5 Pulse Width Latch 6 Pulse Cycle Counter 7 Pulse Cycle Decoder 8 Pulse Cycle Latch 9 Gate Generator 10 JK Flip-Flop 11 Pulse Modulation Signal Generator 12 Source Circuit 13 Amplifier 14 PIN switch 15 Amplifier drive circuit 16 One-shot circuit 17 AND gate

Claims (1)

[Claims] 1. A bus transceiver for reading data from a signal processor while latching the data by a write latch,
The register that latches the input data by the pulse width change signal and sends the signal, counts the data from the register as the initial value, sends the count value to the decoder, and sends the carry signal to its own load signal and pulse period counter. A pulse width counter, a pulse width decoder that selects and outputs only the signal corresponding to the count value sent from the pulse width counter, a pulse width latch that outputs the signal of the pulse width decoder by latching it into a clock signal, and a pulse The pulse cycle counter that counts the carry signal from the width counter and sends the count value to the pulse cycle decoder, the pulse cycle decoder that selects and outputs only the signal corresponding to the count value sent from the pulse cycle counter, and the pulse cycle A pulse that sends the decoder signal by latching it with the clock signal. And period latch, pulse width latch,
A gate generator that determines the rise and fall of the pulse of the gate drive signal based on the output signal of the pulse cycle latch, and a JK flip-flop that generates a gate drive signal that controls ON / OFF of the amplifier drive circuit,
A one-shot circuit that generates a pulse by a pulse-width changing signal, an AND gate that ANDs the output signal of the one-shot circuit with the logic of an appropriate signal output from the pulse width latch and the pulse period latch, and the AND gate output An amplifier gate drive control circuit characterized by being connected to the reset terminal of the JK flip-flop.