JPH0557751B2 - - Google Patents

Info

Publication number
JPH0557751B2
JPH0557751B2 JP63279356A JP27935688A JPH0557751B2 JP H0557751 B2 JPH0557751 B2 JP H0557751B2 JP 63279356 A JP63279356 A JP 63279356A JP 27935688 A JP27935688 A JP 27935688A JP H0557751 B2 JPH0557751 B2 JP H0557751B2
Authority
JP
Japan
Prior art keywords
copper foil
inner layer
linear expansion
copper
expansion coefficient
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63279356A
Other languages
Japanese (ja)
Other versions
JPH02126698A (en
Inventor
Masaki Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP27935688A priority Critical patent/JPH02126698A/en
Publication of JPH02126698A publication Critical patent/JPH02126698A/en
Publication of JPH0557751B2 publication Critical patent/JPH0557751B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は内層用回路板とプリプレグ及び最外層
として銅箔を用いて加熱・加圧しシワや銅箔切れ
がない内層回路入銅張積層板を製造する方法に関
するものである。 (従来技術) 従来内層回路入りの多層銅張積層板を製造する
場合、加熱・加圧時に使用する当て板としての鏡
面板には時に注意はなされておらず、通常は用い
る銅箔の線膨張係数を1としたとき、鏡面板の線
膨張係数の比率が0.6〜0.7のものが用いられてい
る。 又用いられる銅箔においてはその厚みが18μm
のものが主流であり、これらの構成で通常の鏡面
板を用いて加熱・加圧し内層回路入銅張積層板を
製造すると最外面の銅箔にシワが多発し歩留まり
が低下してしまうという問題点があつた。 (発明が解決しようとする課題) 本発明の目的とするところは内層回路入銅張積
層板を製造するにあたつて、加熱・加圧時の寸法
変化及び寸法歪等の諸特性を劣化させることな
く、最外面の銅箔にシワの発生や銅箔切れがな
く、反りや寸法変化の少ない内層回路入りの多層
銅張積層板を製造する方法を提供するにある。 (課題を解決するための手段) 本発明は内層回路入りの多層銅張積層板を製造
する方法において、加熱・加圧時に使用する当て
板としての鏡面板の線膨張係数と用いる銅箔の線
膨張係数を特定することによつて最外面の銅箔に
シワの発生のない内層回路入銅張積層板を製造す
ることにあり、銅箔の線膨張係数を1としたとき
に0.8〜1.5の範囲にある線膨張係数の鏡面板を用
いることにある。 (作用) 本発明において用いる鏡面板としては、使用す
る銅箔の線膨張係数を1としたときに鏡面板の線
膨張係数が0.8〜1.5の範囲にあるものをとくに選
択して使用するにある。 鏡面板の線膨張係数の比率が0.8以下のものを
用いた場合、加熱・加圧中のプリプレグの樹脂流
動域において、銅箔の線膨張係数が鏡面板より大
きいために内層回路板の回路形成によつて生じた
凹部に銅箔の熱時の歪が残留しシワを発生させる
原因となる。 又鏡面板の線膨張係数の比率が1.5以上のもの
を用いた場合、加熱・加圧中のプリプレグの樹脂
流動域において、銅箔の線膨張係数が鏡面板のそ
れより小さいために鏡面板に銅箔が引つ張られる
ことにより、発生した引張応力で銅箔切れが発生
し易くなる。 更に銅箔のシワや切れが発生しなくても銅箔と
鏡面板との線膨張係数の比率が大きい場合は樹脂
が硬化した後に銅箔の歪が残つてしまい、できあ
がつた内層回路入銅張積層板に反りや寸法変化が
大きくなるという悪影響を与える。 このため銅箔の線膨張係数に対する鏡面板の線
膨張係数の比率は0.8〜1.5の範囲のものが好まし
いが、さらにこの比率が1.0〜1.3の範囲にあるも
のが望ましい。 尚、用いる銅箔の厚みとしては25μm以下のも
のにシワの発生防止や銅箔切れ防止に対して非常
に優れた効果を示す。 (実施例) 実施例 1 サイズ0.5×0.5m、内層回路板厚さ0.2mm(銅箔
厚さ70μm)2枚の間に0.18mm厚のプリプレグ2
枚を配し、更にこの内層回路板の両側に0.1mm厚
のプリプレグ3枚を介して18μm厚の銅箔を配し
た構成とした。 これを鏡面板として線膨張係数17.3ppm(銅箔
の線膨張係数に対する比率1.07)、硬度430HV、
厚さ1.8mmのSUS板を用い、これらを8組積み重
ねプレスにセツトした。 セツト後、熱盤温度を直ちに190℃まで上昇さ
せ、同時に製品圧力を40Kgf/cm2までかけて100
分間加熱した後冷却を40分間行い内層回路入銅張
積層板を得た。 結果を第1表に示す。 実施例 2 実施例1と同様の構成で、鏡面板を線膨張係数
が14.6ppm(銅箔の線膨張係数に対する比率0.9)
のSUS板に変えた以外は実施例と同様の条件で
内層回路入銅張積層板を得た。 結果を第1表に示す。 比較例 1 実施例1と同様の構成で、鏡面板を線膨張係数
が11.6ppm(銅箔の線膨張係数に対する比率0.7)
のSUS板に変えた以外は実施例と同様の条件で
内層回路入銅張積層板を得た。 結果を第1表に示す。 比較例 2 実施例1と同様の構成で、鏡面板を線膨張係数
が24ppm(銅箔の線膨張係数に対する比率1.5)の
アルミ板に変えた以外は実施例と同様の条件で内
層回路入銅張積層板を得た。 結果を第1表に示す。 (発明の効果) 本発明の方法によれば表面層の銅箔のシワの発
生率が従来では10〜15%であつたものが0.5%以
下に減少し、高い歩留まりが得られるとともにプ
リント板加工及びアセンブリー工程で問題となる
反り、寸法変化率とも良好な方向にあり、さらに
その他諸特性が劣化することのなく、内層回路入
銅張積層板を製造する方法として最適なものであ
つた。 【表】
Detailed Description of the Invention (Field of Industrial Application) The present invention is a copper-clad laminate with an inner layer circuit that is heated and pressurized using a circuit board for the inner layer, a prepreg, and a copper foil as the outermost layer so that there are no wrinkles or breaks in the copper foil. The present invention relates to a method for manufacturing. (Prior art) Conventionally, when manufacturing multilayer copper-clad laminates with inner layer circuits, no attention was paid to the mirror plate used as a backing plate during heating and pressurization, and the linear expansion of the copper foil used usually When the coefficient is set to 1, a mirror plate with a linear expansion coefficient ratio of 0.6 to 0.7 is used. Also, the thickness of the copper foil used is 18μm.
However, when producing copper-clad laminates with inner layer circuits by heating and pressurizing ordinary mirror-finished plates with these configurations, there is a problem that the outermost copper foil often wrinkles and the yield decreases. The point was hot. (Problems to be Solved by the Invention) The purpose of the present invention is to reduce various properties such as dimensional changes and dimensional distortions during heating and pressurization when manufacturing copper-clad laminates with inner layer circuits. To provide a method for manufacturing a multilayer copper-clad laminate with an inner layer circuit, which is free from wrinkles or copper foil breakage on the outermost copper foil, and has little warpage or dimensional change. (Means for Solving the Problems) The present invention relates to a method for manufacturing a multilayer copper-clad laminate with an inner layer circuit, and the present invention relates to the linear expansion coefficient of a mirror plate used as a backing plate used during heating and pressurization, and the wires of copper foil used. By specifying the coefficient of expansion, we can manufacture copper-clad laminates with inner layer circuits that do not cause wrinkles on the outermost copper foil. The purpose is to use a mirror plate with a coefficient of linear expansion within this range. (Function) As the mirror plate used in the present invention, a mirror plate whose linear expansion coefficient is in the range of 0.8 to 1.5, when the linear expansion coefficient of the copper foil used is 1, is particularly selected and used. . If a mirror plate with a ratio of linear expansion coefficient of 0.8 or less is used, the linear expansion coefficient of the copper foil is larger than that of the mirror plate in the resin flow region of the prepreg during heating and pressurization, causing circuit formation on the inner layer circuit board. The distortion of the copper foil during heating remains in the recesses caused by this, causing wrinkles. In addition, if a mirror plate with a linear expansion coefficient ratio of 1.5 or more is used, the coefficient of linear expansion of the copper foil is smaller than that of the mirror plate in the resin flow area of the prepreg during heating and pressurization. When the copper foil is stretched, the generated tensile stress tends to cause the copper foil to break. Furthermore, even if the copper foil does not wrinkle or break, if the ratio of linear expansion coefficients between the copper foil and the mirror plate is large, distortion of the copper foil will remain after the resin hardens, causing damage to the resulting inner layer circuit board. This adversely affects copper-clad laminates by increasing warping and dimensional changes. Therefore, the ratio of the coefficient of linear expansion of the mirror plate to the coefficient of linear expansion of the copper foil is preferably in the range of 0.8 to 1.5, and more preferably in the range of 1.0 to 1.3. It should be noted that when the thickness of the copper foil used is 25 μm or less, it is extremely effective in preventing wrinkles and breaking the copper foil. (Example) Example 1 Size 0.5 x 0.5 m, inner layer circuit board thickness 0.2 mm (copper foil thickness 70 μm) 0.18 mm thick prepreg 2 between two sheets
Furthermore, copper foil with a thickness of 18 μm was placed on both sides of this inner layer circuit board via three sheets of prepreg with a thickness of 0.1 mm. This is used as a mirror plate with a linear expansion coefficient of 17.3ppm (ratio of 1.07 to the linear expansion coefficient of copper foil), hardness of 430HV,
Eight sets of SUS plates with a thickness of 1.8 mm were stacked and set in a press. After setting, the temperature of the hotplate is immediately raised to 190℃, and at the same time, the product pressure is applied to 40Kgf/ cm2 .
After heating for a minute, cooling was performed for 40 minutes to obtain a copper-clad laminate with an inner layer circuit. The results are shown in Table 1. Example 2 A mirror plate with the same configuration as Example 1 with a linear expansion coefficient of 14.6 ppm (ratio to the linear expansion coefficient of copper foil: 0.9)
A copper-clad laminate with an inner layer circuit was obtained under the same conditions as in the example except that the SUS board was used. The results are shown in Table 1. Comparative Example 1 Same configuration as Example 1, with a mirror plate having a linear expansion coefficient of 11.6 ppm (ratio to the linear expansion coefficient of copper foil: 0.7)
A copper-clad laminate with an inner layer circuit was obtained under the same conditions as in the example except that the SUS board was used. The results are shown in Table 1. Comparative Example 2 The inner layer circuit was filled with copper under the same conditions as in Example 2, with the same configuration as Example 1, except that the mirror plate was replaced with an aluminum plate with a linear expansion coefficient of 24 ppm (ratio of 1.5 to the linear expansion coefficient of copper foil). A stretched laminate was obtained. The results are shown in Table 1. (Effects of the Invention) According to the method of the present invention, the incidence of wrinkles in the copper foil on the surface layer is reduced from 10 to 15% in the past to 0.5% or less, and a high yield can be obtained and printed board processing is possible. Both warping and dimensional change rate, which are problems in the assembly process, were in a favorable direction, and other properties did not deteriorate, making it the most suitable method for manufacturing copper-clad laminates with inner layer circuits. 【table】

Claims (1)

【特許請求の範囲】[Claims] 1 内層用回路板の両面にプリプレグを介し、該
プリプレグの両面又は片面に25μm以下の銅箔を
配し加熱・加圧し内層回路入銅張積層板を製造す
る方法において、この両面又は片面に用いる銅箔
と加熱・加圧工程で用いる鏡面板との線膨張係数
の比が、銅箔の線膨張係数を1としたとき、該鏡
面板の線膨張係数が0.8〜1.5の範囲にある鏡面板
を用いて加熱・加圧することにより内層回路入銅
張積層板を製造する方法。
1. Used on both sides or one side of an inner layer circuit board in a method of manufacturing a copper-clad laminate with an inner layer circuit by placing a copper foil of 25 μm or less on both sides or one side of the prepreg and heating and pressurizing the prepreg on both sides of the inner layer circuit board. A specular plate in which the linear expansion coefficient ratio of the copper foil and the specular plate used in the heating/pressing process is in the range of 0.8 to 1.5 when the linear expansion coefficient of the copper foil is 1. A method of manufacturing copper-clad laminates with inner layer circuits by heating and pressurizing them using
JP27935688A 1988-11-07 1988-11-07 Manufacture of copper-clad laminate containing inner layer circuit Granted JPH02126698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27935688A JPH02126698A (en) 1988-11-07 1988-11-07 Manufacture of copper-clad laminate containing inner layer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27935688A JPH02126698A (en) 1988-11-07 1988-11-07 Manufacture of copper-clad laminate containing inner layer circuit

Publications (2)

Publication Number Publication Date
JPH02126698A JPH02126698A (en) 1990-05-15
JPH0557751B2 true JPH0557751B2 (en) 1993-08-24

Family

ID=17610033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27935688A Granted JPH02126698A (en) 1988-11-07 1988-11-07 Manufacture of copper-clad laminate containing inner layer circuit

Country Status (1)

Country Link
JP (1) JPH02126698A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6086206B2 (en) * 2012-02-28 2017-03-01 住友化学株式会社 Metal base substrate and manufacturing method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5830195A (en) * 1981-08-18 1983-02-22 東芝ケミカル株式会社 Method of forming laminated board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5830195A (en) * 1981-08-18 1983-02-22 東芝ケミカル株式会社 Method of forming laminated board

Also Published As

Publication number Publication date
JPH02126698A (en) 1990-05-15

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