JPH0556300A - Synchronizing signal generating circuit - Google Patents

Abstract

PURPOSE:To cancel the vertical synchronization disturbance at the time of switching from a memory output mode to a non-memory output mode. CONSTITUTION:A vertical synchronization generating circuit 62 is equipped with a counter to count the output of a PLL circuit 60, and a vertical synchronizing signal Vsync and a field identifying signal are outputted by a counted value (vertical output counted value) equivalent to the number of the horizontal scanning lines of one screen. A vertical synchronization control circuit 66 has an input video signal and at the non-memory output mode, increases and decreases the vertical output counted value in accordance with the phase error by a phase comparing circuit 54 and except it, sets it to the fixed value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal generating circuit for generating a reference signal such as a horizontal and vertical synchronizing signal of a video signal.

[0002]

2. Description of the Related Art In a circuit for processing a video signal, various image quality improving processes and special effects can be easily realized by digital signal processing. For example, using one frame (or one field) image memory, noise reduction,
It performs time axis correction, motion compensation, etc., and converts moving images into still images and outputs them.

FIG. 2 shows a general circuit configuration block diagram of an image processing circuit having such an image memory. In such a circuit, a mode in which the input video signal of the input terminal 10 is output from the output terminal 22 via the memory 16 is called a memory output mode, and is output from the output terminal 22 without passing through the memory 16. The mode will be called a non-memory output mode.

The video signal input from the input terminal 10 is
It is applied to the preprocessing circuit 12 and the synchronization signal generation circuit (SSG) 24. The preprocessing circuit 12 is, for example, a circuit that converts a composite signal into a luminance / color difference signal or an RGB signal.

The synchronizing signal generating circuit 24 follows the output mode signal, and in the non-memory output mode, the preprocessing circuit 12, A
/ D converter 14, D / A converter 18, and post-processing circuit 20
To the clock signal and the horizontal / vertical synchronizing signal formed from the horizontal / vertical synchronizing signal included in the video signal of the input terminal 10, and in the memory output mode, the preprocessing circuit 12, A
A clock generated from the horizontal and vertical synchronizing signals included in the video signal from the input terminal 10 is supplied for writing to the D / D converter 14 and the memory 16, and is used for reading from the memory 16 and the D / A converter 18 and the rear side. The processing circuit 20 is supplied with the clock and horizontal / vertical synchronization signals output from the internal free-running clock generation circuit.

The A / D converter 14 converts the output of the preprocessing circuit 12 into a digital signal. The output of the A / D converter 14 is applied to the memory 16 and the D / A converter 18,
In the memory output mode, the memory 16 is the A / D converter 14
Is stored according to the write clock from the sync signal generation circuit 24, and is read according to the read clock from the sync signal generation circuit 24. The data read from the memory 16 is applied to the D / A converter 18.

The D / A converter 18 converts the output data of the A / D converter 14 in the non-memory output mode and the data read from the memory 16 in the memory output mode into an analog signal. The post-processing circuit 20 converts the output of the D / A converter 18 into a signal form for monitor output (for example, NTSC composite signal, luminance / color difference separation signal, RGB signal, etc.), and outputs the result to the output terminal 22.

[0008]

In the above circuit, the memory 1 is used.
In the memory output mode via 6, when reading from the memory 16, the synchronization signal generation circuit 24 supplies the clock generated from the free-running clock generation circuit to the memory 16,
It is supplied to the D / A converter 18 and the post-processing circuit 20. Therefore, the output video signal of the output terminal 22 is not synchronized with the input video signal of the input terminal 10. In other words, when a monitor device is connected to the output terminal 22, when the output mode is switched, the display of the monitor device is disturbed in synchronization and becomes unsightly.

Further, even if the vertical synchronizing signal for output in the memory output mode is synchronized with the vertical synchronizing signal of the video signal of the input terminal 10, if the odd / even fields are not adjusted, the skew may occur when the output mode is switched. Will occur.

An object of the present invention is to provide a synchronizing signal generating circuit which solves these problems.

[0011]

A synchronizing signal generating circuit according to the present invention is a synchronizing signal generating circuit for generating a synchronizing signal in a memory output mode and a non-memory output mode in an image processing circuit having a memory. The generation interval of the sync signal can be changed with the horizontal frequency of one field as a basic unit. Further, the generation interval of the horizontal synchronizing signal can be freely changed according to the clock of the predetermined frequency.

[0012]

By the above means, even when the memory output mode is switched to the non-memory output mode or vice versa, the output horizontal synchronizing signal and vertical synchronizing signal have the same phase before and after the switching. Therefore, the output monitor image is not disturbed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The input terminal 30 includes, for example, the input terminal 1 of FIG.
A video signal from 0 is input, and an output mode signal designating an output mode is input to the input terminal 32. The output mode signal is L for the memory output mode and H for the non-memory output mode.

The sync separation circuit 34 separates the composite sync signal from the video signal input from the input terminal 30, and applies the separated composite sync signal to the vertical sync separation circuit 36, the horizontal sync separation circuit 38 and the input detection circuit 40. The vertical sync separation circuit 36 separates and outputs the vertical sync signal, the horizontal sync separation circuit 38 separates and outputs the horizontal sync signal, and the input detection circuit 40 determines the input terminal 3 from the time interval of the sync pulse of the composite sync signal.
Presence or absence of 0 video signal is detected. Input detection circuit 40
Outputs H when there is a video input, and outputs L when there is no video input.

Further, the field discriminating circuit 42 outputs from the outputs of the vertical sync separating circuit 36 and the horizontal sync separating circuit 38,
It is determined whether the video signal at the input terminal 30 is the first field or the second field.

The AND circuit 44 takes the logical product of the detection output of the input detection circuit 40 and the mode signal from the input terminal 32. That is, the AND circuit 44, when the input terminal 30 has a video input and the mode signal is a non-memory output,
It outputs H, and otherwise outputs L. Inverter 4
6 inverts the mode signal of the input terminal 32, and the AND circuit 4
8 is a detection output of the input detection circuit 40 and an inverter 46.
AND with the output of. The AND circuit 48 outputs H when the input terminal 30 has a video input and the mode signal is a memory output, and otherwise outputs L.

The horizontal sync generation circuit 50 has a counter (horizontal counter) for counting an internal clock, and outputs a horizontal sync signal Hsync with a count value corresponding to one horizontal period (hereinafter referred to as horizontal output count value). The output of the horizontal sync separation circuit 38 is connected to the reset terminal of (the internal counter of) the horizontal sync generation circuit 50 via the switch 52, and is also applied to the phase comparison circuit 54. Switch 5
2 opens when the output of the AND circuit 44 is L and closes when the output is H. The phase comparison circuit 54 is a horizontal sync separation circuit 38.
Output (horizontal sync signal of input video signal) and the output of the horizontal sync generation circuit 50 (horizontal sync signal of internal reference) are compared in phase to output a phase error signal.

The horizontal synchronization control circuit 56 is an AND circuit 48.
When the output of H is H, the horizontal output count value of the horizontal synchronization generating circuit 50 is increased or decreased within a predetermined range in accordance with the output of the phase comparison circuit 54 (phase error). .. The horizontal synchronization control circuit 56 also
When the output of the AND circuit 48 is L, the phase comparison circuit 54
The horizontal output count value of the horizontal synchronization generating circuit 50 is held at a standard fixed value regardless of the output (phase error) of the.

The switch 58 selects the output of the horizontal sync separation circuit 38 (the horizontal sync signal of the input video signal) or the output of the horizontal sync generation circuit 50 (the internal reference horizontal sync signal), and the selected signal is the PLL circuit. 60. The switch 58 is controlled by the output of the AND circuit 44, and when the output of the AND circuit 44 is H, the horizontal sync separation circuit 3
8 is selected, and when the output of the AND circuit 44 is L, the output of the horizontal sync generation circuit 50 is selected.

The PLL circuit 60 generates clocks of various frequencies that are phase-locked with the selection signal from the switch 58. The vertical synchronization generation circuit 62 outputs the clock output from the PLL circuit 60 (for example, the clock of the horizontal synchronization frequency).
A counter (vertical counter) for counting the vertical sync signal Vsync and the field identification with a count value (hereinafter referred to as a vertical output count value) corresponding to one vertical period (for example, the number of horizontal scanning lines in one screen). Output a signal.
The phase comparison circuit 64 compares the field discrimination signal output from the field discrimination circuit 42 with the field discrimination signal output from the vertical synchronization generation circuit 62, and outputs a signal indicating a field phase difference and a vertical phase difference. ..

The vertical synchronization control circuit 66 includes an AND circuit 48.
When the output of L is L, the vertical output count value of the vertical synchronization generating circuit 62 is set to a predetermined standard value regardless of the output of the phase comparison circuit 54, and when the output of the AND circuit 48 is H, the output from the phase comparison circuit 54 is output. The vertical output count value of the vertical synchronization generating circuit 62 is increased or decreased according to the phase error signal.

An output horizontal synchronizing signal is output from the output terminal 68, an output vertical synchronizing signal is output from the output terminal 70, and a clock for the D / A converter 18 and the like is output from the output terminal 72. It

Next, the operation of FIG. 1 will be described.

First, the operation in the non-memory output mode will be described. The mode signal at the input terminal 32 is H. The sync separation circuit 34 separates the composite sync signal from the video signal at the input terminal 30, the vertical sync separation circuit 36 separates the vertical sync signal, the horizontal sync separation circuit 38 separates the horizontal sync signal, and the input detection circuit 40. , The presence / absence of a video signal input to the input terminal 30 is detected. That is, when a video signal is input to the input terminal 30, the output of the input detection circuit 40 becomes H and the output of the AND circuit 44 becomes H from L, whereby the switch 52 is closed and the switch 58 is horizontally synchronized. Separation circuit 3
8 outputs are selected. The output of the AND circuit 48 is L
Therefore, the horizontal synchronization control circuit 56 sets the horizontal output count value of the horizontal synchronization generation circuit 50 to a standard fixed value regardless of the output of the phase comparison circuit 54.

When the switch 58 selects the output of the horizontal sync separation circuit 38, the PLL circuit 60 generates a clock synchronized with the video signal input to the input terminal 30, and the vertical sync generation circuit 62 outputs the clock. The vertical sync signal Vsync and the field identification signal are generated in synchronism with the video signal input to the.

The field discriminating circuit 42 discriminates the first field or the second field from the outputs of the vertical sync separating circuit 36 and the horizontal sync separating circuit 38, and the phase comparing circuit 64.
Detects the field phase difference and the vertical phase difference by comparing the phase of the field identification signal output from the vertical synchronization generation circuit 62 with the field identification signal output from the field determination circuit 42. Since the output of the AND circuit 44 is H, the vertical synchronization control circuit 66 increases or decreases the vertical output count value of the vertical synchronization generation circuit 62 according to the output of the phase comparison circuit 64 so that the phase error decreases. As a result, the output of the vertical sync generation circuit 62 is synchronized with the video signal input to the input terminal 30.

On the other hand, for the horizontal sync signal Hsync, since the switch 52 is closed, the horizontal sync signal separated by the horizontal sync separation circuit 38 is applied to the reset terminal of the horizontal sync generation circuit 50. In the horizontal synchronization control circuit 56, since the output of the AND circuit 48 is L,
Regardless of the output of the phase comparison circuit 54, the horizontal output count value of the horizontal synchronization generation circuit 50 is fixed to a predetermined standard value.
As a result, the horizontal synchronization generating circuit 50 causes the horizontal synchronization signal Hsync synchronized with the video signal input to the input terminal 30.
Is output.

When the video signal is no longer input to the input terminal 30, the output of the input detection circuit 40 becomes L and the output of the AND circuit 44 becomes L. As a result, the switch 58 selects the output of the horizontal sync signal generating circuit 50, and the vertical sync control circuit 66 sets the vertical output count value of the vertical sync generating circuit 62 to a predetermined standard value. The vertical synchronization generation circuit 62 outputs the horizontal synchronization signal Hsync output from the horizontal synchronization generation circuit 50.
And outputs a vertical synchronization signal Vsync synchronized with.

Next, assume that the output mode is switched from the non-memory output mode to the memory output mode. The mode signal changes from H to L, the output of the AND circuit 44 changes to L regardless of the video signal input to the input terminal 30,
The output of the AND circuit 48 becomes H when the video signal is input to the input terminal 30.

Since the output of the AND circuit 44 becomes L, the switch 58 selects the output of the horizontal synchronization generating circuit 50 and the switch 52 is opened. When the switch 52 is opened, the horizontal sync generation circuit 50 is not reset externally, but since it was reset externally in the non-memory output mode, the phases are matched before and after switching to the memory output mode. In the state where the video signal is input to the input terminal 30, the output of the AND circuit 48 is H, and the horizontal synchronization control circuit 56 responds to the phase error by the phase comparison circuit 54 in the direction in which the error decreases in the horizontal synchronization. Generation circuit 50
Increase or decrease the horizontal output count value of the horizontal sync signal Hsyn
c is made to follow the video signal of the input terminal 30.

Regarding the vertical synchronizing signal, the AND circuit 44
, The vertical synchronization control circuit 66 fixes the vertical output count value of the vertical synchronization generation circuit 62 to a predetermined standard value regardless of the output of the phase comparison circuit 64. As a result, the vertical synchronization signal Vs output from the vertical synchronization generation circuit 62 is output.
sync is synchronized with the horizontal sync signal Hsync generated by the horizontal sync generation circuit 50. The horizontal synchronization signal Hsync
Is synchronized with the video signal of the input terminal 30, the vertical synchronization signal Vsync output from the vertical synchronization generation circuit 62 is output.
Eventually follows the vertical phase of the video signal at the input terminal 30.

Since the vertical synchronizing signal Vsync is also in phase with the video signal of the input terminal 30 in the non-memory output mode, it is in phase before and after the memory output mode is switched.

When the video signal is not input to the input terminal 30, the output of the input detection circuit 40 becomes L and the output of the AND circuit 48 becomes H to L. As a result, the horizontal output count value of the horizontal sync generation circuit 50 and the vertical output count value of the vertical sync generation circuit 62 are fixed to standard values.

When a video signal is input to the input terminal 30 in this state, as described above, the horizontal synchronization control circuit 5
6 increases or decreases the horizontal output count value of the horizontal sync generation circuit 50 to operate the horizontal sync generation circuit 50 in synchronization with the video signal of the input terminal 30. Further, the vertical synchronization generating circuit 62 outputs the horizontal synchronization signal Hsync output from the horizontal synchronization generating circuit 50.
Since the vertical synchronizing signal Vsync is generated in synchronization with the vertical synchronizing signal Vsync, the vertical synchronizing signal Vsync is also synchronized with the video signal of the input terminal 30.

[0036]

As can be easily understood from the above description, according to the present invention, the monitor image is not disturbed even when the output mode is switched from the memory output mode to the non-memory output mode or vice versa. Further, even if the input video signal is lost during monitor output and noise is input, the monitor image is not disturbed.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is a general circuit configuration example of an image processing circuit having a memory.

[Explanation of symbols]

10: Input terminal 12: Pre-processing circuit 14: A / D converter 16: Memory 18: D / A converter 20: Post-processing circuit 22: Output terminal 24: Synchronous signal generation circuit 30,
32: input terminal 34: sync separation circuit 36: vertical sync separation circuit 38: horizontal sync separation circuit 40: input detection circuit 42: field discrimination circuit 44: AND circuit 4
6: Inverter 48: AND circuit 50: Horizontal synchronization generation circuit 52: Switch 54: Phase comparison circuit 56: Horizontal synchronization control circuit 58: Switch 60: PLL circuit
62: Vertical sync generation circuit 64: Phase comparison circuit 66:
Vertical synchronization control circuit 68, 70, 72: output terminal

Claims (2)

[Claims] 1. An image processing circuit having a memory,
A synchronization signal generation circuit for generating a synchronization signal in a memory output mode and a non-memory output mode, wherein the generation interval of the vertical synchronization signal is freely changeable with a horizontal frequency of one field as a basic unit. Generator circuit. 2. An image processing circuit having a memory,
A synchronization signal generation circuit for generating a synchronization signal in a memory output mode and a non-memory output mode, wherein a generation interval of a horizontal synchronization signal is changeable according to a clock of a predetermined frequency. ..