JPH0555751A - Thin film multilayer circuit substrate - Google Patents

Thin film multilayer circuit substrate

Info

Publication number
JPH0555751A
JPH0555751A JP3217479A JP21747991A JPH0555751A JP H0555751 A JPH0555751 A JP H0555751A JP 3217479 A JP3217479 A JP 3217479A JP 21747991 A JP21747991 A JP 21747991A JP H0555751 A JPH0555751 A JP H0555751A
Authority
JP
Japan
Prior art keywords
interlayer insulating
capacitor
dielectric
wiring conductor
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3217479A
Other languages
Japanese (ja)
Inventor
Naoki Suzuki
直樹 鈴木
Atsuo Hori
厚生 堀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3217479A priority Critical patent/JPH0555751A/en
Publication of JPH0555751A publication Critical patent/JPH0555751A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To provide a thin film multilayer circuit substrate which realizes small size and high mounting density and easily changes a capacitance value of capacitor. CONSTITUTION:Interlayer insulating layer 10 and wiring conductor layer 11 having via holes 12 are alternately laminated on an insulated substrate 1 to form a multilayer circuit substrate. At least one capacitor 7, which uses one of interlayer insulating layers 10 as a dielectric material 9 and the wiring conductor layers 11 almost in the same shape as the insulated substrates 1 in both sides as electrodes 8, 8a, is included. Moreover, the interlayer insulating layer which becomes a dielectric material 9 of the capacitor 7 is formed thicker than the other interlayer insulating layers 10 or formed by a material having a higher dielectric constant to acquire a capacitance value of a capacitor.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子機器の小型軽量化
のために用いられる薄膜多層回路基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film multilayer circuit board used for reducing the size and weight of electronic equipment.

【0002】[0002]

【従来の技術】近年、薄膜技術は半導体のみならず高周
波回路用基板、コンピュータ用基板、またはマルチチッ
プモジュール用基板などに応用されている。この薄膜技
術は従来のSMT技術(表面実装技術:プリント基板に
チップ部品を半田付けする技術)にくらべて可能最小線
幅が1/10ほどになるのでより高密度の回路を形成す
ることができる。図2は従来の薄膜回路基板の断面図
で、コンデンサと抵抗を形成した回路を構成している。
図において、1はアルミナ基板(純度99.5%)、2
は配線導体でアルミナ基板1との密着性を良くするため
の下地のCr膜(膜厚50nμm)とその上のCu膜
(膜厚5μm)からなり、スパッタ法または蒸着法によ
って成膜しフォトリソグラフィ法でパターンを形成す
る。3は薄膜コンデンサで電極4と誘電体5からなる。
電極4は配線導体2と同じ材料からなり誘電体5はたと
えばTa25が用いられる。6は抵抗体でNiCr,T
aNなどでなり配線導体2と同じくスパッタ法または蒸
着法によって成膜しフォトリソグラフィ法でパターンを
形成する。
2. Description of the Related Art In recent years, thin film technology has been applied not only to semiconductors but also to substrates for high frequency circuits, substrates for computers, substrates for multichip modules, and the like. Compared with the conventional SMT technology (surface mounting technology: technology for soldering chip components to a printed circuit board), this thin film technology has a minimum possible line width of about 1/10, so that a circuit with higher density can be formed. .. FIG. 2 is a sectional view of a conventional thin film circuit board, which constitutes a circuit in which a capacitor and a resistor are formed.
In the figure, 1 is an alumina substrate (purity 99.5%), 2
Is a wiring conductor composed of a base Cr film (film thickness 50 n μm) for improving the adhesion to the alumina substrate 1 and a Cu film (film thickness 5 μm) thereon, and is formed by a sputtering method or a vapor deposition method and photolithography. Pattern is formed by the method. A thin film capacitor 3 is composed of an electrode 4 and a dielectric 5.
The electrode 4 is made of the same material as the wiring conductor 2 and the dielectric 5 is made of Ta 2 O 5, for example. 6 is a resistor, NiCr, T
The wiring conductor 2 is made of aN or the like and is deposited by a sputtering method or a vapor deposition method to form a pattern by a photolithography method.

【0003】[0003]

【発明が解決しようとする課題】上記のような薄膜回路
基板でコンデンサを作る場合には、電極の面積または電
極にはさまれる絶縁層の膜厚を操作して所要の容量を形
成する。しかしそのようにして作られた回路基板上のい
くつかのコンデンサのうちのひとつの容量を変える必要
が生じた場合、露光マスクの変更など多大の手間を要し
ていた。
When a capacitor is made from the thin film circuit board as described above, the required capacitance is formed by manipulating the area of the electrode or the film thickness of the insulating layer sandwiched between the electrodes. However, when it becomes necessary to change the capacity of one of the several capacitors on the circuit board thus manufactured, it takes a lot of time and labor to change the exposure mask.

【0004】本発明は、上記従来の課題を解決するもの
で、回路基板の小型高密度を実現するとともにコンデン
サ容量の変更が簡単である薄膜多層回路基板を提供する
ことを目的とする。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a thin film multilayer circuit board which realizes a compact and high density circuit board and has a simple change of capacitor capacity.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明の薄膜多層回路基板は、ヴィアホールを有す
る層間絶縁層と配線導体層とを交互に絶縁基板上に多層
積層して構成され、上記層間絶縁層のひとつを誘電体と
しその両側の上記絶縁基板とほぼ同形状の配線導体層を
電極とするコンデンサをすくなくとも1個含んでおり、
かつ上記コンデンサの誘電体となる層間絶縁層は他の層
間絶縁層より膜厚を薄くして、または他の層間絶縁層よ
り誘電率が高い材料で構成してコンデンサ容量を確保し
ている。
In order to achieve the above object, a thin film multilayer circuit board of the present invention is constructed by alternately laminating an interlayer insulating layer having a via hole and a wiring conductor layer on the insulating substrate. And includes at least one capacitor having one of the above-mentioned inter-layer insulation layers as a dielectric and electrodes having wiring conductor layers of substantially the same shape as the above-mentioned insulation substrate on both sides thereof,
In addition, the interlayer insulating layer serving as the dielectric of the capacitor has a smaller film thickness than other interlayer insulating layers or is made of a material having a higher dielectric constant than other interlayer insulating layers to secure the capacitor capacitance.

【0006】[0006]

【作用】上記構成により、コンデンサ容量の変更は、コ
ンデンサの電極を絶縁基板とほぼ同形状の一定に保った
まま層間絶縁層の膜厚または誘電率を調整して簡単に行
なえる。
With the above structure, the capacitance of the capacitor can be easily changed by adjusting the film thickness or the dielectric constant of the interlayer insulating layer while keeping the electrode of the capacitor constant and having substantially the same shape as the insulating substrate.

【0007】[0007]

【実施例】以下、本発明の一実施例を図面を参照しなが
ら説明する。図1は本発明の薄膜多層回路基板の断面図
で、1はアルミナ基板、7は電極8および8aと誘電体
9からなるコンデンサ、10は層間絶縁層、11は配線
導体、12は層間絶縁層10をはさんでいる配線導体1
1を接続するヴィアホールである。以上のように構成さ
れた薄膜多層回路基板の製造は次のようである。まずア
ルミナ基板1上にスパッタ法によりCr膜(膜厚50n
μm)とその上にCu膜(膜厚1μm)を成膜する。次
にフォトリソグラフィ法でパターンを形成し電極8を得
る。本実施例では電極8はアルミナ基板1とほぼ同じ形
状である。次にTa25膜をスパッタ法で200nμm
厚成膜しフォトリソグラフィ法でヴィアホールを含むパ
ターンを形成し誘電体9を形成する。同じように成膜と
フォトリソグラフィ法で電極8aを、短絡を防止するた
めに誘電体9より少し小さい形で形成する。次に光硬化
性のポリイミド樹脂溶液をスピンコート法によって成膜
し、プリキュア(80℃,2H)、マスクを通した露
光,現像,キュア(400℃,30min)によってヴ
ィアホール12の開いたポリイミド膜(20μm)を形
成して層間絶縁層10を得る。ヴィアホール12内へは
Cuを電解または無電解めっきによって埋め込む。さら
に配線導体11と層間絶縁層10とを交互に重ねて薄膜
多層回路を得る。上記構成でコンデンサ容量の変更は、
誘電体9の膜厚または誘電率を調整して簡単に行なえ
る。なお、アルミナ基板1は、ガラスや金属ベース絶縁
基板などでもよい。誘電体9は、SiO2,BaTiO3
などでもよい。層間絶縁層10はSiO2などでもよ
い。また、さらに多層にコンデンサを形成し直列または
並列に接続してもよい。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a thin film multilayer circuit board of the present invention. 1 is an alumina substrate, 7 is a capacitor composed of electrodes 8 and 8a and a dielectric 9, 10 is an interlayer insulating layer, 11 is a wiring conductor, and 12 is an interlayer insulating layer. Wiring conductor 1 sandwiching 10
It is a via hole that connects 1. The manufacture of the thin film multilayer circuit board configured as described above is as follows. First, a Cr film (film thickness 50 n is formed on the alumina substrate 1 by the sputtering method.
μm) and a Cu film (film thickness 1 μm) thereon. Next, a pattern is formed by photolithography to obtain the electrode 8. In this embodiment, the electrode 8 has substantially the same shape as the alumina substrate 1. Next, a Ta 2 O 5 film is formed to a thickness of 200 nm by a sputtering method.
A thick film is formed and a pattern including a via hole is formed by a photolithography method to form a dielectric 9. Similarly, the electrode 8a is formed in a shape slightly smaller than the dielectric 9 in order to prevent a short circuit by film formation and photolithography. Next, a photo-curable polyimide resin solution is formed by a spin coating method, and the polyimide film having the via holes 12 opened by pre-cure (80 ° C., 2H), exposure through a mask, development, and cure (400 ° C., 30 min). (20 μm) is formed to obtain the interlayer insulating layer 10. Cu is embedded in the via hole 12 by electrolytic or electroless plating. Further, the wiring conductors 11 and the interlayer insulating layers 10 are alternately stacked to obtain a thin film multilayer circuit. With the above configuration, changing the capacitor capacity is
It can be easily performed by adjusting the film thickness or the dielectric constant of the dielectric 9. The alumina substrate 1 may be glass or a metal-based insulating substrate. The dielectric 9 is made of SiO 2 , BaTiO 3
And so on. The interlayer insulating layer 10 may be SiO 2 or the like. Also, capacitors may be formed in multiple layers and connected in series or in parallel.

【0008】[0008]

【発明の効果】以上の説明で明らかなように、本発明の
薄膜多層回路基板は、回路基板の小型高密度を実現する
とともにコンデンサ容量の変更が簡単であり、かつ大容
量のコンデンサが作り易い。またコンデンサ容量の変更
は誘電体の膜厚または誘電率を変えて行い、ホトマスク
変更がないので設計変更の対応が敏速にできる。
As is apparent from the above description, the thin film multilayer circuit board of the present invention realizes a small size and high density of the circuit board, the change of the capacitor capacity is easy, and the large capacity capacitor is easy to make. .. Further, the capacitance of the capacitor is changed by changing the film thickness or the dielectric constant of the dielectric, and since the photomask is not changed, the design change can be promptly dealt with.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の薄膜多層回路基板の断面図FIG. 1 is a cross-sectional view of a thin film multilayer circuit board of the present invention.

【図2】従来の薄膜多層回路基板の断面図FIG. 2 is a sectional view of a conventional thin film multilayer circuit board.

【符号の説明】[Explanation of symbols]

1 アルミナ基板(絶縁基板) 7 コンデンサ 8,8a 電極 9 誘電体 10 層間絶縁層 11 配線導体(配線導体層) 12 ヴィアホール 1 Alumina Substrate (Insulation Substrate) 7 Capacitor 8, 8a Electrode 9 Dielectric 10 Interlayer Insulation Layer 11 Wiring Conductor (Wiring Conductor Layer) 12 Via Hole

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 ヴィアホールを有する層間絶縁層と配線
導体層とを交互に絶縁基板上に多層積層して構成され、
上記層間絶縁層のひとつを誘電体としその両側の上記絶
縁基板とほぼ同形状の配線導体層を電極とするコンデン
サをすくなくとも1個含んでおり、かつ上記コンデンサ
の誘電体となる層間絶縁層は他の層間絶縁層より膜厚が
薄い薄膜多層回路基板。
1. An interlayer insulating layer having a via hole and a wiring conductor layer are alternately laminated to form a multilayer structure,
It includes at least one capacitor having one of the above-mentioned interlayer insulating layers as a dielectric and a wiring conductor layer of substantially the same shape as the above-mentioned insulating substrate on both sides thereof as an electrode, and the other interlayer insulating layer serving as a dielectric of the above capacitor is not included. Thin-film multi-layer circuit board that is thinner than the inter-layer insulating layer.
【請求項2】 ヴィアホールを有する層間絶縁層と配線
導体層とを交互に絶縁基板上に多層積層して構成され、
上記層間絶縁層のひとつを誘電体としその両側の上記絶
縁基板とほぼ同形状の配線導体層を電極とするコンデン
サをすくなくとも1個含んでおり、かつ上記コンデンサ
の誘電体となる層間絶縁層は他の層間絶縁層より誘電率
が高い材料で構成されている薄膜多層回路基板。
2. An interlayer insulating layer having a via hole and a wiring conductor layer are alternately laminated in multiple layers on an insulating substrate,
It includes at least one capacitor having one of the above-mentioned interlayer insulating layers as a dielectric and a wiring conductor layer of substantially the same shape as the above-mentioned insulating substrate on both sides thereof as an electrode, and the other interlayer insulating layer serving as a dielectric of the above capacitor is not included. Thin-film multilayer circuit board made of a material having a higher dielectric constant than the interlayer insulating layer of.
JP3217479A 1991-08-28 1991-08-28 Thin film multilayer circuit substrate Pending JPH0555751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3217479A JPH0555751A (en) 1991-08-28 1991-08-28 Thin film multilayer circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3217479A JPH0555751A (en) 1991-08-28 1991-08-28 Thin film multilayer circuit substrate

Publications (1)

Publication Number Publication Date
JPH0555751A true JPH0555751A (en) 1993-03-05

Family

ID=16704879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3217479A Pending JPH0555751A (en) 1991-08-28 1991-08-28 Thin film multilayer circuit substrate

Country Status (1)

Country Link
JP (1) JPH0555751A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214445B1 (en) 1998-12-25 2001-04-10 Ngk Spark Plug Co., Ltd. Printed wiring board, core substrate, and method for fabricating the core substrate
US7224040B2 (en) 2003-11-28 2007-05-29 Gennum Corporation Multi-level thin film capacitor on a ceramic substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214445B1 (en) 1998-12-25 2001-04-10 Ngk Spark Plug Co., Ltd. Printed wiring board, core substrate, and method for fabricating the core substrate
US7224040B2 (en) 2003-11-28 2007-05-29 Gennum Corporation Multi-level thin film capacitor on a ceramic substrate

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