JPH0553925A - Microprogram controller - Google Patents

Abstract

PURPOSE:To avoid a fault in the case of a fixed fault by regenerating a microprogram with fault address information as a use inhibit area and writing the program in a control storage part when the arbitrary word of the control storage part is turned to the fault. CONSTITUTION:A microprogram generating part 5 holds the source program of the microprogram in the state of an assembly language and rewrites a generated object program through an assembly to a control storage part 1. In that case, the fault address from a fault address register 4 is defined as the use inhibit area. Namely, when a read data abnormality detection circuit 2 detects abnormality in the object program stored in the control storage part 1, concerning the relevant address part of the control storage part 1 detecting the abnormality, the microprogram generating part 5 does not use the relevant address part in the case of rewriting the microprogram by defining it as the use inhibit area. Therefore, the microprogram is not written in the part having the fault at the control storage part 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram controller, and more particularly, to fault processing of a control storage unit.

[0002]

2. Description of the Related Art A conventional microprogram controller is
When a failure occurs in the control storage unit, the method of rewriting the microprogram has been adopted.

[0003]

In the conventional method of rewriting a microprogram described above, if the data stored in the control storage unit is temporarily destroyed by a soft error due to cosmic rays or the like. Recovery is possible,
There is a problem that it cannot be avoided if the memory element is a fixed failure.

In view of the above problems, it is an object of the present invention to provide a control device capable of recovering a microprogram even when a memory element has a fixed failure.

[0005]

A microprogram control device according to the present invention comprises a control storage unit composed of a rewritable storage element, an abnormality detection circuit for detecting an abnormality in read data from the control storage unit, and an abnormality detection. When an abnormality is detected in the read data by the circuit, a failure address storage unit that stores the read address of the control storage unit where the abnormality is detected as a failure address and a microprogram to be stored in the control storage unit are generated and written. In the microprogram control device including a microprogram generation unit, the microprogram generation unit holds a source program of the microprogram in an assembly language state, passes through an assembler, and stores the generated object program in the control storage unit. When rewriting, write the fault address It has the function of a failure address the use inhibited area than section.

[0006]

When the abnormality detection circuit detects an abnormality in the object program stored in the control storage unit, the microprogram generation unit determines the use of the microprogram as a prohibited area for the corresponding address portion of the control storage unit where the abnormality is detected. Do not use when writing. Therefore, the microprogram is not written in the defective portion of the control storage unit.

[0007]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the microprogram controller of the present invention.

At initialization of the microprogram controller,
When a failure occurs, the microprogram generated by the microprogram generation unit 5 (hereinafter referred to as the MP generation unit 5) is written in the control storage unit 1. The microprogram is read from the control storage unit 1 by the address register 3 and the operation of the microprogram control device is performed. The read data abnormality detection circuit 2 sends an abnormality detection signal to a failure processing processor (not shown) and the failure address register 4 when an abnormality is detected. Fault address register 4
Holds the address information from the address register 3 according to the abnormality detection signal. The fault processing processor controls stop and restart of the microprogram controller by the abnormality detection signal.

The operation of the MP generator 5 will be described with reference to FIG. Source program holding unit 51 (hereinafter, SP
As an example of the holding unit 51), if the coding is performed as in the flowchart shown in FIG.
If there is no failure in the control storage unit 1, the assembling unit 52 assembles it as shown in the memory map shown in FIG. 2B at the time of initialization, and the object program output unit 53 (hereinafter referred to as the OBJ output unit 53 Note) is written in the control storage unit 1 as an object program. The field indicated by NA on the memory map of FIG. 2B is a field indicating the next address,
It shows the word address of the control storage unit 1 to be executed next. In this example, the instruction “A” is at address 0, the instruction “B” is at address 1, the instruction “C” is at address 2, and the instruction “D” is at address 3.
It is written in the address. When the control storage unit 1 is normal, as shown in the flowchart of FIG. 2A, the instruction “A” → the instruction “B” → the instruction “C” → the instruction “D” are executed in this order. Consider the case where address 2 of 1 fails. When the read data abnormality detection circuit 2 detects an abnormality by reading address 2 from the control storage unit 1, the failure address register 4 holds the address information “2” from the address register 3 and the failure processing processor controls it. The microprogram controller stops operating. Next, in response to a restart instruction from the failure processing processor, the assembler 52 sets the failure address information “2” of the failure address register 4 as a use prohibited area in FIG.
Assemble into the memory map as shown in (d), and
It is passed to the J output unit 53. Whether to assemble as shown in FIG. 2 (c) or as shown in FIG. 2 (d) on the memory map,
Depends on the function of the assembler and the free area on the memory map. When the object program shown in the memory map of FIG. 2C and FIG. 2D is written in the control storage unit 1, the object program shown in the memory map of FIG. Although the arrangement of instructions is different, as shown in the flowchart of FIG.
Instructions are executed in the order of instruction “A” → instruction “B” → instruction “C” → instruction “D”. At this time, in the case of the object program shown in the memory map of FIG. 2C, address 0 → 1
Since the control storage unit 1 is read out in the order of address → 3 address → 4 address, and in the case of the object program shown in the memory map of FIG. 2 (d), 0 address → 1 address → z address → 3 address. The address 2 of the control storage unit 1 is not read, and the failure due to the abnormality detection by the read data abnormality detection circuit 2 does not occur again.

In this way, when an arbitrary word in the control storage unit 1 fails, the failure is avoided by regenerating the microprogram.

[0011]

As described above, according to the present invention, when an arbitrary word in the control storage section fails, the microprogram is regenerated by using the failure address information as the prohibited area,
Since the data is written in the control storage unit, there is an effect that it is possible to avoid a failure when a fixed failure occurs in any word in the control storage unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a micro program control device of the present invention.

FIG. 2A is a flowchart explaining the operation of the embodiment of FIG. (B) is a diagram showing a state of a memory map of the control storage unit before failure processing. (C) is a diagram showing a state of a memory map of the control storage unit showing an example after failure processing. FIG. 9D is a diagram showing a state of the memory map of the control storage unit showing another example after the failure processing.

[Explanation of symbols]

 1 Control Storage Section 2 Read Data Abnormality Detection Circuit 3 Address Register 4 Failure Address Register 5 Micro Program Generation Section (MP Generation Section) 51 Source Program Holding Section (SP Holding Section) 52 Assembling Section 53 Object Program Output Section (OBJ Output Section)

Claims (1)

[Claims] 1. A control storage unit including a rewritable storage element, an abnormality detection circuit for detecting an abnormality in read data of the control storage unit, and an abnormality when the read data is detected by the abnormality detection circuit. In a microprogram control device including a failure address storage unit that stores a read address of the control storage unit in which is detected as a failure address, and a microprogram generation unit that generates and writes a microprogram to be stored in the control storage unit. The microprogram generator holds a source program of the microprogram in an assembly language state,
A microprogram control device having a function of setting a failure address from the failure address storage unit as a use prohibited area when rewriting the generated object program to the control storage unit through an assembler.