JPH0551927B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a magnetic bubble memory control device, and particularly to an output suitable for reading registers in a data controller when a plurality of data controllers are controlled by a magnetic bubble memory controller. It's about batshua.

[Background of the invention]

Generally, a magnetic bubble memory device consists of a magnetic bubble memory device, a direct peripheral circuit that directly sends and receives signals to and from the magnetic bubble memory device, and a magnetic bubble memory control circuit that controls the direct peripheral circuit. It is configured.

FIG. 1 is a block diagram of essential parts showing an example of the configuration of this type of magnetic bubble memory device. In the figure, 1 is a magnetic bubble memory controller (hereinafter referred to as
This BMC 1 exchanges data with a host computer (not shown),
It controls the magnetic bubble memory by discontinuing commands from the host computer. 2 is a data controller (hereinafter referred to as DC), and this
DC2 has a data buffer for transferring data to the magnetic bubble memory, and controls data.
3 is a timing generator (hereinafter referred to as TG), and this TG3 generates the timing necessary for the operation of the magnetic bubble memory. And DC2 and TG3 are controlled by BMC1. 4 is a magnetic bubble memory (hereinafter referred to as "magnetic bubble memory") as a storage unit that operates upon receiving control signals from TG3.
The BM 4 includes a magnetic bubble memory device and direct peripheral circuits such as a coil driver, a sense amplifier, and a pulse driver for a function. And this
Data transfer to BM4 is performed by DC2.

In such a configuration, when BMC1 receives an instruction from the host computer, BMC1
3 and generates the necessary control signals to DC2. On the other hand, the DC2 receives data to be written to the BM4 from the host computer, temporarily stores it in a data buffer, and transfers the data to the BM4 according to the operation of the BM4. Furthermore, when reading data, the data in BM4 is transferred to the data buffer in DC2, and the data in this data buffer is read out from the host computer. Then, for each movement of BM4, BM
DC2 checks whether there is any abnormality in the data of No.4, and this result is temporarily stored in a register in DC2. On the other hand, BMC1 checks whether there are any abnormalities in the data system after each operation and allows the host computer to detect the results.
Reading the register in DC2. In the example shown in FIG. 1, one DC2 is connected to the BMC1, and there is no major problem in reading the register.

On the other hand, in the case of a large-capacity magnetic bubble memory device, a plurality of BM4s are connected and the BM4s are operated simultaneously. In this case, since a plurality of magnetic bubble memory data cannot be connected to the DC2 at the same time, the DC2 is connected and controlled by the number of BM4s that operate simultaneously.

FIG. 2 is a block diagram showing an example of a large-capacity magnetic bubble memory device in which a plurality of _DC2s are connected. ₁ to 2n are connected in parallel.

In such a configuration, the DC2 ₁ controls the data of the BM4 ₁ , the DC2 ₂ controls the data of the _BM42 , and the DC controls the data of the BM on a one-to-one basis. Further, control of the n DCs is performed by the BMC 1 as in FIG. Therefore, for each operation, the BMC 1 reads the registers in the n DCs 2 ₁ to 2n in order to check whether there are any abnormalities in the data. In this case, this register
Conventionally, as a method of reading from BMC1, each DC2
₁ to DC2n were read out in order from _DC21 to DC2n. That is, each DC2 ₁ to 2n
The data in the registers inside was read out using the data bus 5 connected to each DC 2 ₁ to 2n. In addition, the output buffers of each DC2 ₁ to 2n conventionally have a tri-state structure, and the output buffer of only the selected DC is in the active state, and the state of the data bus is set to "H" or "" depending on the contents of the register. Set it to L” level. In this case, since the output buffers of the other unselected DCs are in an off state, the contents of the registers of the unselected DCs do not interfere with the contents of the data bus.

Figure 3 shows the conventional tri-state buffer.
FIG. 2 is a circuit diagram showing an example of a configuration using CMOS. In the figure, the output OUT is connected to the drains of a PMOS transistor 11 and an NMOS transistor 12, and the sources of these transistors 11 and 12 are connected to the power supply and ground, respectively. Further, the gate of the PMOS transistor 11 is connected to the output of the NAND gate 13, and the gate of the NMOS transistor 12 is connected to the output of the AND gate 14.
Furthermore, the signal which is the output of the register in said DC
DATA is connected to AND gate 14 and inverter 1
5 to the NAND gate 13.
Also, a signal for reading the register of the DC
READ is connected to the inputs of NAND gate 13 and AND gate 14.

In a circuit configured like this, when reading the register in DC, only the selected DC is read.
A READ signal is generated and becomes “H”. On the other hand, the READ signal of the unselected DC is in the "L" state. Therefore, when the READ signal is “L”,
Since the gate of the PMOS transistor 11 is at "H" and the gate input of the NMOS transistor 12 is at "L", both transistors 11 and 12 are off. on the other hand,
When the READ signal becomes “H”, the PMOS transistor 11 or
One of the NMOS transistors 12 is turned on,
The OUT signal becomes "H" or "L". That is, when the DATA signal is "H", the NMOS transistor 12 is turned on, and the OUT signal is "L".
Also, when the DATA signal is “L”, the PMOS transistor 11 is turned on, and the OUT signal is “H”.
become.

In this way, when reading the register contents of a DC having an output buffer with a tri-state structure as shown in Fig.
Select one by one, DC2 ₁ , DC2 ₂ ...DC2n
It was necessary to read them in order. For this reason, when multiple DCs are connected, there is a drawback that the operation of the BM must be restricted because it takes time to read the register contents of the DCs.

[Purpose of the invention]

Therefore, the present invention has been made in view of the above-mentioned conventional drawbacks, and its object is to reduce the time required to read the registers of the data controllers in a magnetic bubble memory device in which a plurality of data controllers are connected. An object of the present invention is to provide a magnetic bubble memory control device that speeds up the process.

[Summary of the invention]

A drawback of the conventional magnetic bubble memory control device is that when reading the contents of the registers of a plurality of data controllers, the data controllers are sequentially selected and read, and therefore, the reading time is long. Therefore, in order to shorten the reading time, it is necessary to read the registers of a plurality of data controllers simultaneously. However, if the structure of the output buffer is tri-state, if all data controllers are read at the same time, the OUT signal will naturally go to "H" in some data controllers because the data content is different for each data controller. In other data controllers, it is "L". This results in outputs of different levels across the data bus, resulting in unstable levels of the data bus or shorting of the output transistors with the output transistors of other data controllers. Therefore, the present invention is characterized in that the output buffer of the data controller is controlled to have an open drain structure during simultaneous reading.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a circuit diagram showing the configuration of the output buffer of the data controller in the magnetic bubble memory control device according to the present invention, and the same parts as in FIG. 3 are designated by the same reference numerals. In the figure, the SREAD signal is used as a signal to control data reading.
There is a PREAD signal. Here, the SREAD signal is a signal for selecting a data controller and reading a register, and only the selected data controller has the SREAD signal set to "H". Furthermore, when a data controller is selected and read, the SREAD signal of the unselected data controller is "L". On the other hand, the PREAD signal is a signal that becomes "H" when reading a plurality of data controllers simultaneously, and the PREAD signals of all data controllers become "H" at the same time. Then, the SREAD signal becomes the input signal of the NAND gate 13, the SREAD signal and the PREAD signal become the input of the OR gate 16, and its output becomes the input signal of the AND gate 14.
The input is the same as in FIG. 3.

The operation of the circuit diagram configured in this way is as follows. First, when the data controller simultaneously reads data, the PREAD signal becomes "H", and as a result, the NMOS transistor 12 is turned on or off depending on the state of the DATA signal. That is,
When the DATA signal is "H", the NMOS transistor 12 is turned on, and when it is "L", it is turned off.
On the other hand, the SREAD signal of the PMOS transistor 13 is "L" regardless of the level of the PREAD signal, and the PMOS transistor 13 is off during simultaneous reading. Therefore,
During simultaneous reading, the OUT signal may be in the off state or in the NMOS transistor 1 depending on the contents of the register.
2 is in the on state or one of the states. In such a state, only the NMOS transistor 12 is connected, and depending on the data content, when reading simultaneously,
There is only one state in which the NMOS transistor 12 is on or off, which is equivalent to the absence of the PMOS transistor 11. In other words, it is the same as the open drain output of the NMOS transistor 12.

On the other hand, when the data controller is selected and read, it is controlled by the SREAD signal, so its OUT signal becomes a tri-state signal.

Figure 5 shows a magnetic bubble memory controller (hereinafter referred to as BMC) when a plurality of data controllers (hereinafter referred to as DC) 2' having the configuration shown in Figure 4 are connected.
This is a main circuit diagram showing the connection between DC' ₁ , 2' ₂ ... 2'n (referred to as The magnetic bubble memory (BM) and timing generator (TG), which are not directly related to the above, are not shown. Furthermore, although the data bus 5 shown in FIG. 2 is composed of a plurality of signal lines, in the same figure, for the sake of explanation, only one of the signal lines is shown and designated as the data bus 5a. Further, 6 is a resistor, and one end of this resistor 6 is connected to the data bus 5a, and the other end is connected to a power source (not shown). In this case, NMOS
The impedance of the transistor 12 when it is on is:
It is made sufficiently smaller than resistor 6. Therefore, if even one NMOS transistor 12 is turned on, the signal level of the data bus 5a becomes "L".

In the circuit configuration shown in Figure 5, from BMC1
When reading the registers in DC2' ₁ , 2' ₂ to 2'n at the same time, as described above, DC2' ₁ , 2' ₂ to 2'n
The output of is in the off state or the NMOS transistor 12 is in the on state. Also, all DC2' ₁ ,2' ₂
When the outputs of ~2'n are off, the data bus 5a is connected to the power supply through the resistor 6, and the level becomes "H". On the other hand, if even one NMOS transistor 12 is turned on, the level of the data bus 5a becomes "L" as described above.

Now, when an error occurs in the data system, if the contents of the register are determined so that the DATA signal shown in Figure 4 becomes "H", the data system will be detected at any one of DC2' ₁ to 2'n. When an abnormality is detected, the data bus 5a becomes "L" level by simultaneous reading.
The data bus 5a becomes "H" level when no abnormality is detected in any of DC' ₁ to DC2'n. In this way, the BMC 1 can know whether an abnormality has occurred in the data system of the BM with a single read, and therefore the read time can be shortened. In this case, it is extremely rare for an abnormality to occur, and in most cases it can be treated as no abnormality by simultaneous reading. If an abnormality occurs, it is necessary to know which DC the abnormality occurs in. In that case, select the DC, read the register, and read the registers in order as before.
All you have to do is select and read it out. In that case, you can read it out as a tri-state output in the same way as before.

Also, if you use an open drain structure,
It is also possible to select and read DC.
However, when reading with an open drain structure, when the output becomes "L", a current flows from the resistor 6 shown in FIG. 5 to the DC whose output is "L".
In the embodiments of the present invention, a circuit using a CMOS transistor is described, but since the CMOS transistor is characterized by low power consumption, usage methods that increase power consumption must be avoided. Therefore, when reading the contents of the DC register, if you select DC and read it, other than when reading at the same time which is necessary to shorten the read time, the data is output in tri-state, and when reading it, the resistor 6 is used. It is better to separate the bus line 5a from the bus line 5a.

FIG. 6 is a main circuit diagram showing another embodiment of the present invention. In the same figure, a resistor 6 in FIG. 5 is used to raise the bus line 5a to a high potential.
A PMOS transistor 7 is used in the BMC1.
The gate signal A connected to the gate of this PMOS transistor 7 is at "L" level only during simultaneous DC reading, and is at "H" level in other states. Therefore, PMOS transistor 7 is turned on during simultaneous DC reading,
The same effect as the resistor 6 described above can be obtained. On the other hand, in the case of DC selection and read operation, the PMOS transistor 7 is turned off, the level of the data bus 5a is determined by the output of the selected DC, and the resistor 6
Since it is connected, the current consumption will not increase.

FIG. 7 is a circuit diagram of a main part showing still another embodiment of the present invention. In the figure, a second PMOS transistor 7 is connected in parallel with the first PMOS transistor 7 in the BMC1.
It has a PMOS transistor 8. This second
The PMOS transistor 8 is characterized in that its impedance when on is sufficiently lower than that of the first PMOS transistor 7. In FIG. 6, it is necessary to change the level of the data bus 5a from "L" to "H" by the PMOS transistor 7 when all DC outputs are off when reading the DC simultaneously.
In addition, the stray capacitance connected to the data bus 5a is
It varies greatly depending on the number of DC connections, but approximately 200PF must be considered. On the other hand, from BMC1
The time for reading DC2' ₁ to DC2'n is about 500 ns. Therefore, PMOS transistor 7,
8 makes the data bus 5a “L” for about 500ns.
When changing from "H" to "H", the PMOS transistor 7 requires an impedance of about 1KΩ when turned on. On the other hand, the on-state impedance of the NMOS transistor used for the DC2' ₁ to 2'n output buffer must be sufficiently smaller than the on-state impedance of the PMOS transistor 7, and approximately 10 to 100 Ω is required. . Such low impedance NMOS transistors have large dimensions, making them impractical. The second PMOS transistor 8 is provided to solve this drawback. In other words, the second PMOS transistor 8 is activated only half the time during simultaneous readout.
The gate signal B of is set to "L" and turned on, the data bus 5a is pulled to "H", and after half the time,
The gate signal B is returned to "H" and the gate signal A is set to "L" to turn off the second PMOS transistor 8 and turn on the first PMOS transistor 7. Since the impedance of the second PMOS transistor 8 when it is on is made sufficiently small, the change of the data bus 5a from "L" to "H" is fast, and after it becomes "H", the impedance of the second PMOS transistor 8 is sufficiently small. 2 of
Since the PMOS transistor 7 only needs to maintain the “H” level, the impedance when the first PMOS transistor 7 is on is approximately 100K.
There is no problem even if it is made as large as Ω. In addition, in the embodiment shown in FIG. 7, DC2' ₁ ~
When simultaneously reading 2'n, the size of the NMOS transistor for determining the "L" level can be considered relative to the first PMOS transistor 7, and the impedance when on can be set to 1 to 10KΩ. This makes it possible to reduce the dimensions to a practical level.

In addition, in the above-mentioned embodiment, the case where the data buffer of the data controller is in an open drain format has been explained, but the present invention is not limited to this, and even when an open collector is used, the same thing as described above is achieved. Of course, the effect can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, the contents of the registers of multiple data controllers can be read out simultaneously as necessary, so that high-speed operation of the magnetic bubble memory is possible, and the data controllers can be selected. A tri-state output can be used for operation, and an extremely excellent effect can be obtained in that the power consumption of the control circuit can be reduced.

[Brief explanation of the drawing]

1 to 3 are main part block diagrams showing an example of a conventional magnetic bubble memory control device, and FIGS.
FIG. 6 is a block diagram of a main part showing an embodiment of a magnetic bubble memory control device according to the present invention, FIG. 6 is a block diagram of main parts showing another embodiment of a magnetic bubble memory control device according to the present invention, and FIG. FIG. 7 is a block diagram of main parts showing still another embodiment of the magnetic bubble memory control device according to the invention. 1... Magnetic bubble memory controller (BMC), 2' ₁ , 2' ₂ to 2'n... Data controller (DC), 3... Timing generator (TG), 4, 4 ₁ , 4 ₂ to 4n ...Magnetic bubble memory (BM), 5, 5a... Data bus, 6... Resistor, 7, 8... First and second PMOS transistors, 11... PMOS transistor, 12...
NMOS transistor, 13...NAND gate,
14...AND gate, 15...Inverter, 1
6...OR gate.

Claims (1)

[Scope of Claims] 1. A magnetic bubble memory control device comprising at least a magnetic bubble memory controller that controls an operation sequence of a magnetic bubble memory, and a data controller that controls a data system, wherein a register in the data controller is When the magnetic bubble memory controller reads out registers in multiple data controllers in parallel, the data buffer of the data controller has an open drain or open collector configuration, whereas when only the register of one data controller is read, the data buffer of the data controller has an open drain or open collector configuration. A magnetic bubble memory control device comprising a read control means having a three-state configuration. 2. A first transistor that maintains the level of a data bus connecting the magnetic bubble memory controller and the data controller is provided in the magnetic bubble memory controller, and the first transistor is turned on during parallel reading. A magnetic bubble memory manufacturing apparatus according to claim 1. 3. In the magnetic bubble memory controller, a second transistor different from the first transistor that maintains the level of the data bus and whose impedance when turned on is lower than that of the first transistor is arranged in parallel with the first transistor. 2. The magnetic bubble memory control device according to claim 1, wherein the second transistor is turned on in the first half of a read cycle during parallel read of registers in the data controller.