JPH055169B2 - - Google Patents

Info

Publication number
JPH055169B2
JPH055169B2 JP59131208A JP13120884A JPH055169B2 JP H055169 B2 JPH055169 B2 JP H055169B2 JP 59131208 A JP59131208 A JP 59131208A JP 13120884 A JP13120884 A JP 13120884A JP H055169 B2 JPH055169 B2 JP H055169B2
Authority
JP
Japan
Prior art keywords
wafer
circuit
integrated circuit
layer
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59131208A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6052048A (ja
Inventor
Aaru Kurisuchan Reimondo
Suu Harii
Ee Wagunaa Haabaato
Shii Zaachaa Josefu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Teletype Corp
Original Assignee
Teletype Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teletype Corp filed Critical Teletype Corp
Publication of JPS6052048A publication Critical patent/JPS6052048A/ja
Publication of JPH055169B2 publication Critical patent/JPH055169B2/ja
Granted legal-status Critical Current

Links

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Die Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP59131208A 1983-06-27 1984-06-27 集積回路デバイスの製作方法 Granted JPS6052048A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/508,314 US4485553A (en) 1983-06-27 1983-06-27 Method for manufacturing an integrated circuit device
US508314 1995-07-27

Publications (2)

Publication Number Publication Date
JPS6052048A JPS6052048A (ja) 1985-03-23
JPH055169B2 true JPH055169B2 (Direct) 1993-01-21

Family

ID=24022252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59131208A Granted JPS6052048A (ja) 1983-06-27 1984-06-27 集積回路デバイスの製作方法

Country Status (5)

Country Link
US (1) US4485553A (Direct)
EP (1) EP0132614B1 (Direct)
JP (1) JPS6052048A (Direct)
CA (1) CA1205578A (Direct)
DE (1) DE3466955D1 (Direct)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468857A (en) * 1983-06-27 1984-09-04 Teletype Corporation Method of manufacturing an integrated circuit device
US4688075A (en) * 1983-07-22 1987-08-18 Fairchild Semiconductor Corporation Integrated circuit having a pre-attached conductive mounting media and method of making the same
JPS60100450A (ja) * 1983-11-07 1985-06-04 Disco Abrasive Sys Ltd 半導体ウエーハ装着及び切断装置
US4662956A (en) * 1985-04-01 1987-05-05 Motorola, Inc. Method for prevention of autodoping of epitaxial layers
DE3632943A1 (de) * 1986-09-27 1988-03-31 Bosch Gmbh Robert Hochfrequenz-leistungs-transistor in bipolar-epitaxial-technik
US4778258A (en) * 1987-10-05 1988-10-18 General Electric Company Protective tab structure for use in the fabrication of matrix addressed thin film transistor liquid crystal displays
FR2664095B1 (fr) * 1990-06-28 1993-12-17 Commissariat A Energie Atomique Procede de fabrication d'un contact electrique sur un element actif d'un circuit integre mis.
US6323139B1 (en) 1995-12-04 2001-11-27 Micron Technology, Inc. Semiconductor processing methods of forming photoresist over silicon nitride materials
US5926739A (en) 1995-12-04 1999-07-20 Micron Technology, Inc. Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride
US6300253B1 (en) 1998-04-07 2001-10-09 Micron Technology, Inc. Semiconductor processing methods of forming photoresist over silicon nitride materials, and semiconductor wafer assemblies comprising photoresist over silicon nitride materials
US6635530B2 (en) * 1998-04-07 2003-10-21 Micron Technology, Inc. Methods of forming gated semiconductor assemblies
US6316372B1 (en) 1998-04-07 2001-11-13 Micron Technology, Inc. Methods of forming a layer of silicon nitride in a semiconductor fabrication process
US5985771A (en) 1998-04-07 1999-11-16 Micron Technology, Inc. Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
JP2003503854A (ja) * 1999-06-29 2003-01-28 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体デバイス
JP2005101290A (ja) * 2003-09-25 2005-04-14 Disco Abrasive Syst Ltd 半導体ウエーハの分割方法
US9780143B2 (en) * 2015-08-25 2017-10-03 Western Digital Technologies, Inc. Implementing magnetic memory integration with CMOS driving circuits

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1235197A (en) * 1967-07-03 1971-06-09 Texas Instruments Inc Manufacture of circuit element arrays
JPS501872B1 (Direct) * 1970-01-30 1975-01-22
US3769562A (en) * 1972-02-07 1973-10-30 Texas Instruments Inc Double isolation for electronic devices
US3775838A (en) * 1972-04-24 1973-12-04 Olivetti & Co Spa Integrated circuit package and construction technique
CH560463A5 (Direct) * 1972-09-26 1975-03-27 Siemens Ag
DE2348325A1 (de) * 1973-09-26 1975-04-03 Licentia Gmbh Halbleiteranordnung mit fuer die drahtlose kontaktierung geeigneten anschlusskontakten
US3852563A (en) * 1974-02-01 1974-12-03 Hewlett Packard Co Thermal printing head
US4110598A (en) * 1975-09-02 1978-08-29 Texas Instruments Incorporated Thermal printhead assembly
JPS5283070A (en) * 1975-12-29 1977-07-11 Seiko Instr & Electronics Ltd Production of semiconductor device
JPS5387163A (en) * 1977-01-12 1978-08-01 Hitachi Ltd Production of semiconductor device
US4134125A (en) * 1977-07-20 1979-01-09 Bell Telephone Laboratories, Incorporated Passivation of metallized semiconductor substrates
JPS5459083A (en) * 1977-10-19 1979-05-12 Sumitomo Electric Ind Ltd Double-sided pattern forming method for semiconductor wafer
US4205099A (en) * 1978-04-14 1980-05-27 Sprague Electric Company Method for making terminal bumps on semiconductor wafers
CA1109927A (en) * 1978-06-26 1981-09-29 Edmund T. Marciniec Manufacture of thin film thermal print head
US4266334A (en) * 1979-07-25 1981-05-12 Rca Corporation Manufacture of thinned substrate imagers
JPS5717158A (en) * 1980-07-04 1982-01-28 Fujitsu Ltd Manufacture of semiconductor device
JPS5745254A (en) * 1980-09-01 1982-03-15 Nippon Telegr & Teleph Corp <Ntt> Automatic detector for amount of silicon wafer worked
JPS5893345A (ja) * 1981-11-30 1983-06-03 Nec Corp 半導体装置の製造方法
US4472875A (en) * 1983-06-27 1984-09-25 Teletype Corporation Method for manufacturing an integrated circuit device
US4468857A (en) * 1983-06-27 1984-09-04 Teletype Corporation Method of manufacturing an integrated circuit device

Also Published As

Publication number Publication date
EP0132614A1 (en) 1985-02-13
EP0132614B1 (en) 1987-10-28
US4485553A (en) 1984-12-04
JPS6052048A (ja) 1985-03-23
DE3466955D1 (en) 1987-12-03
CA1205578A (en) 1986-06-03

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