JPH0550079B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an associative memory device, that is, a memory device that can perform addressing based on stored contents.

[Prior art and its problems]

This type of content addressable memory device is an important device used as a component of an electronic computer. An example of the application of associative memory is ``Ultra-high-performance electronic computers using large-scale projects'' (edited by the Agency of Industrial Science and Technology, Ministry of International Trade and Industry,
Published by Japan Industrial Technology Promotion Association (July 1947)
Mentioned in PP45-48. According to this, the associative memory device stores which address of the main memory device corresponds to a sector of the buffer memory, and enables address conversion from a logical address to a physical address to be performed at high speed by searching the contents.

Also, pages 102 to 136 of Nikkei Electronics (published October 27, 1980) describe list processing, image processing, and applications to Dentabase.

Regarding the associative memory elements used in this type of associative memory device, there are already many references, such as ``logical memory'' published in ``Information Processing Handbook.''
(Published by Ohmsha in May 1947, edited by Information Processing Society of Japan,
It is introduced in PP13-96-PP13-99).
According to this, this type of associative memory device requires an associative memory element having a configuration in which each memory element that can store information is provided with a coincidence detection circuit that checks whether the stored content matches the search information. Therefore, compared to memory elements used in ordinary memory devices that are accessed by supplying an address indicating the storage location of desired data, conventional associative memory elements have a more complex structure.
It had the disadvantage that the cost per bit was several tens of times higher.

In order to eliminate this drawback, an associative memory device has been considered in which a normal memory element is used in the information storage section and a match detection circuit is provided for each word. However, this associative memory device has a drawback in that it requires a number of search operations corresponding to the number of bits.

Furthermore, a first normal storage element which takes the search information as an address input and stores data information, and a second normal storage element which takes the data information or the read output of the first normal storage element as an address input and stores the search information. An associative memory device using memory elements was published in Japanese Patent Application Laid-open No.
No. 49-73039. However, although this associative memory device has the advantage of being able to be constructed using ordinary memory elements, as the number of bits of search information or data information increases, the number of memory elements required increases significantly, resulting in an increase in price. have.

[Purpose of the invention]

The object of the present invention is to easily overcome the above-mentioned drawbacks of the conventional art and provide a high-speed, six-capacity, low-cost content addressable memory device that is constructed of ordinary memory elements that can be accessed by supplying an address.

Another object of the present invention is to provide an associative memory device that can perform a search operation by masking a portion of search information.

Furthermore, another object of the present invention is to provide an associative memory device that allows search operations not only for matching but also for size relationships as search conditions.

[Structure of the invention]

Therefore, according to the present invention, a storage means in which storage elements are arranged in a matrix, input data is inputted, and an output is connected to each row selection line of the storage means, and the input data is specified by the input data of the storage means at the time of search. a row selection means for sequentially driving a row selection line and its adjacent row selection lines, which receives a registered address as an input, has an output connected to each column selection line of the storage means, and is specified by the registered address at the time of registration. Select a specific column,
Column selection means for selecting all columns during a search; write data generation means for inputting input data and supplying write data that is inverted at a row specified by the input data to a write data line for each row of the storage means;
Temporary storage means for storing the read output of the line specified by the input data of the storage means, and a search condition for determining whether this output and the next read output of the storage means match a given search condition. A content addressable memory device characterized by comprising a processing means and an encoding means connected to the output thereof is obtained.

〔Example〕

The present invention will be explained in more detail below using the drawings.

FIG. 1 is an explanatory diagram of an embodiment of an associative memory device according to the first invention. This associative memory device receives input data 101 and search conditions 102, and outputs a search address 162 in which data satisfying the search conditions 102 is stored. A row selection means 120 is connected to this by a row selection line 121 and drives all row selection lines 121 during a registration operation, and drives a row selection line 121 designated by input data 101 during a search operation, and a storage means. Each column selection line 13
1 and register address 132 when registering.
The example selection means 130 drives the column selection line 131 designated by , and drives all the example selection lines 131 during the search operation, and the write data line 141 supplies write data to the storage elements of each row of the storage means 110. Write that is connected to the storage means 110 and supplies write data to the write data line 141 specified by the input data 101 with write data inverted from "0" to "1" or from "1" to "0". Data generation means 140 and storage means 110
a register 145 serving as a temporary storage means for receiving the read signal 116 from the search condition processing means 15 which inputs this output 115 and the next read signal 116 and outputs whether or not they satisfy the search condition;
0 and this output 152 as input, and if “1” is included in it, a matching signal 161 of “1” is input.
and an encoding means 160 for outputting a search address 162 indicating the position of "1".

The storage means 110 is constituted by a conventional storage element that is accessed by providing an address indicating the storage location of desired data. If the memory structure of this content addressable memory device is N words and M bits, then the memory structure of the storage means 110 will be 2M rows and N columns, that is, 2M words and N bits. The number of bits of the input data 101 is M bits, and the number of bits of the registered address 132 and search address 162 is log ₂ N bits.

The basic operation of this content addressable memory device consists of a registration operation and a search operation. Input data 101 is given as registration information during a registration operation and as search information during a search operation. Furthermore, the search condition given as the search condition data 102 can be selected from large, small, match, and any combination thereof. The registration operation and search operation will be sequentially explained below.

In the registration operation, registration information is given as an operation mode signal 103 of "1" indicating the registration operation, a registration address 132, and input data 101.
With the operation mode signal 103 of "1", the row selection means 120 drives all the row selection lines 121 of the storage means in parallel, and the column selection means 130 drives all the row selection lines 121 of the storage means in parallel.
Column selection line 131 of storage means 110 specified by 2
Only select the drive.

FIG. 2 is an explanatory diagram of the storage contents of the storage means 110, and also serves as an explanatory diagram of write data 141 generated by the write data generation means 140. The higher the row is located, the smaller the input data 101 is specified. The write data generating means 140 will be explained using FIG. The write data generation means 140 generates input data 1 as registration information.
01 is input, and the storage means 1 stores write data in which the data is inverted from the row specified by the input data 101.
Supply each row of 10. If the registration information is A,
The write data generating means 140 generates write data 141 in which the rows specified by the value greater than or equal to the value of A are "1" and the rows corresponding to the value less than or equal to the value A are "0". These write data 141 are write pulse signal 1
04, the registered address 1 is registered as shown in Figure 2.
It is stored in the column of storage means specified by 32.

The registration operation is performed by the above operation. During the search operation, search information is given as input data 101 along with an operation mode signal 103 of "0" indicating the search operation. Furthermore, search condition processing means 1
Search condition data 102 is supplied to 50 . “0”
The row selection means 12
0 sequentially selects two rows of the storage means 110 specified by the search information, and the column selection means 130 selects the two rows of the storage means 110 specified by the search information.
All column select lines 131 of 0 are read in parallel. First, the storage means 110 outputs the contents of one line specified by the search information as a read signal 116. This read signal 116 is taken into the register 145 by a first clock signal 146 applied in synchronization with the input data 101.

Next, when a row shift signal 122 is applied to the row selection means 120, the row selection means 120 selects the input data 10.
Selects the row specified by the value 1 less than the value 1. Therefore, the storage means 110 outputs the contents of the next higher row as the read signal 116. Since information is stored in the storage means 110 as shown in FIG. 2, the register 14 for the column in which registered information matching the search information is stored
The output 115 of 5 and the read signal 116 are "1," respectively.
0''. Also, the output 115 of the register 145 and the read signal 11 for the column in which registered information with a value larger or smaller than the search information is stored.
6 becomes "1, 1" and "0, 0", respectively.

Furthermore, if you register registration information with a value of zero,
“1” is stored in all rows of the column specified by the registered address 132 of the storage means 110. When a search operation using zero search information is performed in this state, the contents of the 0th line of the storage means 110 are read. Next, the row selection means 1 after being supplied with the row shift signal 122
20 does not drive any row selection line 121. Therefore, the read signal 116 becomes "0".

The output 115 of this register 145 and the read signal 116 are supplied as a pair to the search condition processing means 150. Further, each search condition processing means 150 is supplied with 3-bit search condition data 102 indicating search conditions of large, small, and matching. Register 145 input to each search condition processing means 150
Only when the output 115 and the read signal 116 satisfy the search conditions based on the search condition data 102, the search condition processing means 150 generates a search result signal 152 of "1" and supplies it to the encoding means 160.

FIG. 3 shows a search condition that generates a search result signal 152 of "1" which means that the search condition is satisfied, the output 115 of the register 145, and the read signal 11.
The correspondence with 6 is shown. As shown in FIG. 3, the small search condition is "0, 0" at the output 11 of the register 145.
5 and read signal 116, the search condition for small or match is "0, 0" or "1,
1” register 145 output 115 and read signal 1
Satisfied in 16 cases.

The encoding means 160 inputs the search result signal 152, and contains the search result signal 152 of "1".
is included, it becomes “1” along with matching signal 161.
A search address 162 indicating the location of the search result signal 152 is output to an external device. The matching signal 161 contains search information and information satisfying the search conditions in the storage means 11.
0, and its address or column is indicated by search address 162.

As explained above, this associative memory device has 2M
A memory means 110 of conventional memory elements for N words and N bits can be used to construct an associative memory for N words and M bits, resulting in a list price. Also,
The search operation is performed twice and the registration operation is performed in one memory access, allowing high-speed operation. Furthermore, search operations can be performed under various search conditions including size relationships, etc., thereby providing a highly functional associative memory device.

FIG. 4a is an explanatory diagram of one embodiment of the row selection means 120 used in the associative memory device of FIG. 1. This row selection means input data 101 which becomes search information.
As input data 101, the higher the value of information input, the lower the output is set to "1".
a decoder 410 whose upper and lower outputs of these two adjacent outputs are connected to an A input and a B input, respectively, and a selection circuit 420 which selectively outputs either one by a row shift signal 122; and an OR gate 430 whose output is connected to the row selection line 121.

During the registration operation, an operation mode signal 103 of "1" is applied. Therefore, this row selection means drives all row selection lines 121 by OR gates 121. During the search operation, the operation mode signal 1 is “0”.
03 and a row shift signal 122 of "0" is initially applied. The selection circuit 420 selects the A input by the row shift signal 122 of "0". Therefore, the row selection line 121 specified by the input data 101 given as search information is driven. Next, when the row shift signal 122 of “1” is applied, the selection circuit 420
selects B input. Therefore, this row selection means selects the row selection line 1 that is one line above the previously driven row selection line 121.
21. However, if zero input data 101 is input, which row selection line 12
1 is not driven.

FIG. 4b is an explanatory diagram of another embodiment of the row selection means 120 of the associative memory device of FIG. 1. This row selection means is a counter 440 that takes in input data 101 and decrements the value by 1 in response to a row shift signal 122.
, a decoder 450 connected to this output, and an OR gate 46 which performs the logical sum of this output and the operation mode signal 103 and whose output is connected to the row selection line 121.
0.

Operation mode signal 103 is “1” during registration operation.
is applied, and all row selection lines 121 are driven by OR gate 460. “0” during search operation
An operation mode signal 103 is given thereto, and input data 101 given as search information is taken into the counter 440. If the number of bits of the input data 101 is M bits, the number of bits of the counter 440 is (M+1) bits. The most significant bit 441 of counter 440 is connected to an enable input of decoder 450. First, the decoder 450 drives the row selection line 121 specified by the search information stored in the counter 440 via the OR gate 460. When the row shift signal 122 is then applied, the contents of the counter 440 become the search information minus one. Therefore, the decoder 450 selects the row selection line 12 that is one line above the row selection line 121 that has been driven so far.
Drive 1. However, when zero search information is given, the most significant bit 441 of the counter 440 becomes "1" after the row shift signal 122 is applied, and each output of the decoder 450 is prohibited. That is, not one row selection line 121 is driven.

FIG. 5 is an explanatory diagram of an embodiment of the column selection means 130 used in the associative memory device of FIG. 1. This column selection means includes a decoder 510 that inputs the registered address 132, an inverter 520 that inverts the operation mode signal 103, and performs a logical sum of the output of the inverter 520 and each output of the decoder 510,
It consists of an OR gate 530 that drives the column selection line 131 of the storage means 110, and is set to "1" during the registration operation.
The operation mode signal 103 is supplied to the decoder 5.
10 is registered address 1 via OR gate 530
Column selection line 13 of storage means 110 designated by 32
1 is selectively driven. Therefore, storage means 110
Allows writing to specific columns. During the search operation, the operation mode signal 103 of "0" is supplied, and the OR gate 530 drives all column selection lines 131 without being influenced by the output of the decoder 510. Therefore,
It allows parallel reading of all columns of storage means 110.

FIG. 6 is an explanatory diagram of an embodiment of the write data generating means 140 used in the associative memory device of FIG. This write data generation means is a decoder 610 that receives input data 101 as registration information.
and an OR gate 620. If the registration information is A, the write data line 141 has a second
Write data corresponding to the contents of one column of the storage means 110 shown in the figure is supplied. That is, the output of the decoder 610 is also supplied to the lower write data line 141 via the OR gate 620, and the write data of "1" is generated on the write data line 141 specified by the value greater than or equal to the registered information.

FIG. 7 is an explanatory diagram of an embodiment of the search condition processing means 150 used in the associative memory device shown in FIG. 1. This search condition processing means includes two inverters 7.
10,720 and three AND gates 730,7
40,750 and an OR gate 760, which outputs the output 115 of the register 145 and the read signal 1.
16 is supplied, and a small condition signal 711, a match condition signal 712, and a large condition signal 713 are supplied as the search condition data 102. Each AND gate 730,
740 and 750 process the small, matching, and large search conditions shown in FIG. 3, respectively. For example, if a search condition of “1” of the small condition signal 711 is given,
A search result signal 152 of “1” indicates that the search condition is satisfied only when the output 115 of the register 145 of (0,0) and the read signal 116 are supplied.
occurs. Small condition signal 711, matching condition signal 7
12. By combining the large condition signal 713,
The search conditions shown in FIG. 3 can be processed.

In addition, in the above explanation, the OR gate 420,
530, 630, 760, and gate 620,
730, 740, and 750 can be replaced with other logic gates such as AND gates and OR gates by setting the logic value "0" to be true.

FIG. 8 is an explanatory diagram of an embodiment of an associative memory device according to the second invention. This associative memory device
It is possible to handle search information with a larger number of bits than the content addressable memory device shown in the figure, and it is possible to perform searches and multiple matching processing by masking part of the search information. For this reason, a search processing means 810 is provided in place of the search condition processing means 150, and further includes an OR gate 820 serving as a masking means, a counter 830 serving as a counting means, and a decoder 8 serving as a decoding means.
40 have been added.

The memory structure of this associative memory device is N words M×K
In the case of bits, the storage means 110 has 2M×K rows N
It consists of memory elements arranged in rows and columns.
In other words, the storage structure of the storage means 110 is ^2M ×K words and N bits. Further, the number of bits of the counter 830 is log2K bits. Therefore, if the storage means 110 of 2M rows and N columns in FIG. M×K bit search information and registration information is M bit input data 101
The data is divided into K times and sent to the row selection means 120 and the write data generation means 140 sequentially from the top. The registration information sent as K input data 101 is stored in each block of the storage means 110 for each input data 101. For example, registration information A consisting of four M-bit data A ₀ , A ₁ , A ₂ , A ₃ stores data A ₀ in the 0th block of the storage means 110, data A ₁ in the first block, and data in the second block.
Data A ₂ and data A ₃ are stored in the third block, respectively, as shown in FIG.

The registration operation and search operation will be explained in more detail. First, the four M-bit data shown above
A registration operation for registering registration information A consisting of A ₀ , A ₁ , A ₂ , and A ₃ at address J will be described. Here, it is assumed that data A ₀ is the upper part of the registration information A, and data A ₃ is the lowest part, and the data are supplied sequentially from the upper data A ₀ . Next, a search operation based on the same information will be explained. At the start of both operations, an initial setting signal 811 is supplied, and initial values of the search processing means 810 and the counter 830 are set.

In the case of a registration operation, an initial setting signal 811 is given and an operation mode signal 1 of "1" indicating a registration operation is given.
03 and the registered address 132 of address J are first supplied. As a result, the contents of the counter 830 are cleared and the 0th block of the storage means 110 is designated. Next, the data that is the upper part of registration information A
While supplying A ₀ as input data 101,
When the write pulse signal 104 is supplied, the write data line 141 specified by the value of data A ₀ or more in the J column of the 0th block of the storage means 110 becomes "1".
The write data will be stored. counter 830
is incremented at the rising edge of the clock signal 812, so that the contents of the counter 830 are incremented at the end of this write and designate the first block of the storage means 110.

By the above operation, partial data of registered information A
A ₀ is written. In this manner, the partial data write operation is performed by supplying input data 100, write pulse signal 104, and clock signal 812. Registration of registration information A is data
A ₀ , A ₁ , A ₂ , A ₃ input data 101 is obtained by performing the write operation of the partial data four times.

FIG. 9 is an explanatory diagram of the storage contents of the storage means 110. As explained above, the four partial data A ₀ ,
When the registration information A consisting of A ₁ , A ₂ , and A ₃ is registered in the registration address 5, data as shown in the figure is stored in the J column of the storage means 110.
That is, each block in column J has A ₀ , A ₁ ,
“1” is stored in the row specified by the values of A ₂ and A ₃ or higher.

In this way, the write operation of partial data in the registration operation of this content addressable memory device is performed in the same manner as the registration operation of the content addressable memory device shown in FIG.

Next, the operation when a search is performed using the same search information A in a state where registration information A is registered at address J will be described. Although this associative memory device can perform a search operation by masking a part of the search information, a search operation in which a mask signal 813 of "0" is first supplied and no mask processing is performed will be described.

In the search operation, an operation mode signal 103 of "0" is supplied. Further, an initial setting signal 811 is applied to set the contents of the counter 830 and the search processing means 810 to initial values.

Next, partial data A ₀ , A ₁ , A ₂ , and A ₃ of search information A are sequentially input as input data 101. When inputting each partial data, the row shift signal 122 of "0" and the first clock signal 146 are input, and then the row shift signal 122 of "1" and the second clock signal 812 are input. As a result, the row selection means 120 first sequentially drives the row selection lines 121 designated by the data A ₀ of the 0th block of the storage means 110 and the data obtained by subtracting 1 from A ₀ . The contents of the storage means 110 connected to the former line selection line 121 are the first
The contents of the storage means 110 connected to the latter row selection line 121 are then output as a read signal 116. The output 115 of register 145 and read signal 116 are incorporated into search processing means 810 on the rising edge of second clock signal 812. Further, the contents of the counter 830 are also clocked by the second clock signal 811.
It increases at the rising edge of , and specifies the next first block. As a result, a search operation for partial data _A0 is performed. Similarly, partial data A ₁ , A ₂ ,
Perform search operation for A ₃ . Storage means 110
contains the contents shown in Figure 9, so
Register 1 for partial data A ₀ , A ₁ , A ₂ , A ₃
The output 115 of 45 and the read signal 116 will be (1, 0), meaning a match.

Next, it is assumed that search information A is divided into K pieces of M-bit partial data A ₀ , A ₁ , . . . _Ai , . The output 115 of the register 145 and the read signal 116 of the storage means 110 for each partial data Ai are the partial data of the registration information and the search information A encoded and stored in the columns of the storage means 110 as shown in FIG. The results of comparison with partial data Ai are shown. partial data
Bi, the output 115 of the register 145 at the rising edge of the second clock signal 812 relative to Ai;
If the read signal 116 is Ci, the partial data Ai
and the partial data of the registered information stored in each column of the storage means 110, that is, the matching relationship.
Ei, major relationship Li, and minor relationship Si are expressed by equations (1), (2), and (3), respectively, as shown in FIG.

Ei=Bi・(i=0～ _K-1 ) ...(1) Li=Bi・Ci(i=0～ _K-1 ) ...(2) Si=・(i=0～ _K-1 )... ...(3) Furthermore, the matching relationship E, major relationship L, and minor relationship S, which are the comparison results between the search information A and the registered information stored in each column of the storage means 110, are (4), (5), respectively. It can be expressed by equation (6).

E=E ₀・E ₁・……・Ei・……・E _K-1 ……(4) L=L ₀ +L ₁・E ₀ +……+Li・E ₀・E ₁・……・Ei _{- 1} +...+L _K-1・E ₀・E ₁・... ・Ei・...・E _K-2 ...(5) S=S ₀ +S ₁・E ₀ +...+Si・E ₀・E ₁ ... ・Ei _-1 +...S _K-1・E ₀・E ₁・...・Ei・... ・E _K-2 ...(6) In addition, the search condition data 102 that is the search condition is Match condition signal Ec, large condition signal Lc, small condition signal Sc
The search result R indicating whether or not the search condition is satisfied can be found using equation (7).

R=E・Ec+L・Lc+S・Sc (7) The search processing means 810 uses the second clock signal 81
Register 1 for partial data Ai in synchronization with 2
45 and the read signal 116, the search result R is obtained by the logical operations of equations (1) to (7), and is outputted as the search result signal 152.

Encoding means 160 which receives this search result signal 152 operates in the same manner as the associative memory device shown in FIG. 1, and generates a search address 162 and matching signal 161. When a plurality of registered information satisfying the search condition is stored in the storage means 110, that is, in the case of multiple matching, a plurality of search result signals 152 of "1" indicating that the search condition is satisfied are generated. The encoding means 160 prioritizes the search result signal 152 and generates a search address 161 with a high priority. This search address 162 is sent to the decoder 8
40 is also supplied. After reading this search address 162, the external device applies a reset signal 841 to the decoder 840. Each output 842 of decoder 840 is connected to an internal reset input of each search processing means 810. Therefore, decoder 840 supplies a reset signal to the internal reset input of search processing means 810 specified by search address 162. The output of the search processing means 810 to which the reset signal 841 is supplied, that is, the value of the search result signal 152 changes from "1" to "0". Therefore, the encoding means 160 changes the position of the search result signal 152 of "1" with the next highest priority to the next search address 16.
Output to the outside as 2. In this way, multiple search addresses that satisfy the search conditions can be generated one after another,
Processing for multiple matching becomes possible. An embodiment of the search processing means 810 is shown in FIG.

The above description of the search operation is an operation in which masking is not applied to the search information. This content addressable memory device can perform a search by masking the search information for each partial data. This is done by applying a mask signal 813 of "1" to the OR gate 820 at the time when the partial data to be masked is input, and prohibiting the application of the second clock signal 812 applied to the search processing means 810 at the same time. . partial data
When the clock signal to the search processing means 810 is masked when inputting Ai, Ei, Li, and Si are removed from equations (4), (5), and (6), and the masked partial data Ai is The comparison result is obtained.

As explained above, according to the present invention, an associative memory device of N words, ^{M.times.K bits can be constructed using the ordinary storage means 110 of 2.sup.M.times.K} words, N bits. In the associative memory device shown in FIG.
Compared to the case where a typical memory element of ^2M x K words and N bits is required for the 10th generation, this associative memory device can be constructed with a smaller capacity memory element, resulting in lower cost. Furthermore, as search conditions, it is possible to search not only for matching relationships but also for size relationships, or to search by masking part of the search information.

FIG. 12 is an explanatory diagram of an embodiment of the search processing means 1120 used in the associative memory device of FIG. 11. This search processing means includes first, second, and third registers 1010, 1020, 1030, and gates 1040, 1041, 1042, 1043,
1044,1045 and orgate 1050,1
051, 1052, 1053 and inverter 10
60,1061. This search processing means uses the above equation (4) to calculate the intermediate result of comparison processing E′i=E ₀・E ₁ ...・Ei (i=0~ _K-1 ) ...(8) L′i=Li・E ′i _-1 (i=0~ _K-1 , E′ _-1 = ₁ ...(9) S′i=Si・E′i _-1 (i=0~ _K-1 , E′ _-1 = ₁ )......(10) is introduced, and each of equations (4), (5), and (6) is transformed into the following (11), (12)(
13)
It is determined by the formula.

E=E′ _K-1 ……(11) L= _K-1 〓 ^t=0 L′i ……(11) S= _K-1 〓 ^t=0 S′i ……(13) Partial data Ai is Before being input, an initial setting signal 811 is applied, the first register 1010 is set, and the second and third registers 1020 and 1030 are set.
Reset it. The first register 1010, AND gate 1040, and inverter 1061 are synchronized with the second clock signal 812, and the partial data
The logical operations of equations (1) and (8) are executed for each Ai. When all partial data Ai have been input, the logical operations of equations (1) and (8) are also completed, and the matching relationship E shown by equation (11) remains in the first register 1010. Similarly, the second register 1020, OR gate 1050, AND gate 1041, and first register 1010 are (2)
Executes the logical operations of equations (9) and (12), and registers the second register 1.
The major relationship L is stored in 020. Further, the third register 1030, the OR gate 1051, the AND gate 1042, the inverter 1060, and the first register 1010 execute the logical operations of equations (3), (10), and (13), and the third register has a small relation. Store S.

These first, second, and third registers 101
The matching relationship E, major relationship, and minor relationship S stored in 0, 1020, and 1030 are search condition data 102
A matching condition signal 712, a major relation signal 713,
A logical operation based on equation (7) is performed with the minor relation signal 711 by AND gates 1043, 1044, 1045 and an OR gate 1053. This search result R is sent from the OR gate 1053 to the search result signal 15.
Output as 2. This signal 152 becomes "1" when the search condition is satisfied.

The initial setting signal 811 is supplied at the start of the search operation and sets the first register 1210 and the second and third registers.
The registers 1220 and 1230 are reset. On the other hand, the reset signal 1112 supplied via the decoder 1110 in FIG.
The third registers 1210, 1220, and 1230 are reset. As a result, the search result signal 15
2 is forcibly cleared to "0". Therefore, the encoding means that receives the search result signal 152 can generate the next search address.

FIG. 11 is an explanatory diagram of an embodiment of an associative memory device according to the third invention. This associative memory is the first
Compared to the associative memory device shown in the figure, it can handle search information and registration information with a larger number of bits.
Search operations and registration operations can be performed faster than the associative memory device shown in the figure. For this purpose, the associative memory device shown in FIG. storage means 110;
a search condition processing means 1110 that receives the read signals 116 and determines whether or not they satisfy the search conditions determined by the search condition data 102; a search result register 1120 that temporarily stores the search result signal 152 supplied from the search condition data 102; Encoding means 1
60, decoder 840, and registered address 132
is input, and the column selection line 131 of each storage means 110
and column selection means 130 for selectively driving the column.

The memory structure of this associative memory device is N words M×K
In terms of bits, each storage means 110 has ^2M rows and N columns of storage elements, that is, ^2M words and N bits, and the number is K. In the associative memory device of FIG. 8, the number of bits is expanded by expanding the number of words of the storage means 110, but in this associative memory device, the number of bits is expanded by increasing the number of storage means 110. Therefore, the block of storage means 110 in the associative memory device of FIG. 8 corresponds to each storage means 110 in this associative memory device. M×K bits of search information and registration information are divided into K pieces of M bits of input data 101, each of which is divided into K pieces of row selection means 12.
0 and the write data generating means 140 in parallel. In FIG. 11, K=3.

During the registration operation, the registration information supplied by the three input data 101 is
As shown in the figure, stored in each storage means 110,
be registered.

During a search operation, each storage means 110 corresponds to each input data 101 supplied as search information.
The contents of are taken into each register 145, and its output 115 and read signal 116 are supplied to search condition processing means 1110. Search condition processing means 111
0 is the output 116 of register 145 and read signal 1
16 satisfies the search conditions determined by the search condition data 102, and sends the result to the search result signal 15.
2 and is supplied to the N-bit search result register 1120. Search result register 1120 receives this search result signal 152 using second clock signal 812. The contents of the search result register 1120 indicate whether the registered information stored in the column of the storage means 110 matches the search information given as the input data 101 and the search conditions given as the search condition data 102 with "1" or "1". Indicated by 0”. The content of “1” indicating that there is a match is stored in the search result register 112.
a matching signal 161 indicating that 0 is held;
A search address 162 indicating the bit position is outputted by the encoding means 160. This search address 162 indicates an address where registered information that satisfies the search conditions is stored.

At the time of multiple matching when multiple addresses match, multiple bits in search result register 1120 hold "1". In this case, the reset signal 8
41 is applied. Decoder 840 supplies a reset signal 841 to the reset input of the bit of search result register 1120 specified by search address 162. As a result, the bit in the search result register 1120 corresponding to the previously output search address 162 is reset. Therefore, the encoding means 160 outputs the next search address 162. The external device monitors the matching signal 161 and indicates that it is “0”.
By applying the reset signal 841 until
All search addresses 162 at the time of multiple matching can be found.

Furthermore, in this way, the content addressable memory device can expand the number of bits of search information and registration information without significantly increasing the storage capacity of the storage means 110. Furthermore, search operations, multiple matching processing, and masking processing based on search conditions that include not only matching conditions but also magnitude relationships are also possible. Furthermore, in the content addressable memory devices of FIGS. 8 and 11, registration information and search operations are input in multiple steps, but with this content addressable memory device, input can be made in parallel.
Therefore, the search operation can be performed by accessing the storage means 110 once, increasing the speed.

FIG. 12 is an explanatory diagram of one embodiment of the search condition processing means 1110 used in the associative memory device of FIG. 11. This search condition processing means includes nine AND gates 1210 to 1218 and three OR gates 1.
220 to 1222, and three decoders 1230,
1240 and 1250. This search condition processing means uses the output 115 of the same bit of each register 145, the read signal 116 of the same column of each storage means 110, and the match condition signal 712, large condition signal 713, and small condition signal 711 as search condition data 102 from outside. is input. In the associative memory device shown in FIG. 11, N search condition processing means are provided corresponding to each column of the storage means 110.

This search condition processing means is the number K of storage means 110.
Assuming that K=3, the coincidence relation E, the major relation L, and the minor relation S are determined by the logical operations of equations (1) to (6). Furthermore, the logical operation with the matching condition signal 712, large condition signal 713, and small condition signal 711, which are search conditions, is performed as shown in (7).
It is executed based on the formula, it is determined whether the search condition is satisfied, and it is generated as the search result signal 152. Each decoder 1230, 1240, 1
250 inputs the output 115 of the register 145 and the read signal 116, and outputs partial data of the search information A.
The coincidence relationships E ₀ , E ₁ , E ₂ for A ₀ , A ₁ , A ₂ and the major relationships L ₀ , L ₁ , L ₂ and the minor relationships S ₀ , S ₁ , S ₂ are expressed as (1), (2), (3)
It is calculated based on the formula. First, second, and third mask signals 123 for masking each partial data
1, 1241, 1251 are each decoder 1230,
1240 and 1250 enable inputs. The output of the decoder to which the mask signal is supplied becomes "1", and the matching relationship, Ei, major relationship Li, and minor relationship Si for the input partial data Ai are (4), (5), (6).
can be removed from the equation. That is, the partial data Ai is masked.

AND gates 1210 and 1215 execute the logical operation of equation (4) to find the matching relationship E. Also, the AND gates 1210, 1211, 1213 and the OR gate 1220 calculate the minor relationship S based on the logical operation of equation (6), and the AND gates 1210, 1212, 1
214 and the OR gate 1221 calculate the major relationship L based on equation (5). Also, and gate 121
6,1217,1218 and orgate 1223 are
A search result R indicating whether or not the search condition is satisfied is obtained by the logical operation of equation (7), and this is output as the search result signal 152.

The search result signal 152 obtained in this manner is supplied to the search result register 1120 in FIG.

Note that such logical operations are performed using gate arrays and
This can be easily realized using PROM, etc.

FIG. 13 is an explanatory diagram of an embodiment of an associative memory device according to still another invention. This associative memory device aims to increase the capacity, and is shown in Figures 1, 8, and 11.
A plurality of content addressable memory units 1310 corresponding to the content addressable memory device shown in the figure are utilized, a plurality of output means 1320 are connected to the content addressable memory units 1310, an encoding means 1330 is connected to each output means 1320, and a write pulse signal 104 is sent to each content addressable memory unit 1310. and a decoder 1340 that applies . Each associative memory unit 1310 has a mask signal 8 in parallel.
13, first clock signal 146, second clock signal 812, search condition data 102, initial setting signal 811, input data 101, operation mode signal 103, registered address 132, row shift signal 12
2 is supplied.

At the time of registration, the operation mode signal 103 of "1" indicating the registration operation, the initial setting signal 811, the second clock signal 812, the input data 101, and the registration address 132 are sent to each associative memory unit 1310 in the first register.
It is provided in the same way as the associative memory device shown in FIGS. 8 and 11. The registered address 132 becomes the lower address of this content addressable memory device, and the upper address is supplied to the decoder 1340 as the upper registered address 1341. The upper registration address 1341 specifies the content addressable memory unit 1310, and the registration address specifies the column of the storage means 110 within the content addressable memory unit 1310. A write signal 1342 instructing a write to the content addressable memory device is provided to decoder fabrication 1340. Decoder 1340 outputs write signal 1342
is selectively supplied as the write pulse signal 104 to the associative unit 1340 specified by the upper registration address 1341. By this decoder memory 1310, the registration information is registered in the associative memory unit 1310 selected by the upper registration address 1341.

During a search, a mask signal 813, first and second clock signals 146, 812, and search condition data 10 are used.
2. The initial setting signal 811, input data 101, operation mode signal 103, and row shift signal 122 are supplied to each content addressable memory unit 1310 in parallel. An associative memory unit 13 in which search information given as input data 101 and information matching the search conditions given as search condition data 102 are registered.
10 outputs a matching signal 161 of "1" and a search address 162. Output means 1320
When a matching signal 161 of "1" is generated from a plurality of associative memory units 1310, the associative memory unit 1310 located on the left side is given a higher priority,
The search address 162 from the content addressable memory unit 1310 with a high priority is set as the lower search address 1321.
Output as . In order to prioritize the associative memory unit 1310, an enable signal 1322 is provided from the left to the right output means 1320. The output means 1320 supplied with the enable signal 1322 of “0” outputs the internal search address 162.
The output buffer is brought into a high impedance state, and an enable signal 1322 of "0" is generated. The output means 1320 supplied with the enable signal of "1" and the matching signal 161 of "1" outputs the search address 162 and generates the enable signal 1322 of "0". Therefore, the output means 13 located on the right side of the output means 1320
The output buffer within 20 is placed in a high impedance state. The output means 1320 that outputs the search address 162 outputs the matching signal 161 as a first matching signal 1323, and the output means 1320 located on the right side outputs the first matching signal 1 of "0".
323 is generated. The encoding means 1330 inputs the first matching signal 1323 and outputs the first matching signal 1323 of "1".
A second matching signal 1331 indicating whether or not the matching signal 1323 has been inputted, and an upper search address 1332 indicating the position of the first matching signal 1323.
and output to an external device. Second matching signal 133
1 indicates that the search information and information satisfying the search conditions are registered in this content addressable memory device, and the upper search address 1332 indicates the position of the registered content addressable memory unit 1310. Furthermore, the lower search address 1321 is stored in the associative memory unit 1310.
The search address 162, that is, the storage means 110
Indicates the column.

The external device monitors the second matching signal 1331;
Upper search address 1332 and lower search address 1
321 and then the first reset signal 1
324 is applied to each output means 1320. The first reset signal 1324 is used to obtain the search address for the next highest priority information when a plurality of matching pieces of information are registered in the associative memory. The output means 1320 that outputs the search address 162 outputs the first reset signal 1324.
The associative memory unit 1 uses the reset signal 841 as the reset signal 841.
310 and the next search address 162
output.

In this way, this associative memory device is shown in Figures 1 and 8.
It is constructed using the associative memory device shown in FIGS.

FIG. 14 is an explanatory diagram of an embodiment of the output means 1320 used in the associative memory device of FIG. 13.
This output means includes an output buffer 1410, three AND gates 1420, 1430, 1440,
It is composed of an inverter 1450.

The search address 162 is output by the left output means 1320.
When the enable signal 1322 and the matching signal 161 inputted to the enable input terminal 1460 from the output buffer 1410 are both “1”,
It is output as a lower search address 1321. In this case, the matching signal 161 is connected to the AND gate 1430
The signal is output as a first matching signal 1323 via. Furthermore, an enable signal 1322 of “0” is output from the enable output terminal 1470.
Therefore, the output buffer 14 of the right output means 1320 connected to this enable output terminal 1470
10 is in a high impedance state.

Further, the first reset signal 1324 is supplied to the content addressable memory unit 1310 as a reset signal 841 via an AND gate 1420. “1”
output means 1 for generating a first matched signal 1323 of
The first reset signal 1324 applied to the output means 1320 located on both sides of 320 does not pass through the AND gate 1420 and does not output the reset signal 841. Therefore, if the associative memory unit 1310 to which the reset signal 841 is applied has multiple matching, the associative memory unit 1310 finally generates the search address 162 with a high priority.

Note that when the associative memory device shown in FIG. 1 is used as the associative memory unit 1310, the mask signal 81
3. Second clock signal 812, initial setting signal 8
11 becomes unnecessary, and when the associative memory device of FIG. 11 is used, the initial setting signal 811 becomes unnecessary.

FIG. 15 is an explanatory diagram of an embodiment of an associative memory device according to still another invention. This associative memory device stores keys and data as pairs in each associative memory section 151.
0 in the data storage section 1520, and by giving a key, the data paired with it is obtained. The associative memory unit 1510 is shown in FIGS.
Corresponding to the associative memory device shown in FIG. 11 or FIG. 13, the data storage unit 1520 is constituted by a normal storage device that outputs data stored at an address when given an address.

The associative memory unit 1510 includes a reset signal 84.
1, mask signal 813, first and second clock signals 146, 812, input data 101, initial setting signal 811, search condition 102, operation mode signal 1
03, registered address 132, row shift signal 12
2. The write signal 104 is input, and the write signal 104 and address information 1 are input to the data storage section 1520.
540 and write data 1550 are input.
The selection circuit 1530 selects the registered address 1 during the registration operation.
32, the search address 162 is output as address information 1540 to the data storage unit 1520 during the search operation.

In the registration operation, paired keys and data are provided as each input data 101 and write data 1540, and are stored at addresses specified by the registration address 132 of the associative memory section 1510 and data storage section 1530, respectively. When the same registered key is given as input data 101 and a search operation is performed, a search address 162 that is the same as the registered address 132 is output from the associative memory section. This search address 16
2 is connected to the data storage section 1 via the selection circuit 1530.
520 becomes the address information 1540. Therefore, the data that pairs with the key is output from the data storage section 1520 as read data 1560.

For example, if a registration operation is performed using "apple" as a key and "red" as data, and then a search operation is performed using "apple" as a key, "red" is output as read data 1560. Furthermore, after registering "red" as a key and "apple" as data, if a search operation is performed by giving "red" or "apple" as a key, each "apple" or "red" will be read as read data 1560. is output.

In this way, this associative memory device can realize the above associative operation at high speed. Further, after storing the age as a key and the name as data in the associative memory unit 1510 and the data storage unit 1520, respectively, and then giving the age as the key, the corresponding name is found as read data 1560. In this case, if a matching relationship or a major relationship is given as a search condition, the names of people who are the same age as the key or the names of people who are older than the key can be immediately obtained, respectively. In other words, this content addressable memory device can immediately search for magnitude relationships for unsorted information, making it possible to realize a high-speed database system.

〔Effect of the invention〕

As described above, the content addressable memory device according to the present invention can be constructed using inexpensive ordinary memory elements that are accessed by supplying an address indicating the storage location of desired data. The associative memory device of FIG. 1 for N words and M bits is used as storage means 110.
It can be constructed with ordinary memory elements of 2 ^M words and N bits,
The content addressable memory device of FIG. 8 or FIG. 11 of N words ^M.times.K bits can be constructed of ordinary memory elements of 2M.times.K words N bits or K ordinary memory elements of ^2M words N bits. Therefore, 1 megabit
If RAM semiconductor technology is used, for example, an associative memory device of 4 kilowords, 8 bits as shown in FIG.
The associative memory device shown in FIGS. 1 and 11 can be realized with a single chip. Compared to a generally commercially available semiconductor associative memory, such as the associative memory IC8220 manufactured by Signetics, which has 4 words and 2 bits, the associative memory device according to the present invention can be said to have an extremely large capacity.

In addition, search operations and registration operations in this content addressable memory device can be completed with one or several accesses to the normal storage elements, and are faster than conventional word serial/bit parallel or word parallel/bit serial content addressable memory devices. be.

Furthermore, search operations and multiple matching processes that mask part of the search information are also possible. Furthermore, as search conditions, it is possible to search not only for matching conditions but also for size relationships. Furthermore, the number of words can be easily expanded, and a content addressable memory device with a larger capacity can be realized.

That is, according to the present invention, a high-speed, large-capacity, low-cost, and highly functional associative memory device can be realized. When such an associative memory device is used as a storage device of an information processing system, it is possible to realize an information processing system that can perform associative processing and comparison processing in databases, pattern recognition, artificial intelligence, etc. at high speed.

In the above explanation, "1" is written in each column of the storage means 110 in a row specified by a value greater than or equal to the registered information value.
was stored. This is an example of a storage method, and it is also possible to store "1" or "0" in a row specified as less than or equal to the registered information value.
As the method of storing write data in the storage means 110, various methods can be selected by combining them. Therefore, the write data generation means 140, the search condition processing means 150, 1110, and the search processing means 810
can be easily modified depending on the method of storing write data in the storage means 110. That is, the above description does not limit the scope of the claims of the present invention.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an embodiment of an associative memory device according to the first invention, and FIG. 2 is a storage means 110 of FIG.
FIG. 3 is a diagram showing a method of storing registration information. FIG. 3 is an explanatory diagram showing the relationship between search conditions, register outputs, and read signals; FIG. 4 is an explanatory diagram of one embodiment of the row selection means; FIG. 5 is an explanatory diagram of one embodiment of the column selection means; FIG. 6 is an explanatory diagram of one embodiment of the writing means, FIG. 7 is an explanatory diagram of one embodiment of the search condition processing means, and FIG. 8 is an explanatory diagram of one embodiment of the associative memory device according to the second invention. FIG. 9 shows storage means 1 of the associative memory device shown in FIG.
10 is an explanatory diagram of an embodiment of the search processing means 810 of the associative memory device of FIG. 8, and FIG. 11 is an explanatory diagram of an embodiment of the associative memory device according to the third invention. 12 is a diagram showing an example of the search condition processing means 1110 of the associative memory device of FIG. 11, FIG. 13 is an explanatory diagram of an embodiment of the associative memory device according to another invention, and FIG. FIG. 13 is an explanatory diagram of an embodiment of the output means 1320 of the associative memory device, and FIG. 15 is an explanatory diagram of an embodiment of the associative memory device of still another invention. 110...Storage means, 120...Line selection means,
130...Column selection means, 140...Write data generation means, 145...Register, 150, 111
0... Search condition processing means, 160, 1330...
Encoding means, 410, 450, 510, 61
0,840,1230,1240,1250,1
340... Decoder, 420, 1530... Selection circuit, 440, 830... Counter, 1120...
...Search result register, 1310...Associative memory unit, 1320...Output means, 1410...Output buffer, 1510...Associative memory unit, 1560...
...Data storage section.

Claims (1)

[Claims] 1 storage means in which storage elements are arranged in a matrix;
a row selection means that receives input data, has an output connected to each row selection line of a storage means, and sequentially drives a row selection line designated by the input data of the storage means and its adjacent row selection line during a search; a column selection means which takes an address as an input, whose output is connected to each column selection line of the storage means, selects a specific column specified by the registration address at the time of registration, and selects all columns at the time of search; write data generation means for inputting write data that is inverted at a row designated by the input data to a write data line for each row of the storage means; and storing read output of the row designated by the input data of the storage means. a search condition processing means for determining whether or not this output and the next read output of the storage means match a given search condition; and an encoding means connected to the output. Characteristic associative memory device.