JPS61104497A - Associative memory device - Google Patents

Abstract

PURPOSE:To use the ordinary memory elements which receive accesses with supply of addresses to obtain an inexpensive associative device of a high speed and large capacity, by providing a temporary memory means which stores the read output of a memory means and a retrieval condition processing means which decides whether or not said read output and the next read output are accordant with the given retrieval conditions. CONSTITUTION:An associative memory device supplies the input data 101 and the retrieval conditions 102 and delivers a retrieval address 162 storing the data that satisfies the conditions 102. In addition, a memory means 110 containing memory elements distributed in a matrix form is provided together with a row selection means 120, a column selection means 130, a write data generating means 140, a register 145 which fetches a read signal 116 from the means 110, a retrieval condition processing means 150 which decides whether the output 115 of the register 145 and the next read signal 116 satisfy the conditions 102 or not, and an encoding means 160. The storage constitution of this associative memory device is defined as N words and M bits. Thus the storage constitution of the means 110 is equal to 2M rows and N columns, i.e., 2M words and N bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an associative memory device, that is, a memory device that can perform addressing based on stored contents.

[Prior art and its problems]

This type of content addressable memory device is an important device used as a component of an electronic computer. An example of the application of associative memory is [Ultra-high-performance electronic computer developed by Daisei Project]
(Edited by the Agency of Industrial Science and Technology, Ministry of International Trade and Industry, published by the Japan Industrial Technology Promotion Association, July 1947), pp. 45-48. According to this, the associative memory stores which address of the main memory corresponds to a sector of the buffer memory,
To enable high-speed address conversion from a logical address to a physical address by content search.

In addition, on pages 102 to 136 of Nikkei Electronics (published October 27, 1980), list processing, image
' treatment and application to Dentabase are described.

There are already many documents about associative memory elements used in this kind of associative memory device, such as [Information Processing Handbook].
"Logical Memory" published in May 1947 by Sai7musha, edited by Information Processing Society of Japan, PP13-96-PP13-9
9) etc.

According to this, this type of associative memory device requires an associative memory element having a configuration in which each memory element that stores information is provided with a coincidence detection circuit that checks whether the stored content matches the search information. Therefore, compared to memory elements used in ordinary writing devices that are accessed by supplying an address indicating the storage location of desired data, conventional associative memory elements have a more complex structure and cost several bits per bit. It had the disadvantage of being ten times as large.

In order to eliminate this drawback, an associative memory device has been considered in which a normal memory element is used in the information storage section and a match detection circuit is provided for each word.

However, searching this associative memory device has the drawback of requiring a number of search operations corresponding to the number of bits.

Further, the search information is an address input and a first normal storage element stores data information, and the data information or read output of the first normal storage element is used as an address input and a first normal storage element stores the search information. An associative memory device using two ordinary memory elements is disclosed in Japanese Patent Laid-Open No. 49-73039. However, although this associative memory device has the advantage of being able to be constructed using ordinary memory elements, as the number of bits of search emotion or data information increases, the number of memory elements required increases significantly, resulting in an increase in price. have.

[Purpose of the invention]

The object of the present invention is to easily solve the above-mentioned conventional drawbacks and to provide a high-speed, large-capacity, and low-cost associative memory device that is constructed of ordinary memory elements that are accessed by supplying an address.

Another object of the present invention is to provide an associative memory device capable of performing a search operation while masking a portion of search information.

Another object of the present invention is to provide an associative memory device that allows searching not only for matching but also for size relationships.

[Structure of the invention]

Therefore, according to the present invention, the following content addressable memory device can be obtained. That is, a storage means in which storage elements are arranged in a matrix, a row selection means that takes input data as input and whose output connects to each row selection line of the storage means, and a row selection means that takes registered addresses as input and whose output selects each column of the storage means. Column selection means connected to the line; write data generation means for inputting input data and supplying write data inverted at a row designated by the input data to the write data line for each row of the storage means; and a read output of the storage means. an associative memory comprising a temporary storage means for storing the output, a search condition processing means for determining whether this output and the next read output of the storage means match a given search condition, and an encoding means for connecting the output I. a device, a counting means for counting the number of input data, a memory means in which memory elements are arranged in a matrix, the input data and the output of the counting means are input, and the output is connected to each row selection line of the memory means. a row selection means; a column selection means which takes the registered address as input and whose output is connected to each column selection line of the storage means; and a column selection means which takes the input data as input and selects write data to be inverted at the row specified by the input data for each row of the storage means. write data generation means for supplying the write data line to the write data line; temporary storage means for storing the read output of the storage means every time input data is given; an associative memory device having search processing means for taking in the next read output and determining whether or not these conform to a given search condition; and a Φ encoding means connected to this output; a plurality of row selection means that take input data as input and whose outputs are connected to each row selection line of the storage means; and a plurality of row selection means that take registered addresses as input and whose outputs are connected to each column selection line of the valley storage means. A plurality of column selection means are connected, and the input data is input, and write data that is inverted at the row specified by the input data is written to each row of the storage means.A plurality of write data connected to the write data line is generated.This output and the next of the storage means. search condition processing means for determining whether or not the read output of the search condition 4C is met; second temporary storage means for storing the output of the search condition processing means; and second temporary storage means for storing the output of the search condition processing means. The associative memory device is an associative memory device comprising an encoding means which receives the output of the second temporary storage means as an input, and a decoding means connected to the reset input and output of the second temporary storage means selected by the output of the encoding means.

〔Example〕

The present invention will be explained in more detail below using the drawings.

FIG. 1 is an explanatory diagram of an embodiment of an associative memory device according to the first invention. This associative memory device receives input data 101 and search conditions 102, and outputs a search address 162 in which data satisfying the search conditions 102 is stored.
0, a row selection means 120 connected to this by a row selection line 121, which drives all the row selection lines 121 during the registration operation, and drives the row selection line 121 specified by the data 101 during the search operation; Means and each column selection, 1i51131
A column selector R130 that drives the column select line 131 designated by the registration address 132 during a registration operation and drives all column select lines 131 during a search operation, and a storage means 1.
It is connected to the storage means 110 through the write data 1lA 141 that supplies write data to the storage elements of each row of 10, and the write data line 141 designated by the input data 101 is connected to
A write data generating means 140 supplies write data with an inversion from 0'' to #1'' or from "1'" to Register 1 serves as a temporary storage means for
45, this output 115 and the next read signal 116 as inputs, and a search condition processing means 150 that outputs whether or not they satisfy the search conditions; this output m52 as input; 11'' matching signal 16 if included
1 as well as a search address 162 indicating the location of "1".

The storage means 110 is constituted by a normal storage element that is accessed by adding an address indicating a storage location of desired data. Assuming that the storage structure of this content addressable memory device is N word bits, the storage structure of the storage means 110 is 2 antagonist N bits.
That is, 2'17 words and N bits. Also,
The number of bits of input data 101 is M bit registration address 1
32 and the number of bits of the search address 162 is L Og, N bits.

The basic operation of this content addressable memory device consists of a registration operation and a search operation. Input data 101 is given as registration information during a registration operation and as search information during a search operation. Furthermore, the search condition given as the search condition data 102 can be selected from large, small, match, and any combination thereof. The registration operation and search operation will be sequentially explained below.

In the registration operation Cζ, the operation mode signal 103 of "1" indicating the registration operation, the registration address 132 and the input data 10
Registration information is given as 1. By the operation mode signal 103 of '1'', the row selection means 120 drives all the row selections 7iJ i 21 of the storage means in parallel, and the column selection means 13
0 selectively drives only the column selection line 131 of the storage means 110 specified by the registered address 132.

FIG. 2 is an explanatory diagram of the storage contents of the storage means 110, and also serves as an explanatory diagram of write data 141 generated by the write data generation means 140.

The upper row is specified by input data 101 having the smallest value. Write data generation means 140 using FIG.
I will explain. The write data generation means 140 receives input data 101 as registration information and inputs the input data 101.
The storage means 11 (b) supplies write data whose data is inverted from the row designated by 7 to each row. Assuming that the registration information is A, the write data generating means 140 generates write data 141 in which the rows specified by the value greater than or equal to the value of A are "1" and the rows corresponding to the value less than or equal to the value A are "0". The write data 141 is stored in the column of storage means designated by the registration address 132 as shown in FIG. 2 in response to the write pulse signal 104.

The registration operation is performed through the above operations. During the search operation, the operation mode signal 103 of "O" indicating the search operation is activated.
Search information is also given as input data 101.

Furthermore, the search condition processing means 150 includes search condition data 10.
2 is supplied. Due to the operation mode signal 103 of “0”,
The row selection means 120 sequentially selects two rows and selects the column selection means 13.
0 performs parallel reading of all column selection lines 131 of storage means 110. First, the storage means 110 outputs the contents of one line specified by the search information as a read signal 116. This read signal 116 is taken into the register 145 by a first clock signal 146 applied in synchronization with the input data 101.

Next, when a row shift signal 122 is applied to the row selection means 120, the row selection means 120 selects a row specified by a value that is 1 smaller than the value of the input data 101.

Therefore, the storage means 110 outputs the contents of the next higher row as the read signal 116. Storage means 11
Since information is stored in 0 as shown in Figure 2,
The output 115 of the register 145 and the read signal 116 for the column in which registered information matching the search information is stored are "1,0" respectively. The output 115 of register 145 and the read signal 116 for the column
1.1", '0.0'.

Note that when registration information having a value of zero is registered, "1" is stored in all rows of the column specified by the registration address 132 of the storage means 110. In this state, a search operation using the search information of zero is performed. Then, the contents of the 0th row of the storage means 110 are read.Then, the row selection means 120 after being supplied with the row shift signal 122 does not drive any of the row selection lines 121.Therefore, the read signal 116 is It becomes “0′. 7゛Output of this register 145''115 and read signal 116
is supplied to the search condition processing means 150 through the pair I. Further, each search condition processing means 150 is supplied with 3-bit search condition data 102 indicating search conditions of large, small, and matching. The output 115 of the register 145 and the read signal 116 input to each search condition processing means 150 are
Only when the search condition based on the search condition data 102 is satisfied, the search condition data 150 is “11 search result signal 1”.
52 and supplies it to the encoding means 160.

FIG. 3 shows search conditions and a register 145 that generates a search result signal 152 of 1, which means that the search conditions are satisfied.
The correspondence between the output 115 and the read signal 116 is shown. As shown in FIG. 3, the search condition for small is satisfied when the output 115 of the register 145 and the read signal 116 are "0,0", and the search condition for small or match is "0,0" or "1". .1'' Output 115 of register 145 and read signal 1
Satisfied in 16 cases.

The encoding means 160 inputs the search result signal 152, and if it contains the search result signal 152 of "1", it outputs the search result signal 152 of "1" together with the matching signal 16].
A search address 162 indicating the location of is output to the external device. The matching signal 161 indicates that the search information and information satisfying the search conditions are stored in the storage means 110, and the address or column thereof is indicated by the search address 162.

As explained above, this associative memory device can be configured as an associative memory device of N words and bits by using the storage means 110 of 2M+words and N bits of ordinary storage elements, resulting in a reduction in price. Furthermore, the search operation is performed twice and the registration operation is performed in one memory access, allowing high-speed operation. Furthermore, search operations can be performed under various search conditions including size relationships, etc., thereby providing a highly functional associative memory device.

FIG. 4(a) is an explanatory diagram of one embodiment of the row selection means 120 used in the associative memory device of FIG. This row selection means inputs input data 101 serving as search information, and includes a decoder 410 that inputs information with a large value as the input data 101 and outputs "l"lζ of the output located at the lower level of the 8th type, and the two adjacent The upper and lower outputs are input A and B, respectively.
a selection circuit 420 that is connected to the input and selectively outputs one of them in accordance with the row shift signal 122; and an OR gate 430 that performs the logical sum of this output and the operation mode signal 103, and whose output is connected to the row selection line 121. Prepared and configured.

During the registration operation, an operation mode signal 103 of l' is applied. Therefore, this row selection means drives all row selection lines 121 by OR gates 121. During the search operation, “
An operation mode signal 103 of 0' and a row shift signal 122 of "0" are initially applied. The selection circuit 420 selects the A input by the "0" shift signal 122. Therefore, it drives the row selection line 121 specified by the input data 101 given as search information. When signal 122 is applied, selection circuit 420 selects the B input. Therefore, this row selection means drives the row selection line 121 that is one line above the previously driven row selection line 121. However, if zero input data 10Lt≦is input, none of the row selection lines 121 is driven.

FIG. 4(b) shows the row selection means 12 of the associative memory device shown in FIG.
FIG. This row selection means takes in input data 101, and includes a counter 440 that decrements the value by 1 according to the row shift signal 122, a decoder 450 connected to this output, and a logical sum of this output and the operation mode signal 1υ3, so that the output is m[ ] 121.

During the registration operation, the operation mode signal 103 of "1" is given, and all eight goods 121 are driven by the OR gate 460. During the search operation, the operation mode signal 103 of "0" is given, and the input given as search information data 1
01 is taken into the counter 440. Input data 101
If the number of bits in the counter 440 is M bits, the number of bits in the counter 440 is +1) bits. The topmost dot 441 of counter 440 connects to the enable input of decoder 450. First, the decoder 450 drives the row selection line 121 specified by the search information stored in the counter 440 via the OR gate 460. When the row shift signal 122 is then applied, the contents of the counter 440 become the search information minus one. Therefore, the decoder 450 drives the row selection line 121 that is one line above the row selection line 121 that has been driven so far. However, if zero search information is given,
After the row shift signal 122 is applied, the most significant bit 441 of the counter 440 becomes 1, and each output of the decoder 450 is inhibited. That is, not one row selection line 121 is driven.

FIG. 5 is an explanatory diagram aA of one embodiment of the column selection means 130 used in the associative memory device of FIG. This column selection means includes a decoder 510 that receives the registered address 132 as an input, an inverter 520 that inverts the operation mode signal 103, and performs a logical sum of the output of the inverter 520 and each output of the decoder 516 to select the column of the storage means 110. and an OR gate 530 that drives line 131. During the registration operation, a 1° operation mode signal 103 is supplied, and the decoder 51
0 selectively drives the column selection line 131 of the storage means 110 specified by the registered address 132 via the OR gate 530. Therefore, writing to a specific column of the storage means 110 is allowed.

During the search operation, the operation mode signal 1o3 of "0" is supplied, and the OR gate 530 drives all column selection lines 131 without being influenced by the output of the decoder 510. Therefore, parallel reading of all columns of the memory element R110 is possible. enable.

FIG. 6 is an explanatory diagram of one embodiment of the write data generating means 140 used in the associative memory device of FIG. 1. This write data generation means is composed of a decoder 610 that receives input data 101 as registration information, and an OR gate 620. If the registration information is A, write data line 1
41 is supplied with write data corresponding to the contents of one column of the storage means 110 shown in FIG. That is, the output of the decoder 610 is also supplied to the lower write data line 141 via the OR gate 620, and the write data of "1" is generated on the write data line 141 specified by the value greater than or equal to the registered information.

FIG. 7 is an explanatory diagram of an embodiment of the search condition processing means 150 used in the associative memory device shown in FIG. 1.

This search condition processing means consists of two inverters 710 and 72.
0, three AND gates 730, 740, 750,
The output 115 of the register 145 and the read signal 116 are supplied, and the small condition signal 711 and the match condition signal 712 are supplied as the search condition data 102.
and a large condition signal 713 are supplied. Each AND gate 73
0, 740, and 750 process the small, match, and dog conditions of the search conditions shown in FIG. 3, respectively. For example, the small condition signal 71
Given a search condition of 1° of 1, the search result signal 152 of 1° indicates that the search condition is satisfied only when the output 115 of the register 145 of (0,0) and the read signal 116 are provided. By combining the small condition signal 711, the match condition signal 712, and the large condition signal 713, the search conditions shown in FIG. 3 can be processed.

In addition, in the above explanation, OR gate 420, 530° 630.760 and AND gate 620, 730, 740
, 750 can be replaced with other logic gates such as AND gates and OR gates by setting the logic value "0" to be true.

FIG. 8 is an explanatory diagram of an embodiment of an associative memory device with a second view. This associative memory device can handle search information with a larger number of bits than the associative memory device shown in FIG. 1, and is capable of searching while masking part of the search information and multiple matching processing. Therefore, a search processing means 810 is provided in place of the search condition processing means 150, and an OR gate 820 serving as a masking means, a counter 830 serving as a counting means, and a decoder 840 serving as a decoding means are added.

Assuming that the memory structure of this content addressable memory device is N words and MXK bits, the memory means 110 is composed of memory elements arranged in a matrix of zK rows and N columns. That is, storage means 1
The storage structure of 10 is zffl:xx words and N bits. Further, the number of bits of the counter 830 is Log;2'. Therefore, if the z'AI row, N column, and row arrangement means 110 in FIG.
0 is made up of blocks, and the block designation is performed by the counter 830. -MXK bit search information and registration information is M bit input data 10
The data is divided into K times and sent to the row selection means 120 and the write data generation means 140 in order from the higher order. The registration information sent as K input data 101 is stored in each block of the storage means 110 for each input data 101. For example, 1,4 M cut data Ao, AI, A2 .
Registration information A consisting of AS is stored in the 0th block of the storage means 110 as data AO, in the 1st block as data AI, in the 2nd block as data AZ, and in the 3rd block as data A3, as shown in FIG. .

The registration operation and search operation will be explained in more detail.

First, the four M-bit data AO, At, A shown above
The registration operation of registering registration information A consisting of m and A3 to address J will be described. Here, it is assumed that the data A11 is the upper part of the registration information A, and the data A1 is the lowest part, and the data are supplied sequentially from the upper data AO. Next, a search operation based on the same information will be explained. An initial setting signal 811 is supplied at the start of each image operation, and the search processing means 8
10 and the initial values of the counter 830 are set.

- In the case of a registration operation, an initial setting signal 811 is given, and an operation mode signal 103 of "1" indicating a registration operation and a registration address 132 of address J are first supplied.

As a result, the contents of the counter 830 are cleared and the Oth block of the storage means 110 is designated. Next, registration information A
When data AO, which is the upper part of
The write data line 141 specified by the value of ll or more is “1”.
The write data is stored. Since the counter 830 increments at the rising edge of the clock signal 812, the contents of the counter 830 increment at the end of this write and designate the first block of the storage means 110.

Through the above operations, partial data A6 of registration information A is convolved. In this way, the partial data write operation is performed using input data 100. This is done by providing a write pulse signal 104 and a clock signal 812. The registration information A is registered by performing the write operation of the partial data four times for the data AO1A"HA"IA3A3 big data 101.

FIG. 9 is an explanatory diagram of the storage contents of the storage means 110. As explained above (these four parts 7-ta AO).

Registration information A8 consisting of Ax, At, As Registration address 5
When the registration operation is performed, data as shown in the figure is stored in one column of the storage means 110. That is, in each block in one column, 11'' is stored in the row specified by "*At", which is equal to or greater than the value of AmA3.

In this manner, the partial data write operation in the registration operation of the content addressable memory ia is performed in the same manner as the registration operation of the content addressable memory device shown in FIG.

Next, the operation when a search is performed using the same search information A in a state where the registration information A7JS address J is registered will be described. Although this associative memory device can perform a search operation by masking a part of the search information, a search operation in which a mask signal 813 of "0'' is first supplied and no mask processing is performed will be described.

In the search operation, an operation mode signal 103 of "0" is supplied. Further, an initial setting signal 811 is applied to set the contents of the counter 830 and the search processing means 810 to initial values.

Next, partial data Ao of search information A, A1. A
z and A s are input sequentially as input data 101. When inputting each partial data, input the row shift signal 122 of "θ'" and the first clock signal 146,
Next, the row shift signal 122 of 11'' and the second clock signal 812 are input.
20 is data AO and A of the first block of the storage means 110.
Row selection lines 121 specified by data obtained by subtracting 1 from O are sequentially driven. The contents of the storage means 110 connected to the former row selection line 1211 are loaded into the register 145 by the first clock signal 146, and then the contents of the storage means 110 connected to the latter row selection line 121 are outputted as a read signal 116. Ru. The output 115 of the register 145 and the read signal 116 are taken into the search processing means 810 at the rising edge of the second clock signal 812.

Further, the contents of the counter 830 are also determined by the second clock signal 81.
It is incremented at the rising edge of 1 and specifies the next first block.

As a result, a search operation is performed for partial data 80. Similarly, a search operation is performed for partial data A 1 and A zA3. Since the storage means 110 stores the contents shown in FIG. 9, the partial data A O,
Register 145 for A I , A 2 , As
output 115 and read signal 116 mean a match (1
．． 0).

Next, search information A, M-bit partial data AO,
It is assumed that the data is divided into All...-, Ai, .-+AK-1 and supplied as input data 101. The output 115 of the register 145 and the read signal 116 of the storage means 110 for each partial data Ai are the partial data of the registration information and the search information A encoded and stored in the columns of the storage means 110 as shown in FIG. The results of comparison with partial data Ai are shown. Output 115 of register 145 at the rising edge of second clock signal 812 for partial data Ai
Assuming that Bi is Bi and the read signal 116 is Ci, the results of comparison between the partial data Ai and the partial data of the registration information stored in each column of the storage means 110, that is, the matching relationship Et, the major relationship Li, and the minor relationship 3i are as follows. As is clear from Figure 3, each (
It is expressed by equations 1), (2), and (3).

Ei-Bi -c: (s-o~ni-1)-...(1
)Li-ni-cic;-o~ni-1)...(2)Si
mBi, Ci (is-Q-x-t) - (3)
Furthermore, the matching relationship E, major relationship, and minor relationship S, which are the comparison results between the search information @A and the registered information stored in each column CcJ/& of the storage means 110, are (4), (5), ( 6
) can be expressed by the formula.

E-EO-El...-Fji...
E K -1-・(4) L-LO+L1-Eo+-=+
Li −EOjEl ・−・−1Bi−1+−−−−・
+LK-1 Fist EO・Elshima・−・・−El ・−・・
−♂Ex−z ・−・−(
5) f; -8O+81-Ey +-・+f3i -EO
−El ・−−−−−El−1+・・・・・・+SK−
Yi・EO-El・−・・Eil−・−・Ex−2・
...B6) Also, if the search condition data 102 serving as the search condition is given as the match condition signal EC9, the large condition signal LC2, the small condition signal SC, the search result R indicating whether the search condition is satisfied or not. is determined by equation (7).

The R-E-EC+L-LC+S-8C-()) search processing means 810 inputs the output 115 of the register 145 and the read signal 116 for the partial data Ai in synchronization with the second clock signal 812, and performs the above (1). The search result R is obtained by the logical operation of formula (7) and is sent to the search result signal 15.
Output as 2.

Encoding means 1 which receives this search result signal 152 as input
60 operates similarly to the associative memory device of FIG. 1 and generates a search address 162 and matching signal 161.

When the storage means 110 stores a plurality of pieces of registered information that satisfy the search condition, that is, in the case of multiple matching, a plurality of search result signals 15 of "1" indicating that the search condition is satisfied are stored.
Generates 2. The encoding means 160 outputs the search result signal 1.
52 and search address 1 with high priority.
61 is generated. This search address 162 is sent to the decoder 8
40 is also supplied. External devices use this search address 16
2, the reset signal 841 is sent to the decoder 840.
to be applied. Each output 842 of the decoder 840 is connected to an internal reset input of each search processing means 810. Therefore, decoder 840 converts the reset signal to search address 16.
It is supplied to the internal reset input of the search processing means 810 designated by 2. The output of the search processing means 810 to which the reset signal 841 is supplied, that is, the value of the search result signal 152 changes from "1" to "0". Therefore, encoding means 1
60 is the search result signal 15 of “1” with the next highest priority.
2 is output to the outside as the next search address 162. In this way, a plurality of search addresses that satisfy the search conditions can be generated one after another, making it possible to process multiple matching. 9 hesitations (Onosusa 5a ship 0♂10%.

The above description of the search operation is an operation in which masking is not applied to the search information. This content addressable memory device can perform a search by masking the search information for each partial data.

This means that a mask signal 813 of "1" is applied to the OR gate 820 at the time when the partial data to be masked is input, and a second clock signal 813 is applied to the search processing means 810 at the same time.
This is done by prohibiting the application of 12. Partial data A
When the clock signal to the search processing means 810 is masked when inputting i, the above (4), (5), (6)
) in the formula Ei, Li.

A comparison result is obtained by removing Si and masking the partial data Ai.

As described above, according to the present invention, an associative memory device of N words and MXK bits can be constructed using the ordinary storage means 110 of 24+rxK words and N bits.

Compared to the associative memory device shown in FIG. 1, which requires a normal memory element of 2fj, xx words and N bits as the storage means 110, this associative memory device can be constructed with a smaller capacity memory element and is inexpensive. bring about change.

Furthermore, as search conditions, it is possible to search not only for matching relationships but also for size relationships, or to search by masking part of the search information.

FIG. 12 is an explanatory diagram of an embodiment of the search processing means 1120 used in the associative memory device of FIG. 11.

This search processing means is the first. Second. Third register 101
0°1020.1030 and Antogame h 1040,
1041, 1042° 1043.1044.1045 and or gate 1050, 1051° 1052.1053
and inverters 1060 and 1061.

This search processing means uses the above equation (4) to calculate the intermediate result of the comparison process E'-E'``E''... Ei (1-θ ~ -1) - (8) L/i story: [,i-E'i-t
(iFu 0 ~ 111E'-1 ■ 1... (9) S'iMaSi-E'i-t (imO~ ni -1,
E'-txt)--Ql is introduced, and each of equations (4), (5), and (6) is calculated using the following αυ and U equations.

E! -1...-(Lυ) Before each partial data is input to E', the initial setting signal 811 is input.
is applied, the first register 1010 is set, and the second register 1010 is set. The third registers 1020 and 1030 are reset.

The first register 1010, the AND gate 1040, and the inverter 1061 are synchronized with the second clock signal 812,
The logical operations of equations (1) and (8) are executed for each partial data Ai. When all partial data Ai have been input, (
1) The logical operations of equations (8) are also completed, and the matching relationship E represented by the αυ equation remains in the first register 1010. Similarly, the second register 1020, ORKATE 1050, AND gate 1041, and first register 1010 are (2)
(9), executes the logical operation of the α2 expression and sets the second register 1
Major relationships are stored in 020. In addition, the third register 1030, the OR gate 1051, and the AND gate 1042
and the inverter 1060 and the first Regis momme 010 are (3
) A 0-hole, α-4-hole logical operation is executed, and the minor relation S is stored in the third register.

The first of these. Second. Third register 1010, 102
The matching relationship E, major relationship, and minor relationship S stored at 0° 1030 are the matching condition signal 712 that becomes the search condition data 102.
, large-related signal 713. With the small relation signal 711 (logical operation based on the force formula is AND gate 1043, 1044.10
45 and Oagoo 1-1053. This search result R is output as a search result signal 152 from Oagoo 1-1053. This signal 152 becomes 1 when the search condition is satisfied.

Initial setting signal 8]1 is supplied at the start of the search operation and sets the first register 1210 and the second register 1210. Third register 12
20. Perform a reset of 1239. On the other hand, the reset signal 11 supplied via the decoder 1110 in FIG.
12 is the first. Second. Third register 1210, 1220
゜1230 reset. As a result, the search result signal 152 is forcibly cleared to "O".The encoding means that receives the search result signal 152 as an input can then generate the next search address.

- FIG. 11 is an explanatory diagram of an embodiment of an associative memory device according to the third invention. This content addressable memory device can handle search information and registration information with a larger number of bits than the content addressable memory device shown in FIG. 1, and can perform search and registration operations faster than the content addressable memory device shown in FIG. It is possible. For this purpose, the associative memory device shown in FIG. 1 includes a storage means 110 divided into blocks, a row selection means 120, a write data generation means 140, and a register 14 serving as a temporary storage means.
5, this output 115, and each storage means 110. A search condition processing means 1110 which receives the read signals 116 and determines whether or not they satisfy the search conditions determined by the search condition data 102, and a search result signal 15 supplied from the search condition processing means 1110.
2, a search result register 1120 for temporarily storing 2, an encoding means 160, a decoder 840, and a registered address 1.
32 as an input and selectively drives the column selection line 131 of each storage means 110.

Assuming that the memory configuration of this content addressable memory device is N words MXK bits, each memory means 110 has 2''4.E rows and N columns of memory elements, that is, 2''!, i words and N bits, and the number thereof is 2''! In the content addressable memory device shown in FIG. 8, the number of bits is expanded by expanding the number of words in the storage means 110.
In this content addressable memory device, the number of bits is expanded by increasing the number of storage means 110.

Therefore, the storage means 110 in the associative memory device of FIG.
The flocks are stored in each storage means 11 in this associative memory device.
Corresponds to 0. The MXK-bit search information and registration information are divided into M-bit input data 101, each of which is supplied to the row selection means 120 and write data generation means 140 in parallel. In FIG. 11, it is set to -3.

Registration operation (at this time, the registration information supplied by the three input data 101 is stored and registered in each memory hand 9110 as shown in FIG. 2 for each input data 101).

During the search operation, the contents of each storage means 110 corresponding to each input data 101 supplied as search information are taken into each register 145, and the output 115 and the read signal 1
16 is supplied with the search condition processing means 111 (H).The search condition processing means 1110 receives the output 116 of the register 145.
It is checked whether the read signal 116 satisfies the search conditions determined by the search condition data 102, and the result is used as the search result signal 1.
52 to the N-bit search result register 1120. The search result register 1120 receives this search result signal 1.
52 is captured by the second clock signal 812. The contents of the search result register 1120 are stored in column 4 of the storage means 110? j
/II indicates whether or not the stored registration information matches the search information given as input data]01 and the search conditions given as search condition data 102 with "1" and "0". A match signal 161 indicating that the search result register 1120 holds the content of "1" indicating a match, and a search address 162 indicating the bit position thereof are outputted by the encoding means 160.This search address 16
2 indicates an address where registered information that satisfies the search conditions is stored.

At the time of multiple matching when multiple addresses are matched, multiple bits in the search result register 1120 hold "l". In this case, a reset signal 841 is applied. The decoder 840 converts the reset signal 841 to the search address 162.
is supplied to the reset input of the bit of the search result register 1120 specified by . As a result, the bit of the search result register 1120 corresponding to the previously output search address 162 is reset. Therefore, the encoding means 160
outputs the next search address 162. The external device monitors the matching signal 161 and applies a reset signal 841 when it becomes 0, thereby obtaining all search addresses 162 during multiple matching.

Furthermore, in this way, the content addressable memory device can expand the number of bits of search information and registration information without significantly increasing the storage capacity of the storage means 110. Furthermore, search operations, multiple matching processing, and masking processing based on search conditions that include not only matching conditions but also magnitude relationships are also possible. Furthermore, in the associative memory devices of FIGS. 8 and 11, registration information and search operations are input in multiple steps, but with this associative memory device, input can be made in parallel.

Therefore, the search operation can be performed by accessing the storage means 110 once, increasing the speed.

FIG. 12 is an explanatory diagram of one embodiment of the search condition processing means 1110 used in the associative memory device of FIG. 11. This search condition processing means consists of 9 anime games) 1210-12
18, three orcates 1220 to 1222, and three decoders 1230, 1240, and 1250. This search condition processing means receives the same bit output 115 of each register 145, the read signal 116 of the ffj-column of each storage means 110, and the search condition data 102 from the outside.
as the match condition signal 712. A large condition signal 713° and a small condition signal 711 are input. In the associative memory device shown in FIG. 11, N search condition processing means are provided corresponding to each column of the storage means 110.

This search condition processing means reduces the number K of storage means 110 to −3.
Then, by the logical operations of equations (1) to (6), the matching relationship E,
I'm looking for major relationships and minor relationships S. Further, a matching condition signal 712. which is a search condition. A logical operation is performed between the large condition signal 713 and the small condition signal 111 based on equation (7) to determine whether or not the search condition is satisfied, and this is generated as the search result signal 152. Each decoder 1230,1
240 and 1250, the output 115 of the register 145 and the read signal 116 are input, and partial data A of the search information A is obtained.
Coincidence relationship Ell for O, A I, A z.

El, E2 and major relationship LO, Ls, Lx and minor relationship So,
81.

S2 is calculated based on equations (1), (2), and (3). The first step is to perform massing of each partial data. Second
．． The third mask signal 1231, 1241.1251 is provided to the enable input of each decoder 1230, 1240.degree. 1250. The output of the decoder to which the mask signal is supplied becomes "1", and the matching relationship Ei, major relationship li, and minor relationship Si for the input partial data Ai are (4),
It can be removed from equations (5) and (6). That is, the partial data Ai is masked.

ANDQUES 1210 and 1215 execute the logical operation of equation (4) to find the matching relationship E. Also, and gate 1
210, 1211.1213 and or gate 1220 are (
6) Based on the logical operation of the expression, find the minor relation S and use the AND gates 1210, 1212.1214 and the OR gate 122.
1 determines the major relationship based on equation (5). Further, the AND gates 1216, 1217, and 1218 and the OR gate 1223 calculate a search result R indicating whether or not the search condition is satisfied by the logical operation of equation (7), and output this as the search result signal 152.

The search result signal 152 obtained in this manner is supplied to the search result register 1120 in FIG.

Note that such logical operations can be easily realized using a gate array, FROM, or the like.

FIG. 13 is an explanatory diagram of an embodiment of an associative memory device according to still another invention. This associative memory device aims to have a larger capacity, and utilizes a plurality of associative memory units 1310 corresponding to the associative memory devices shown in FIGS. 1, 8, and 11, and a plurality of output means 1320 connected thereto. , an encoding means 1330 connected to each output means 1320, and a decoder 1340 applying a write pulse signal 104 to each content addressable memory unit 1310. Each associative memory unit 1310 receives a mask signal 813 . First clock signal 146. Second clock signal 812. Search condition data 102. Initial setting signal 811. Input data 1
01. Operation mode signal 103. A registered address 1329 row shift signal 122 is supplied.

At the time of registration, each associative memory unit 1310 receives an operation mode signal 103 of "1" indicating the registration operation.Initial setting signal 811
, second clock signal 812 . Input data 101. The registered address 132 is supplied in the same manner as the associative memory devices of FIGS. 1, 8, and 11. The registered address 132 becomes the lower address of this content addressable memory device, and the upper address is supplied as the upper registered address 1341 to the decoder 1340ζ. The upper registration address 1341 specifies the associative memory unit l-1310, and the registration address specifies the column of the storage means 110 within the associative memory unit 1310. A write signal 1342 instructing writing to the content addressable memory device is supplied to a decoder 1340.

The decoder 1340 selectively supplies the write signal 1342 to the associative memory unit 1310 specified by the upper registered address 1341 as the write pulse signal 104 .

This decoder 1340 transfers the registration information to the associative memory unit l-1310 selected by the upper registration address 1341.
will be registered.

During the search, the mask signal 813. 1st. Second clock signal 146, 812 . Search condition data 102. Initial setting signal 811, input data 101. Operation mode signal 1031
A row shift signal 122 is supplied to each content addressable memory unit 1-1310 in parallel. An associative memory unit l- in which search information given as input data 101 and information matching the search conditions given as search condition data 102 are registered.
1310 outputs a matching signal 161 of "1" and a search address 162. The output means 1320 is a plurality of associative memory units) 1310 outputs a matching signal 161 of "1"
When this occurs, the associative memory device located on the left l-1
310 and outputs the search address 162 from the associative memory unit l-1310 with the higher priority as the lower search address 1321.

In order to prioritize the associative memory unit 1310, an enable signal 1322 is supplied from the left to the right output means 1320j. “0” enable signal 1322
The output means 1320 supplied with the internal search address 1
When the output buffer 62 is placed in a high impedance state, the enable signal 1322 of "0" is generated.
The output means 1320 supplied with the enable signal of l' and the matching signal 161 of '1' outputs the search address 162 and also generates the enable signal 1322 of 'θ'. Therefore, the output sofa in the output means 1320 located on the right side of the output means 1320 is brought into a high impedance state. The output means 1320 that outputs the search address 162 outputs the matching signal 161 as the first matching signal 1.
Output means 1 which outputs as 323 and is located on the right side of it
320 generates a first matching signal 1323 of "0".

The encoding means 1330 inputs the first matching signal 1323 and outputs a second matching signal 1331 indicating whether or not the first matching signal 1323 of "1" is input, and a first matching signal 1331 of "1".
Upper search address 13 indicating the location of matching signal 1323 of
32 to an external device. Second matching signal 1331
indicates that search information and information satisfying the search conditions are registered in this associative memory device, and the upper search address 13
32 indicates the position of the registered content addressable memory unit 1310. Further, the lower search address 1321 is the search address 162 of the content addressable memory unit) 1310. That is, it shows the columns of the storage means 110.

The external device monitors the second matching signal 1331, reads the upper search address 1332 and the lower search address 1321, and further outputs the first reset signal 1324 to each output means 1.
320. The first reset signal 1324 is used to obtain a search point L/S for information with the next highest priority when a plurality of matching pieces of information are registered in the associative memory device. The output means 1320 that outputs the search address 162 outputs the first reset signal 1324!
Associative memory unit 13101 as J upper set number 841
This is supplied, and the next search address 162 is output.

In this way, this associative memory device is shown in Figures 4, 8, and 1.
It is constructed using the associative memory device shown in FIG. 1, and the number of words can be easily expanded, resulting in a large-capacity associative memory device.

FIG. 14 is an explanatory diagram of an embodiment of the output means 320 used in the associative memory device of FIG. 13. This output means is an output buffer 1410. J:, 3 AND gates 14
20, 1430, 1440, and an inverter 1450.

The search address 162 is the left output means 132 o75>
When the enable signal 1322 and matching signal 161 input to the enable input terminal 1460 are both “1”, the lower search address 13 is outputted via the output buffer 1410.
It is output as 21. In this case, matching signal 161 is output as first matching signal 1323 via AND gate 1430. Further, an enable signal 1322 of "0" is output from the enable output terminal 1470. Therefore, the output buffers 1-i i and o of the right output means 1320 connected to the enable output terminal 1470 are in a high impedance state. .

Further, the first reset signal 1324 is output from the AND gate 14
20 as a reset signal 841 to the content addressable memory unit 1310. “1” first matching signal 13
The output means 13204 located on both sides of the output means 1320 for generating the first reset signal 132
4 does not add AND gate 1420 and reset signal 8
41 is not output. Therefore, if the content addressable memory unit 1310 to which the reset signal 841 is applied has multiple matching, the content addressable memory unit 1310 generates the search address 162 having the next highest priority.

In addition, it is an associative memory unit! 310, when the associative memory device of FIG. 1 is used, the mask signal 813, the second clock signal 812. The initial setting signal 811 is no longer necessary,
When the associative memory device shown in FIG. 11 is used, the initial setting signal 811 is not required.

FIG. 15 is an explanatory diagram of an embodiment of an associative memory device according to still another invention. This associative memory device stores keys and data as pairs in an associative memory section 1510 and a data memory section 15, respectively.
20, and by giving a key, the data paired with it can be obtained.

The associative memory unit 1510 corresponds to the associative memory device shown in FIG. 1, FIG. 8, FIG. 11, or FIG. It consists of a normal storage device.

The associative memory unit 1510 includes a reset signal 841. Mask signal 813. 1st. Second clock signal 146, 812
゜Input data 101. Initial operation mode signal 103, registered address 1329 row shift signal 122. The write signal 104 is input, and the write signal 104 and address information 154 are input to the data storage section 1520.
0.

Write data 1550 is input. Selective times msa.

outputs the registration address 132 during the registration operation and the search address 162 during the search operation as address information 1540 to the data storage unit 1520.

In the registration operation, paired keys and data are given as each manual data 101 and write data 1540, and are stored in an associative memory unit 1510 and a data storage unit 153, respectively.

The address specified by the registered address 1η is stored. When the same registered key is given as input data 101 and a search operation is performed, the registered address 132 is retrieved from the associative memory.
The same search address 162 is output. This search address 162 is sent to the data storage unit 1 via the selection circuit 153.
520 becomes the address information 1540. Therefore, data paired with the key from the data storage unit 15 2 ob> is output as read data 1560.

For example, if a registration operation is performed using "apple" as a key and "red" as data, and then a search operation is performed using "apple" as a key, "red" is output as read data 1560. Furthermore, after registering "red" as a key and "apple" as data, when a search operation is performed by giving "red" or "apple" as a key, read data 156
Each "apple" or "red" is output as 0.

In this way, this associative memory device can perform the above associative operation at high speed. Further, after storing the age as a key and the name as data in the associative memory unit 1510 and the data storage unit 1520, respectively, and then giving the age as the key, the corresponding name is found as read data 1560. In this case, if a matching relationship or a major relationship is given as a search condition, the names of people who are the same age as the key or the names of people who are older than the key can be immediately obtained, respectively. In other words, with this content addressable memory device, a search for size relationships for unsorted information can be performed immediately, making it possible to realize a high-speed database system.

〔Effect of the invention〕

As described above, the content addressable memory device according to the present invention can be constructed using inexpensive ordinary memory elements that are accessed by supplying an address indicating the storage location of desired data. The associative memory device of FIG. 1 with N words and bits can be constructed with a normal storage element of 2MV words and N bits as the storage means 110, and the associative memory device of FIG. 8 or FIG. It can be constructed as a normal memory element of xK words and N bits or a normal memory element of 2 words and N bits. Therefore, 1 bit RA'
Using M semiconductor technology - for example, 4 kilowords 8
The bit content addressable memory device shown in FIG. 1 or the 16 kiloword 24 bit content addressable memory device shown in FIGS. 8 and 11 when divided into 8 can be realized with one chip. An example of a generally commercially available semiconductor associative memory is Signetix (3i'g).
netics) Inc.'s content addressable memory IC8220 has 4 words and 2 bits, but the content addressable memory device according to the present invention can be said to have an extremely large capacity. The process can be completed by accessing the memory elements one to several times, and is faster than conventional word-serial/bit-parallel or word-parallel/bit-serial associative memory devices.

Furthermore, search operations and multiple matching processes that mask part of the search information are also possible. Furthermore, as search conditions, it is possible to search not only for matching conditions but also for relationships between dogs and pets. Furthermore, the number of words can be easily expanded, and a content addressable memory device with a larger capacity can be realized.

That is, according to the present invention, a high-speed, large-capacity, low-cost, and highly functional associative memory device can be realized. When such an associative memory device is used as a storage device of an information processing system, it is possible to realize an information processing system that can perform associative processing and comparison calculation processing in take base, button recognition, artificial intelligence, etc. at high speed.

In the above explanation, '1'' is stored in each column of the storage means 110 in a row specified by a value greater than or equal to the value of registered information. This is an example of a storage method; It is also possible to store "1" or "0" in the row 1 designated by The means 140, the search condition processing means 150, 1110, and the search processing means 810 can be easily modified according to the method of storing write takes in the storage means 110. That is, the above description does not limit the scope of the claims of the present invention. It's not a thing.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an embodiment of an associative memory device according to the first invention, and FIG. 2 is a diagram showing a method of storing registered information in the storage means 110 of FIG. 1. FIG. 3 is an explanatory diagram showing the relationship between search conditions, register outputs, and read signals; FIG. 4 is an explanatory diagram of one embodiment of the row selection means; FIG. 5 is an explanatory diagram of one embodiment of the column selection means; FIG. 6 is an explanatory diagram of one embodiment of the writing means, FIG. 7 is an explanatory diagram of one embodiment of the search condition processing means, and FIG. 8 is an explanatory diagram of one embodiment of the associative memory device according to the second invention. , FIG. 9 is an explanatory diagram of the storage contents of the storage means 0 of the associative memory device in FIG. 8, FIG. 10 is an explanatory diagram of an embodiment of the search processing means 810 of the associative memory device in FIG. The figure is the third
12th explanatory diagram of an embodiment of the associative memory device according to the invention of
The figure shows the search condition processing means 111 of the associative memory device in FIG.
13 is an explanatory diagram of an embodiment of an associative memory device according to another invention; FIG. 14 is an explanatory diagram of an embodiment of the output means 1320 of the associative memory device of FIG. 13; FIG. 15 is an explanatory diagram of an embodiment of an associative memory device according to still another invention. 110--Storing means, 120--Line selection means, 130-4
selection means, 140 - write data generation means, 145
...Register, 150.1110...Search condition processing means, 160.1330--Encoding means, 410,
450,510°610.840,1230,1240
, 1250.1340-decoder, 420°1530
---Selection circuit, 440, 830---Counter, 112
゜...Search result register, 131O--one associative memory unit 1320--output means, 1410--output huffer, 151--one associative memory section, 1560--take storage section. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure δ Figure 9 Figure 1O Figure 11 Figure 17 Figure 13

Claims (12)

[Claims] (1) A storage means in which storage elements are arranged in a matrix, a row selection means whose input data is input and whose output is connected to each row selection line of the storage means, and a registered address is input and whose output is selection of each column of the storage means. Column selection means connected to the line; write data generation means for inputting input data and supplying write data inverted at a row designated by the input data to the write data line for each row of the storage means; and a read output of the storage means. , search condition processing means for determining whether this output and the next read output of the storage means match a given search condition, and encoding means connected to this output. Characteristic associative memory device. (2) The row selection means drives all the row selection lines of the storage means in parallel at the time of registration, and sequentially drives the row selection line designated by the input data and the row selection line next to it at the time of search. An associative memory device according to claim 1. (3) The column selection means drives the column selection line of the storage means specified by the registration address at the time of registration, and drives all the column selection lines in parallel at the time of search, Associative memory device described in. (4) The write data generating means is composed of a decoder connected to the input data and an OR gate connected to each output of the decoder, and the OR gate generates a logical sum between the output of an adjacent OR gate and the output of the decoder. An associative memory device according to claim 1. (5) A counting means for counting the number of input data, a memory means in which memory elements are arranged in a matrix, and a row in which the input data and the output of the counting means are input, and the output is connected to each row selection line of the memory means. a selection means; a column selection means which takes the registered address as an input and whose output is connected to each column selection line of the storage means; and a column selection means which takes the input data as an input and writes write data that is inverted at the row designated by the input data to each row of the storage means. write data generation means for supplying the write data line to the write data line; temporary storage means for storing the read output of the storage means every time input data is given; What is claimed is: 1. An associative memory device comprising: search condition processing means for taking in the read outputs of and determining whether or not these conform to given search conditions; and encoding means connected to the outputs. (6) The row selection means drives all the row selection lines of the storage means in parallel at the time of registration, and sequentially drives the row selection line designated by the input data and the row selection line next to it at the time of search. An associative memory device according to claim 5. (7) The column selection means drives the column selection line of the storage means designated by the registered address at the time of registration, and drives all the column selection lines in parallel at the time of search. The associative memory device described. (8) The write data generating means is composed of a decoder connected to the input data and an OR gate connected to each output of the decoder, and the OR gate generates a logical sum between the output of an adjacent OR gate and the output of the decoder. An associative memory device according to claim 5. (9) A plurality of storage means in which storage elements are arranged in rows and columns; a plurality of row selection means that take input data as input and whose outputs are connected to each row selection line of the storage means; and a plurality of row selection means that take registered addresses as input and output each A plurality of column selection means connected to each column selection line of the storage means, and a plurality of write data connected to the write data line of the storage means for inputting input data and inverting write data at a row specified by the input data to each row of the storage means. A generating means, a plurality of first temporary storage means for storing the read output of the storage means each time input data is given, and whether or not this output and the next read output of the storage means match a given search condition. a second temporary storage means for storing the output of the search condition processing means; an encoding means for inputting the output of the second temporary storage means; and decoding means whose output is connected to the reset input of the second temporary storage means selected by the output. (10) The row selection means drives all the row selection lines of the storage means in parallel at the time of registration, and sequentially drives the row selection line designated by the input data and the row selection line next to it at the time of search. An associative memory device according to claim 9. (11) According to claim 9, the column selection means drives the column selection line of the storage means specified by the registered address at the time of registration, and drives all column selection lines in parallel at the time of search. The associative memory device described. (12) The write data generating means is composed of a decoder connected to the input data and an OR gate connected to each output of the decoder, and the OR gate generates a logical sum between the output of an adjacent OR gate and the output of the decoder. An associative memory device according to claim 9.