JP2786364B2 - Associative memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an associative memory device capable of retrieving data according to contents, and more particularly to a large-capacity CAM (Content Addressable Memory).
The present invention relates to a low power consumption type content addressable memory device having a novel structure for expanding the memory width of a content addressable memory having a match search circuit provided for each of a plurality of memory words for the purpose of multiple memory words. .

[0002]

2. Description of the Related Art Conventionally, an associative memory, that is, an associative memory, has been used as a semiconductor memory circuit having a function of detecting coincidence between search data and stored data in parallel with all bits and outputting a storage address or data of the matched data. Parallel CAM (Content access memory: Content
Addressable Memory is well known (Takuo Sugano, supervised by Tetsuya Iizuka, "Design of CMOS Ultra LSI" Baifukan, P.
176-P177).

[0003] Associative memories are searched by content, not by physical memory address. Each of the memory cells constituting the associative memory includes a 1-bit memory, like the other memories, and has a 1-bit memory with a predetermined number of bits.
A memory word is configured. In a CAM memory match search, the memory words in the CAM memory are a series of,
It is compared in parallel with a known search pattern consisting of data bits (search data pattern). When a match is detected, the physical address of the cell containing the matched data is determined. A major advantage of CAM memories is that a full memory match search is performed quickly, substantially in the time required to perform a one word search.

Many conventional associative memories are limited by design to a specific memory width, and cannot be expanded by cascading the memories. Therefore, such a CAM memory is limited in the number of bits for a given word to a certain maximum value, for example, 16 bits, and a search data pattern larger than 16 bits for this CAM memory is not reliably searched for, so that There is a problem that its use is also restricted.

[0005] Some conventional CAM memories are designed so that a match search can be performed only with a fixed-length search data pattern. However, this has a problem that a match search cannot be performed at all with a variable-length search data pattern.

For this reason, a device for expanding the bit width of an associative memory has been proposed in Japanese Patent Publication No. 63-5839 as a "memory width expanding device of an associative memory". As shown in FIG. 9 , the conventional bit width expansion device 100 disclosed here outputs circuits 102, 104a, 104b,... For outputting a match signal for each memory word of the CAM memory array.
.., And the first word circuit 102
6 is directly input, and the second word circuit 104a is provided with an AND gate 112a for outputting a logical product of the output of the preceding latch circuit 108 and the second word match search line 110a, and the output And a latch circuit 114a for latching a logical product. The third and subsequent circuits 104b,..., And the AND gates 112b,.
4b, and these circuits 102, 104a,
Are connected in cascade.

When a match search is performed in the device 100, first, a latch circuit 108, 1 provided for each memory word is provided by an initialization signal from a signal line 116.
.. Are initialized, and after the second memory word, AND gates 112a, 112b,.
The logical product of the output signal initialized by... And the match search lines 110a, 110b,... Of the next memory word is converted to the final match search signal of each memory word. Was output as. here,
When the bit width is expanded, a logical AND of the previous match search signal and the current match search signal, which are similarly latched, is used to finally obtain a match search signal whose bit width is expanded. . That is, for example, if the CAM memory is an 8-bit cell, if two types of 8-bit search data are successively searched for twice, the 16-bit search data will be matched. Twice 8
Latch circuit 114 after match search of bit search data
When the output signals of a, 114b,... are coincidence signals, a total of 16 bits of the 8-bit cell of the memory word from which the coincidence signal was output and the 8-bit cell of the memory word immediately before the same.
It has been detected that the memory data of the bit memory cell matches the above-mentioned 16-bit search data. In this manner, the bit width is extended by repeating the match search of the search data of the predetermined bit and detecting the match signal from the latch circuit.

[0008]

In the bit width expansion device 100 disclosed in Japanese Patent Publication No. 63-5839 shown in FIG. 9 , one match search line (110a) and one AND line are required for each memory word. Gate (112
a) and a latch circuit (114a) for storing the result, so that this device cannot be adapted to a CAM structure having one match detection circuit for a plurality of memory words. There was a problem. Therefore, a larger capacity CAM having a bit width extension function
There is a problem that cannot be realized.

On the other hand, a large capacity CAM is divided into blocks each having a plurality of addresses in order to reduce power consumption, and data is searched in time series. There were problems such as the inability to deliver results.

An object of the present invention is to provide a large-capacity content addressable memory device which solves the above-mentioned problems of the prior art, enables data search with low power consumption, and has a memory density extension function with a higher degree of integration. is there.

[0011]

Means for Solving the Problems] To achieve the above object, the present invention provides double each comprising a plurality of memory words
Logical address memory blocks and these multiple logical addresses
Between memory words of the same order in the address memory block
And a common match search circuit, respectively,
Time series sequentially for each of the logical address memory blocks
In an associative memory device which performs matching search, the matching search circuit, each of the plurality of logical address memory block
Search data D _t input in sequential chronological people to search results R _t of each of the plurality of logical address memory block
A search result holding means for holding for each memory word, the search results searched held by the holding means results R _t and the next search data D _{t + 1} Result R _{t + 1} and the logical operation top or bottom of the and a logical operation means for performing between adjacent logical address of the memory word, further wherein the logical addresses of the least significant or most significant logical address memory above or below the logical address memory blocks among blocks in the block of memory words the search result includes a inter-block holding means for holding the R _t, adjacent the
An associative memory and wherein the logical address of the memory word is configured to when crossing between the logical address memory block is performed using the search results R _t, which is holding the logic operation by the inter-block holding means To provide.

[0012] Here, the present invention is the above content addressable memory device, the matching search circuit further plurality of logical addresses of menu of the same rank the plurality of logical address memory block
One provided for Moriwado, the plurality of logical address
Search results from the memory block
A match search amplifier for detecting a signal state of a match search line to be detected, and one temporary holding means connected to the logical operation means for temporarily holding a result of the search. Connected to the input of a logical operation means, the temporary holding means is connected to each of the search result holding means, and each of the search result holding means and the lower one of the higher logical addresses of two adjacent logical addresses are connected. preferably configured to sequentially connecting the other input of the logic operation means of the logical address. Moreover, the the temporary storage means, a working register, the search results holding unit is preferably a store register. Further, it is preferable that the temporary holding unit is a working data latch and the search result holding unit is a data store latch.

[0013]

The associative memory device of the present invention has a high integration and a large capacity C.
A plurality of logical address memory blocks in which data is sequentially searched in chronological order because a match search amplifier is used in common for a plurality of memory words for the purpose of realizing AM, or for the purpose of reducing power consumption. Are divided into Here, when performing a match search for search data,
First successively chronologically to search the search data D _t for a plurality of logical address memory block, holds the result in the search result holding means provided with R _t per each memory word of each block all .

Next, the next search data _{Dt + 1} is searched. Prior to the search of one logical address memory block, the lowest (in the case of descending search of the block) or the highest (the search of the block) of this block is performed. results of the logical address in the case of increasing the search) are kept on the R _t to the block between the holding means. Thus, the search for the search data D _{t + 1} is performed for the logical address memory block, and the search result R _{t + 1 is obtained.}
Search results held in the search result holding means adjacent the upper or lower logical address performs a logical operation between R _t and, holding the operation result R _e in the search result holding means as a search result, instead of R _t I do. In this way, even if the content (holding data) of the search result holding means of the lowest or highest logical address of this block is not the previous search result _Rt , the previous search result _Rt is retained between the blocks. , The search data D of the next block
Search by _{t + 1} can be performed correctly. That is,
Between memories of logical addresses adjacent across blocks, the search result _{Rt + 1} of the highest or lowest logical address of the next block and the lowest or highest of the previous block held in the block holding means are stored. A logical operation can be performed with the higher-order previous search result _Rt . Thus, the search for the search data _{Dt + 1} is performed in all the blocks.
Further, the search for the next search data D _{t + 2} can be performed in exactly the same manner.

Therefore, in the associative memory device of the present invention, the search between blocks can be accurately performed even if the memory is divided into a plurality of logical address memory blocks, even if the memory capacity is large. Can be done with
Further, a high-speed and higher-integration memory width extending function can be realized at low cost.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The associative memory device according to the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a conceptual diagram showing the configuration of an embodiment of an associative memory device according to the present invention. FIG. 2 includes a bit width extension function used in the content addressable memory device shown in FIG.
FIG. 2 is a schematic configuration diagram of one embodiment of a match search circuit block including a match detection circuit provided for one memory word; FIG. 3 is a schematic configuration diagram showing logical address memory blocks divided into a plurality (four) for each of a plurality (n) of memory words of the associative memory device of the present invention shown in FIG.

As shown in FIG. 1, an associative memory device (CAM memory) 10 of the present invention includes a CAM memory array 12,
It includes a data and mask drive block 14, an address decoder 16, a coincidence detection circuit block 18 including a bit width extension function most characteristic of the present invention, and an address encoder 20. The CAM memory 10 has a memory mode that performs the same function as a memory such as a RAM or a ROM, and a mode that performs a match search. Here, as shown in FIG. 2, in order to simplify the description,
A case where one match search line is provided for every four memory words of the AM memory array 12 and a match search circuit including one match search amplifier connected thereto is provided will be described as a typical example. However, it is not limited to this.

First, in a normal memory mode, an arbitrary address in the CAM memory array 12 is designated by the address decoder 16 and reading or writing of the content of the address is performed via the data and mask driving block 14. At this time, the coincidence detection circuit block 18 and the address encoder 20 are not driven.

Next, in the match search mode, a mask signal specifying a bit position to be searched for a match and search data are input from the data and mask drive block 14. At this time, the content of each memory word in each divided logical address memory block of the CAM memory array 12, that is, the memory data of the memory cell at each bit position is compared with the masked search data. As described above, in the example shown in FIGS. 2 and 3, the CAM memory array 12 is provided with one match search line for every four memory words, and four logic words each including n memory words (memory addresses). It is divided into address memory blocks. The signal state (“1” H (high) or “0” L (low)) of the match search line indicates that the search data (search data pattern) matches the content of the memory word (memory data pattern). Here, typically, a match signal when a match occurs is indicated by “1” (H (high)), and a mismatch signal when there is a mismatch is “0” (L (low)). ), But of course the reverse is also possible.

Next, the match detecting circuit block 18, which is the most characteristic of the present invention, includes a plurality of matching detecting circuits and logical address memory blocks each receiving a search result of a match search line of each memory word, which will be described in detail later. And outputs a match signal (“1”) from the memory address where the match occurs. When the bit width expansion is not performed, the above-described match signal (“1”)
Alternatively, any match search signal of the mismatch signal (“0”) is output as it is, but when the bit width is extended,
The match signal H ("1") is output only when the search data matches the memory data with respect to the expanded bit width, and the other signals are output with the mismatch signal L ("0"). . Here, if the bit width is expanded, the immediately higher memory word address may be sequentially output.
These match signals are sequentially input to the address encoder 20 from the match signal corresponding to the lowest address among the memory addresses in which the match occurs, and the address in which the match occurs corresponds to the lowest address (or the bit width is expanded). Are determined in order from the higher memory word address. Here, since one match search line is provided for a plurality of memory words, that is, four memory words, a memory word address for simultaneously performing a match search for a plurality of match search lines by the address decoder 16 is assigned to each match search line. A logical address memory block is formed by selecting one of the four connected memory words one by one.

The match search circuit block 18 shown in FIG.
A match search circuit 22 (2) provided for every four memory words having a predetermined bit width (memory width) composed of memory cells of predetermined bits of the CAM memory array 10 shown in FIG.
2 ₁ ,..., 22 _n ) and the search result R _t of a predetermined memory word of the match search circuit 22 _{n at} the time of match search of the previous search data D _t when the bit width is expanded is used as the next search data D _{t + 1}
Before the next memory word group (logical address memory block) is searched for, a register 24 between blocks and a gate 25 for controlling this register are provided. Here, the match search circuit 22 includes a first match search circuit 22
_1, ..., have either the same configuration of the n matching search circuit 22n, each of the four memory words 26 (W
(1,1), W (2,1), W (3,1) and W
(4,1),... W (1, n), W (2, n), W
(3, n) and W (4, n)), one sense amplifier (match search amplifier) 28 (28 ₁ ,...)
.., 28 _n ) and the match search line 30 (30 ₁ ,..., 3)
0 _n ), control gate 32 (32 ₁ ,..., 32)
_n ) and the working registers 34 (34 ₁ ,..., 3)
4 _n ) and data registers (store registers) provided corresponding to the respective memory words 26 described above.
36 (36 ₁₁ , 36 ₂₁ , 36 ₃₁ and 36 ₄₁ ,..., 3
6 _1n , 36 _2n , 36 _3n, and 36 _4n ) and transistors 37 (37 ₁₁ , 37) for controlling them (that is, for controlling the timing of writing and reading).
_21, 37 ₃₁ and 37 _41, ......, 37 _1n, 37 _2n, 37
_3n and 37 _4n ). Transistors 37 ₁₁ , ...
..., 37 _1n , 37 ₂₁ , ..., 37 _2n , 37 ₃₁ , ...
, 37 _3n and 37 ₄₁ ,..., 37 _4n are all connected to control signal lines Z ₁ , Z ₂ , Z ₃ and Z ₄ , respectively.
By these, W (1,1) of the memory word 26,.
, W (1, n), W (2,1), ..., W (2,
n), W (3,1),..., (3, n) and W
Control is performed at the same timing as the selection timing of (4, 1),..., W (4, n).

The signal line 44 ₁ which extends from the output of One block between registers 24 of the control gate 32 _of the input end is connected. On the other hand, the working register 34 ₁
The output line 35 ₁ is branched and is connected to one of the matching search circuit 22 ₂ of the control gate 32 and _second input terminals by a signal line 44 _2. Thus, the match search circuit 22 in the preceding stage
The output line 35 of the working register 34 is branched and connected to the input terminal of the control gate 32 of the match search circuit 22 at the subsequent stage. That is, matching search circuit 22 (22 _1,
.., 22 _n ) are cascaded. Finally, the output line 35 _n of the working register 34 _n of the match search circuit 22 _n branches and is connected by a signal line 45 to one input terminal of the gate 25, in the illustrated example, the AND gate 25.

The sense amplifier 28 detects the signal state of the match search line 30. Here, if the signal state of the match search line 30 matches, the sense amplifier 28 detects "1" H (high). If they do not match, "0" L (low) is detected.

The control gate 32 (32 ₁ ,...,
32 _n ) is the previous search data D of the adjacent upper memory word address held in the data register 36.
A logical operation means for performing logical operation on the search result R _{t + 1} to _t Result R _t and retrieval data D _{t + 1} of the current of the memory word addresses, at least in this case seeks a logical product It is. Therefore, the control gate 32
_{(32 1, ......, 32 n} ) , as shown in FIG. 3, only AND gate _{38 (38 1, ......, 38} n) may comprise only, FIG. 4, FIG. 5 As described above, the AND gate 38 and the through transistor 40 (40 ₁ ,..., 4)
0 _n ). Here, when the control gate 32 is constituted only by the AND gate 38 as shown in FIG. 3, it is necessary to initialize all the data registers 36 before starting the match search.

The CAM memory device 10, the address decoder 16, the same matching search circuit 22 (22 ₁ having the matching search block 18 having such a configuration, ...
... one of 22 _n) in Tsugaru set of four memory words
One memory word is selected one by one from each match search circuit 22 to form one block, in which a match search is performed simultaneously. The CAM 10 using the match search circuit block 18 shown in FIG.
According to the logical address arrangement, as shown in FIG.
Four logical address memory blocks LAB1, LAB2, LAB3 each of which has a group of memory words (addresses).
And LAB4. That is, as the logical address memory block LAB1, n memory addresses W (1, 1),.
, W (1, n) are LAB2, and n memory addresses W (2, 1),..., W (2, n) are LAB3.
, W (3, 1),..., W
(3, n), n memory addresses W (4,1),..., W (4, n) are selected as LAB4 and are divided into blocks. These blocks are called pages or sheets. In the present invention, between these pages, that is, between blocks, are connected by the inter-block register 24 and the gate 25.

Referring to FIG. 3, one embodiment of CAM 10 of the present invention is shown.
An example of the search operation will be described. First, everything
Working register 34 (34₁ , ……, 34_n ),
Data register (36₁₁, ……, 36_4n) And block
The inter-work register 24 is to be initialized. That is,
Data "1" (H,
High) is held. First search data D_t 
Perform a match search for. First, the logical address of the first page
All memory words 26W of the memory block LAB1
(1,1),..., W (1, n) are simultaneously driven,
Memory data and retrieval of memory cells of these memory words
Data D_t Is searched for a match.
Match search line 30₁ , ..., 30_n Signal status changes
Then, the signal states are respectively transferred to the sense amplifiers 28.₁ ,…
…, 28_n And the search result (R _t,₁₁, ... R_t,
_1n) To the control gate 32 (32₁ ,…
…, 32_n). Where the control gate
32 is an AND gate 38 (38₁ , ……, 38_n )
And an AND gate 38 (38₁ , ……, 38_n )of
One of the input terminals is the initialized inter-block level.
Jista 24₁ , Data register 36₁₁, ……, 36_1n-1
All data “1” held in all
And the AND gate 38 (38₁ , ……, 38
_n ) Is the search result R_t(R_t,₁₁, ……, R_t,_1n)
Output as is. And this search result R_t (R
_t,₁₁, ……, R_t,_1n) Is the respective working registry
Tab 34 (34₁, ……, 34_n ), And
Control signal line Z driven in the same manner as₁ To
Therefore, the transistors 37 which are all turned on at the same time
(37₁₁, ……, 37_1n) Through each memory
Word 26 (W (1,1),..., W (1, n))
The corresponding data register 36 (36₁₁, ……, 36_1n)
Will be retained. Thus, the logical address memory of the first page
Search data D of block LAB1_t Match search by
Complete.

Next, the logical address block L of the second page
Search data D of AB2_t Search for matches in exactly the same way
And as a result R_t (R_t,_{twenty one}, ……, R_t,_2n)
Each memory word 26 (W (2,1),..., W
(2, n)) corresponding to the data register 36 (36_{twenty one},
............ 36_2n) And end the search for the second page
You. Thus, the logical add on pages 3 and 4
Search for less memory blocks LAB3 and LAB4
Also the result R_t (R_t,₃₁, ……, R_t,_3n), R _t (R
_t,₄₁, ……, R_t,_4n) To the data register 36
(36₃₁, ……, 36_3n), 36 (36₄₁, ……, 36
_4n) And exit.

Next, a match search of the search data D _{t + 1} is performed. First, here, before starting a match search of the logical address memory block LAB1 of the first page, the inter-block register 24 ₂ between the first page and the second page (in FIG. 3, it is in the block LAB2 of the second page). In the last (lowest) memory word W of the block LAB1 of the first page
(1, n) previous results for R _t (R _{t, 1n)} to hold the. Thereafter, as in the previous time, all the memory words 26 of the logical address memory block LAB1 are driven, a match search between the search data and the memory data is performed, and the signal state of the match search line 30 is detected by the sense amplifier 28. As a result, , That is, the memory word 26 (W (1, 1),..., W (1,
n) search result _{Rt + 1} ( _{Rt + 1} , ₁₁ ,..., _{Rt + 1} , _1n )
Are input to the AND gate 38 (38 ₁ ,..., 38 _n ). The search result R _{t + 1} and the immediately preceding memory word 26 input as the other input of the AND gate 38 (the first row is the inter-block register 24
₁ , W (1,1),..., W (1, n−
1)) of the previous search results held in the data register R _t (1 row interblock register 24 _first resist data, for example R _{t, 4n,} 2 Subsequent rows, R _{t, 11,} ...... ,
R _t , _1n-1 ), and the operation result Re (Re)
_11, ..., holds Re _1n) in the working register 34, data register 36 (36 ₁₁ via the transistor 37 which is turned on by a signal line Z _1, ..., 36 _1n)
Store in

Next, a search based on the search data Dt _{+ 1} of the block LAB2 of the second page is performed.
Inter-block register 243 between page 3 and page ₃
To the lowest memory word W of the block of the second page
Store the previous search result R _t (R _t , _2n ) of (2, n).

Thereafter, in the same manner as described above, the second page
A match search for each memory word in block LAB2 is performed.
Here, the uppermost memory word 26 (W (2,1))
First match search circuit 22₁ On Match Search Behavior by
I will tell. One input of the AND gate 38 is, of course,
The highest memory word of the block LAB2 of the page
Search data D for C (W (2,1))_{t + 1} This time by
Search result R_{t + 1} (R _{t + 1},_{twenty one}). The other input
Is the data D of the block LAB1 on the first page _{t + 1} By
Register 24 before the search₁ Stored in
The lowest memo of block LAB1 on the first page
Retrieval data D of reward 26 (W (1, n))_t by
Search result R_t (R_t,_1n). As a result, these two
Search result R_t (R_t,_1n) And R_{t + 1} (R_{t + 1},_{twenty one}) And logic
The product is taken and the operation result Re (Re,_{twenty one}) In the same way
Data register 36_{twenty one}Store in Therefore, the block
The memory word 26 (W (1,
n) and the logical operation of W (2, 1)) are
When the search for B1 is completed, the data register 36_1nIs rewritten
Continuous data D_t And D_{t + 1} Do about
Can be. Therefore, straddling between blocks like this
Bit width expansion should also be performed on adjacent memory words.
Can be.

The memory words 26 (W (2,2),..., W (2, n) in the second and subsequent rows of LAB2 on the second page are stored in the same manner as described above.
(2, i (2 ≦ i ≦ n) search result R _{t + 1} (R _{t + 1} , _2i )
If the previous search result _{R t (R t, 2i-} 1) of the immediately preceding memory word W (2, i-1) ANDs the Results of processing _{Re (Re 22, ......, Re} 2n ) Is similarly stored in the data register 36 (36 ₂₂ ,..., _362n ). Thus, the second search of the block LAB2 of the second page is completed. In this way, the third page and the fourth page can be similarly searched.

When a subsequent match search is performed, the search may be performed in exactly the same manner. At this time, each of the data register 36, the search according to the search result R _t and the second retrieval data D _{t + 1} according to the first retrieval data D _t result R _{t + 1}
And the logical operation result Re is stored, and the logical operation result is stored in the search data (D _t + D
_The third match search may be performed as a search result by _{t + 1} ). To further expand the data bit width,
What is necessary is just to continue the above match search operation.

Here, the inter-block register 24 (24
_1, 24 _2, 24 _3, 24 ₄₎ is between each logical address memory block is always necessary, physically it may be four, but the control inputs of one register 24 to the gate 25 may be selectively used as a between the four blocks register 24 _{1-24 4.} By doing so, costs can be reduced, the area of hardware can be reduced, and high integration can be achieved. Here, as the inter-block register,
Anything can be used as long as it can store 1-bit data, and it may be a data latch circuit. In the gate 25, one input is stored data of the data register 36 of the previous block, while the other input is a switching timing for moving the search block or searching for the next data.

Next, as the control gate 32, FIG.
Instead of using only the AND gate 38 as shown in FIG. 5, a composite gate may be formed as shown in FIGS. The control gates shown here (32 ₁ , 32 ₂ ,
...) Are AND gates 38 (38 ₁ , 38 ₂ ,.
..) And through transistors 40 (40 ₁ , 40 ₂ ,...) That pass through each of them. Here, in order to input the control signal C, all the through transistors 40 (4
0 ₁ , 40 ₂ ,...) Are connected. The working register 34 (34 ₁ , 34 ₂ ,...)
Are paired data latch circuits 46 (46 ₁ , 46
_2, ...) and 48 (48 _1, 48 _2, is constituted by ...), the first data latch circuit 46 (46 _1, 46 _2,
...) Are output to the subsequent stage match search circuit 22 (22 ₂ ,...).
..) Are inputted to the AND gate 38 (38 ₂ ,...).

Next, the match search circuit block 18 shown in FIG.
An example of the operation will be described. First, the control signal
Signal C is controlled as “active” (“1” H (high))
The signal is input to the signal line 42 and the through transistor 40 (40
₁ , 40_Two ,...) Are turned on. Here, register 2
It is assumed that data H (“1”) is latched in No. 4.
Here, the first search data D_t Perform a match search for
The through transistor 40 (40₁ , 40_Two , 40
_Three ,...) Are on, the match of the match search line 30
The search signal is detected by the sense amplifier 28 and the search result R
_t Is a through transistor 40 (40₁ , 40_Two , ……)
Through the AND gate 38 (38₁ , 38_Two ,
...), And directly passes through the working register 34 (34).
₁ , 34 _Two , ......). That is, the composite game
To 32 (32₁ , 32_Two , ……) is the search result R_t To
Let it through as it is. Next search data D_{t + 1} Search for matches
Prior to this, the control signal line 42 is
Active (“0” L (low)) is input,
Transistor 40 (40₁ , 40_Two , ……) are all off
It is. Here, the second search data D_{t + 1} Search for matches by
And the match search signal is changed to match search line 30 (30₁ , 3
0_Two ,...).
_{t + 1} Is detected. Here, the through transistor 40 is
Since everything is off, the search result R_t Is the AND gate 38
Is input to one of the input terminals. On the other hand, AND gate 3
8 is connected to the previous working register 34.
The latch data of the first latch circuit 46 of FIG.
And the AND gate 38 receives the control signal A
The logical AND with the search signal is taken, and as a result, the operation result Re and
And outputs it to the working register 34.

With this configuration, the working registers 34 (34 ₁ ,..., 34 _n ) need not be initialized. FIG. 5 is a circuit diagram showing a specific configuration of control gate 32 and working register 34 shown in FIG. The control gate 32 shown in FIG. 5 has a transistor 50 (5
0 ₁ , 50 ₂ ,...), And turns on the transistor 50 only when the control signal B is input to the control signal line 52.
The output of the control gate 32 is the working register 3
4 may be input.

As can be seen from FIGS. 4 and 5, the working register 34 includes two data latch circuits 46 and 48 as shown in FIG. In that two data latch circuits are required, the data register 36
The same applies to. Therefore, in another embodiment of the present invention, as shown in FIG. 7, each register is constituted by a data latch circuit, and one register is constituted by two latches used at the same time, thereby reducing hardware cost. Can also.

In the register configuration shown in FIG. 7, in place of the working register 34 shown in FIGS. , And each data register 36 (36
₁ , 36 ₂ , 36 ₃ , 36 ₄ ) instead of store latch 5
6 (56 ₁ , 56 ₂ ,...), And a data interference suppression gate 58 is interposed between the working latch 54 and the store latch 56. In this configuration, the working latch 54 that always outputs the search result and the result store latch 56 (56) that stores the result of each block.
₁ , 56 ₂ ,...) To form two latches, which are used as registers. Here, the control signal A is extracted by the gate 58 and the store latch 56.
(56 ₁ , 56 ₂ ,...).

FIG. 8 shows a match search circuit 23 (23i) used in the associative memory device of the present invention to which the configuration shown in FIG. 7 is applied. In the match search circuit 23, compared with the match search circuit 22 shown in FIG. 2, the working register 34 has a working latch 54 and data registers 36 ₁ , 36 ₂ , 36.
_3, 36 ₄ store latch 56 _1, 56 _2, 56 _3, 5
Has a 6 _4, register been simplified construction amount corresponding to a latch, it is possible to achieve a higher integration than the cost down and the hardware.

Although the associative memory device according to the present invention has been described in detail with reference to various embodiments, the present invention is not limited to this, and is provided for one match search line, that is, one match search line. The number of memory words searched for by the match search circuit is not limited to four.
Any number, such as 16, 32, is acceptable. Also,
In the associative memory device of the present invention, one block is divided into a plurality of logical address memory blocks including a plurality of memory addresses, and the plurality of logical address blocks are highly integrated due to physical arrangement (layout). In order to realize a large-capacity CAM, a match search circuit is used in common for a plurality of memory words, and as a result, the match search circuit is not necessarily divided into a plurality of logical address memory blocks that are sequentially searched in chronological order. To reduce power consumption,
It may be for dividing data into a plurality of logical address blocks and sequentially performing data search in time series.

Although the associative memory device according to the present invention has been described above with reference to various embodiments as the match search circuit block applied thereto, the present invention is not limited to these embodiments, and the gist of the present invention is as follows. Of course, various design changes, changes, and substitutions can be made without departing from the above.

[0043]

As described in detail above, according to the present invention,
Due to the problem of physical layout, a match including a search line and a circuit for extending the bit width of a sense amplifier (control gate, register, latch, etc.) for a plurality of memory words to realize a highly integrated large capacity CAM. Even if the search circuit is shared and divided into a plurality of logical address memory blocks which are inevitably searched sequentially in time series, the purpose is to reduce the power consumption at the time of search in order to obtain a large-capacity CAM. Even when dividing into a plurality of logical address memory blocks, even if an adjacent memory address for performing a logical operation straddles between two blocks, each block is sequentially stored in time series. Search can be performed accurately.

In the match search circuit of the content addressable memory device of the present invention, a working latch for outputting a match search result and a store latch for storing the search result are used instead of the working register and the data register. In the case where the register is constituted by two latches, one of the store latches of each block, the hardware cost can be reduced, and higher integration can be achieved.

Therefore, according to the present invention, it is possible to provide a large-capacity CAM having a low power consumption data search function, a low cost, a high speed, a high integration degree and a memory width extension function.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of an associative memory device according to the present invention.

FIG. 2 is a schematic configuration diagram of an embodiment of a match search circuit block used in the content addressable memory device according to the present invention.

FIG. 3 is a schematic configuration diagram of an embodiment of a configuration of a logical address memory block of the content addressable memory device according to the present invention.

FIG. 4 is a partial configuration diagram of another embodiment of the match search circuit used in the content addressable memory device according to the present invention.

FIG. 5 is a partial configuration diagram of another embodiment of the match search circuit used in the content addressable memory device according to the present invention.

FIG. 6 is a partial configuration diagram of another embodiment of the match search circuit used in the content addressable memory device according to the present invention.

FIG. 7 is a partial configuration diagram of another embodiment of the match search circuit used in the content addressable memory device according to the present invention.

FIG. 8 is a schematic configuration diagram of another embodiment of a match search circuit block used in the content addressable memory device according to the present invention.

FIG. 9 is a configuration diagram of a conventional bit width expansion device of an associative memory device.

[Explanation of symbols]

Reference Signs List 10 associative memory device 12 associative memory array 14 data and mask drive block 16 address decoder 18 match detection circuit block 20 address encoder 22, 22 ₁ , 22 _n match search circuit 24 register between blocks 25 gate 26 memory word (memory address) 28 sense Amplifiers (match search amplifiers) 30, 30 ₁ , 30 ₂ , 30 _n Match search lines 32, 32 ₁ , 32 ₂ , 32 _n Control gates 34, 34 ₁ , 34 ₂ , 34 _n Working registers 36, 36 ₁₁ , 36 _{21 , 36 31, 36 41, 36} 1n, 36 2n, 36 3n, 36 4n data register _{38,38 1, 38 2, 38 n} AND gates 40,40 _1, 40 _2, 40 _n through transistor 42,44,44 ₁ , 44 ₂ , 44 _n , 52 Control signal lines 46, 48 Data latch circuit 50,50 _1, 50 ₂ gate transistor 54 working latches 56 _1, 56 _2, 56 _3, 56 ₄ store latch 58 control gate

Claims (4)

(57) [Claims] 1. A plurality of memory words each comprising a plurality of memory words.
Logical address memory block and these logical addresses
Between memory words of the same order in the
Each having a common match search circuit;
Time series for each of the physical address memory blocks
An associative memory device for performing a match search, wherein the match search circuit is configured to search data D _t sequentially input in time series to each of the plurality of logical address memory blocks.
A plurality of results of search R _t the logical address memory blocks
A search result holding means for holding each respective memory word phrases, the search result R which is held by the retrieval result holding means
_t and Memoriwa logical address adjacent top or bottom to a logical operation to the search result R _{t + 1} of the next search data D _{t + 1}
And a logical operation means for performing among over de further Memoriwa logical address of each bottom or the top of the logical address memory above or below the logical address memory block among blocks of the block
Includes interblock holding means for holding the search result R _t of over de, by the inter-block holding means said logical operation in a case where the logical address of the memory word adjacent straddle between the logical address memory block Retained search result R
An associative memory device characterized by being configured to perform the processing using _t . 2. A content addressable memory device according to claim 1, wherein the matching search circuit further plurality of logical addresses of the same order of the plurality of logical address memory blocks Memoriwa
One provided for over-de, the plurality of logical addresses main
Search results from the molybloc are sequentially output in chronological order
A match search amplifier for detecting a signal state of a match search line; and one temporary holding means connected to the logical operation means for temporarily holding a result thereof; Means for connecting the temporary holding means to each of the search result holding means, and the search result holding means and the lower logical address of each of the higher logical addresses of two adjacent logical addresses Characterized in that they are sequentially connected to the other input of the logical operation means. 3. The associative memory device according to claim 2, wherein said temporary holding means is a working register, and said search result holding means is a store register. 4. The associative memory device according to claim 2, wherein said temporary holding means is a working data latch, and said search result holding means is a data store latch.